src/gallium/drivers/swr/swr_screen.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "swr_context.h"
  25 #include "swr_public.h"
  26 #include "swr_screen.h"
  27 #include "swr_resource.h"
  28 #include "swr_fence.h"
  29 #include "gen_knobs.h"
  30
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_defines.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_format.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_cpu_detect.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39
  40 #include "state_tracker/sw_winsys.h"
  41
  42 extern "C" {
  43 #include "gallivm/lp_bld_limits.h"
  44 }
  45
  46 #include "jit_api.h"
  47
  48 #include "memory/TilingFunctions.h"
  49
  50 #include <stdio.h>
  51 #include <map>
  52
  53 /* MSVC case instensitive compare */
  54 #if defined(PIPE_CC_MSVC)
  55    #define strcasecmp lstrcmpiA
  56 #endif
  57
  58 /*
  59  * Max texture sizes
  60  * XXX Check max texture size values against core and sampler.
  61  */
  62 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
  63 #define SWR_MAX_TEXTURE_2D_LEVELS 14  /* 8K x 8K for now */
  64 #define SWR_MAX_TEXTURE_3D_LEVELS 12  /* 2K x 2K x 2K for now */
  65 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14  /* 8K x 8K for now */
  66 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
  67
  68 static const char *
  69 swr_get_name(struct pipe_screen *screen)
  70 {
  71    static char buf[100];
  72    util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
  73                  HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
  74                  lp_native_vector_width );
  75    return buf;
  76 }
  77
  78 static const char *
  79 swr_get_vendor(struct pipe_screen *screen)
  80 {
  81    return "Intel Corporation";
  82 }
  83
  84 static boolean
  85 swr_is_format_supported(struct pipe_screen *screen,
  86                         enum pipe_format format,
  87                         enum pipe_texture_target target,
  88                         unsigned sample_count,
  89                         unsigned bind)
  90 {
  91    struct sw_winsys *winsys = swr_screen(screen)->winsys;
  92    const struct util_format_description *format_desc;
  93
  94    assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
  95           || target == PIPE_TEXTURE_1D_ARRAY
  96           || target == PIPE_TEXTURE_2D
  97           || target == PIPE_TEXTURE_2D_ARRAY
  98           || target == PIPE_TEXTURE_RECT
  99           || target == PIPE_TEXTURE_3D
 100           || target == PIPE_TEXTURE_CUBE
 101           || target == PIPE_TEXTURE_CUBE_ARRAY);
 102
 103    format_desc = util_format_description(format);
 104    if (!format_desc)
 105       return FALSE;
 106
 107    if (sample_count > 1)
 108       return FALSE;
 109
 110    if (bind
 111        & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) {
 112       if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
 113          return FALSE;
 114    }
 115
 116    if (bind & PIPE_BIND_RENDER_TARGET) {
 117       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 118          return FALSE;
 119
 120       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 121          return FALSE;
 122
 123       /*
 124        * Although possible, it is unnatural to render into compressed or YUV
 125        * surfaces. So disable these here to avoid going into weird paths
 126        * inside the state trackers.
 127        */
 128       if (format_desc->block.width != 1 || format_desc->block.height != 1)
 129          return FALSE;
 130    }
 131
 132    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 133       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 134          return FALSE;
 135
 136       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 137          return FALSE;
 138    }
 139
 140    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
 141        format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
 142       return FALSE;
 143    }
 144
 145    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
 146        format != PIPE_FORMAT_ETC1_RGB8) {
 147       return FALSE;
 148    }
 149
 150    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 151       return util_format_s3tc_enabled;
 152    }
 153
 154    return TRUE;
 155 }
 156
 157 static int
 158 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
 159 {
 160    switch (param) {
 161       /* limits */
 162    case PIPE_CAP_MAX_RENDER_TARGETS:
 163       return PIPE_MAX_COLOR_BUFS;
 164    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 165       return SWR_MAX_TEXTURE_2D_LEVELS;
 166    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 167       return SWR_MAX_TEXTURE_3D_LEVELS;
 168    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 169       return SWR_MAX_TEXTURE_CUBE_LEVELS;
 170    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 171       return MAX_SO_STREAMS;
 172    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 173    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 174       return MAX_ATTRIBUTES * 4;
 175    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 176    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 177       return 1024;
 178    case PIPE_CAP_MAX_VERTEX_STREAMS:
 179       return 1;
 180    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 181       return 2048;
 182    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 183       return SWR_MAX_TEXTURE_ARRAY_LAYERS;
 184    case PIPE_CAP_MIN_TEXEL_OFFSET:
 185       return -8;
 186    case PIPE_CAP_MAX_TEXEL_OFFSET:
 187       return 7;
 188    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 189       return 330;
 190    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 191       return 16;
 192    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 193       return 64;
 194    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 195       return 65536;
 196    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 197       return 0;
 198    case PIPE_CAP_MAX_VIEWPORTS:
 199       return 1;
 200    case PIPE_CAP_ENDIANNESS:
 201       return PIPE_ENDIAN_NATIVE;
 202    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 203    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 204       return 0;
 205
 206       /* supported features */
 207    case PIPE_CAP_NPOT_TEXTURES:
 208    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 209    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 210    case PIPE_CAP_TWO_SIDED_STENCIL:
 211    case PIPE_CAP_SM3:
 212    case PIPE_CAP_POINT_SPRITE:
 213    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 214    case PIPE_CAP_OCCLUSION_QUERY:
 215    case PIPE_CAP_QUERY_TIME_ELAPSED:
 216    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 217    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 218    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 219    case PIPE_CAP_TEXTURE_SWIZZLE:
 220    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 221    case PIPE_CAP_INDEP_BLEND_ENABLE:
 222    case PIPE_CAP_INDEP_BLEND_FUNC:
 223    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 224    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 225    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 226    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 227    case PIPE_CAP_PRIMITIVE_RESTART:
 228    case PIPE_CAP_TGSI_INSTANCEID:
 229    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 230    case PIPE_CAP_START_INSTANCE:
 231    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 232    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 233    case PIPE_CAP_CONDITIONAL_RENDER:
 234    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 235    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 236    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 237    case PIPE_CAP_USER_VERTEX_BUFFERS:
 238    case PIPE_CAP_USER_INDEX_BUFFERS:
 239    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 240    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 241    case PIPE_CAP_QUERY_TIMESTAMP:
 242    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 243    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 244    case PIPE_CAP_FAKE_SW_MSAA:
 245    case PIPE_CAP_DRAW_INDIRECT:
 246    case PIPE_CAP_UMA:
 247    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 248    case PIPE_CAP_CLIP_HALFZ:
 249    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 250    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 251    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 252    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 253    case PIPE_CAP_CULL_DISTANCE:
 254    case PIPE_CAP_CUBE_MAP_ARRAY:
 255       return 1;
 256
 257       /* unsupported features */
 258    case PIPE_CAP_ANISOTROPIC_FILTER:
 259    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 260    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 261    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 262    case PIPE_CAP_TEXTURE_BARRIER:
 263    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 264    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 265    case PIPE_CAP_COMPUTE:
 266    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 267    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 268    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 269    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 270    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 271    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 272    case PIPE_CAP_TGSI_TEXCOORD:
 273    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 274    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 275    case PIPE_CAP_TEXTURE_GATHER_SM5:
 276    case PIPE_CAP_TEXTURE_QUERY_LOD:
 277    case PIPE_CAP_SAMPLE_SHADING:
 278    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 279    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 280    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 281    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 282    case PIPE_CAP_VERTEXID_NOBASE:
 283    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 284    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 285    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 286    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 287    case PIPE_CAP_TGSI_TXQS:
 288    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 289    case PIPE_CAP_SHAREABLE_SHADERS:
 290    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 291    case PIPE_CAP_CLEAR_TEXTURE:
 292    case PIPE_CAP_DRAW_PARAMETERS:
 293    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 294    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 295    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 296    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 297    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 298    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 299    case PIPE_CAP_INVALIDATE_BUFFER:
 300    case PIPE_CAP_GENERATE_MIPMAP:
 301    case PIPE_CAP_STRING_MARKER:
 302    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 303    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 304    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 305    case PIPE_CAP_QUERY_MEMORY_INFO:
 306    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 307    case PIPE_CAP_PCI_GROUP:
 308    case PIPE_CAP_PCI_BUS:
 309    case PIPE_CAP_PCI_DEVICE:
 310    case PIPE_CAP_PCI_FUNCTION:
 311    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 312    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 313    case PIPE_CAP_TGSI_VOTE:
 314    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 315    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 316    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 317    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 318    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 319    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 320    case PIPE_CAP_NATIVE_FENCE_FD:
 321       return 0;
 322
 323    case PIPE_CAP_VENDOR_ID:
 324       return 0xFFFFFFFF;
 325    case PIPE_CAP_DEVICE_ID:
 326       return 0xFFFFFFFF;
 327    case PIPE_CAP_ACCELERATED:
 328       return 0;
 329    case PIPE_CAP_VIDEO_MEMORY: {
 330       /* XXX: Do we want to return the full amount of system memory ? */
 331       uint64_t system_memory;
 332
 333       if (!os_get_total_physical_memory(&system_memory))
 334          return 0;
 335
 336       return (int)(system_memory >> 20);
 337    }
 338    }
 339
 340    /* should only get here on unhandled cases */
 341    debug_printf("Unexpected PIPE_CAP %d query\n", param);
 342    return 0;
 343 }
 344
 345 static int
 346 swr_get_shader_param(struct pipe_screen *screen,
 347                      unsigned shader,
 348                      enum pipe_shader_cap param)
 349 {
 350    if (shader == PIPE_SHADER_VERTEX || shader == PIPE_SHADER_FRAGMENT)
 351       return gallivm_get_shader_param(param);
 352
 353    // Todo: geometry, tesselation, compute
 354    return 0;
 355 }
 356
 357
 358 static float
 359 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 360 {
 361    switch (param) {
 362    case PIPE_CAPF_MAX_LINE_WIDTH:
 363    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 364    case PIPE_CAPF_MAX_POINT_WIDTH:
 365       return 255.0; /* arbitrary */
 366    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 367       return 0.0;
 368    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 369       return 0.0;
 370    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 371       return 16.0; /* arbitrary */
 372    case PIPE_CAPF_GUARD_BAND_LEFT:
 373    case PIPE_CAPF_GUARD_BAND_TOP:
 374    case PIPE_CAPF_GUARD_BAND_RIGHT:
 375    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 376       return 0.0;
 377    }
 378    /* should only get here on unhandled cases */
 379    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 380    return 0.0;
 381 }
 382
 383 SWR_FORMAT
 384 mesa_to_swr_format(enum pipe_format format)
 385 {
 386    static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
 387       /* depth / stencil */
 388       {PIPE_FORMAT_Z16_UNORM,              R16_UNORM}, // z
 389       {PIPE_FORMAT_Z32_FLOAT,              R32_FLOAT}, // z
 390       {PIPE_FORMAT_Z24_UNORM_S8_UINT,      R24_UNORM_X8_TYPELESS}, // z
 391       {PIPE_FORMAT_Z24X8_UNORM,            R24_UNORM_X8_TYPELESS}, // z
 392       {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,   R32_FLOAT_X8X24_TYPELESS}, // z
 393
 394       /* alpha */
 395       {PIPE_FORMAT_A8_UNORM,               A8_UNORM},
 396       {PIPE_FORMAT_A16_UNORM,              A16_UNORM},
 397       {PIPE_FORMAT_A16_FLOAT,              A16_FLOAT},
 398       {PIPE_FORMAT_A32_FLOAT,              A32_FLOAT},
 399
 400       /* odd sizes, bgr */
 401       {PIPE_FORMAT_B5G6R5_UNORM,           B5G6R5_UNORM},
 402       {PIPE_FORMAT_B5G6R5_SRGB,            B5G6R5_UNORM_SRGB},
 403       {PIPE_FORMAT_B5G5R5A1_UNORM,         B5G5R5A1_UNORM},
 404       {PIPE_FORMAT_B5G5R5X1_UNORM,         B5G5R5X1_UNORM},
 405       {PIPE_FORMAT_B4G4R4A4_UNORM,         B4G4R4A4_UNORM},
 406       {PIPE_FORMAT_B8G8R8A8_UNORM,         B8G8R8A8_UNORM},
 407       {PIPE_FORMAT_B8G8R8A8_SRGB,          B8G8R8A8_UNORM_SRGB},
 408       {PIPE_FORMAT_B8G8R8X8_UNORM,         B8G8R8X8_UNORM},
 409       {PIPE_FORMAT_B8G8R8X8_SRGB,          B8G8R8X8_UNORM_SRGB},
 410
 411       /* rgb10a2 */
 412       {PIPE_FORMAT_R10G10B10A2_UNORM,      R10G10B10A2_UNORM},
 413       {PIPE_FORMAT_R10G10B10A2_SNORM,      R10G10B10A2_SNORM},
 414       {PIPE_FORMAT_R10G10B10A2_USCALED,    R10G10B10A2_USCALED},
 415       {PIPE_FORMAT_R10G10B10A2_SSCALED,    R10G10B10A2_SSCALED},
 416       {PIPE_FORMAT_R10G10B10A2_UINT,       R10G10B10A2_UINT},
 417
 418       /* rgb10x2 */
 419       {PIPE_FORMAT_R10G10B10X2_USCALED,    R10G10B10X2_USCALED},
 420
 421       /* bgr10a2 */
 422       {PIPE_FORMAT_B10G10R10A2_UNORM,      B10G10R10A2_UNORM},
 423       {PIPE_FORMAT_B10G10R10A2_SNORM,      B10G10R10A2_SNORM},
 424       {PIPE_FORMAT_B10G10R10A2_USCALED,    B10G10R10A2_USCALED},
 425       {PIPE_FORMAT_B10G10R10A2_SSCALED,    B10G10R10A2_SSCALED},
 426       {PIPE_FORMAT_B10G10R10A2_UINT,       B10G10R10A2_UINT},
 427
 428       /* bgr10x2 */
 429       {PIPE_FORMAT_B10G10R10X2_UNORM,      B10G10R10X2_UNORM},
 430
 431       /* r11g11b10 */
 432       {PIPE_FORMAT_R11G11B10_FLOAT,        R11G11B10_FLOAT},
 433
 434       /* 32 bits per component */
 435       {PIPE_FORMAT_R32_FLOAT,              R32_FLOAT},
 436       {PIPE_FORMAT_R32G32_FLOAT,           R32G32_FLOAT},
 437       {PIPE_FORMAT_R32G32B32_FLOAT,        R32G32B32_FLOAT},
 438       {PIPE_FORMAT_R32G32B32A32_FLOAT,     R32G32B32A32_FLOAT},
 439       {PIPE_FORMAT_R32G32B32X32_FLOAT,     R32G32B32X32_FLOAT},
 440
 441       {PIPE_FORMAT_R32_USCALED,            R32_USCALED},
 442       {PIPE_FORMAT_R32G32_USCALED,         R32G32_USCALED},
 443       {PIPE_FORMAT_R32G32B32_USCALED,      R32G32B32_USCALED},
 444       {PIPE_FORMAT_R32G32B32A32_USCALED,   R32G32B32A32_USCALED},
 445
 446       {PIPE_FORMAT_R32_SSCALED,            R32_SSCALED},
 447       {PIPE_FORMAT_R32G32_SSCALED,         R32G32_SSCALED},
 448       {PIPE_FORMAT_R32G32B32_SSCALED,      R32G32B32_SSCALED},
 449       {PIPE_FORMAT_R32G32B32A32_SSCALED,   R32G32B32A32_SSCALED},
 450
 451       {PIPE_FORMAT_R32_UINT,               R32_UINT},
 452       {PIPE_FORMAT_R32G32_UINT,            R32G32_UINT},
 453       {PIPE_FORMAT_R32G32B32_UINT,         R32G32B32_UINT},
 454       {PIPE_FORMAT_R32G32B32A32_UINT,      R32G32B32A32_UINT},
 455
 456       {PIPE_FORMAT_R32_SINT,               R32_SINT},
 457       {PIPE_FORMAT_R32G32_SINT,            R32G32_SINT},
 458       {PIPE_FORMAT_R32G32B32_SINT,         R32G32B32_SINT},
 459       {PIPE_FORMAT_R32G32B32A32_SINT,      R32G32B32A32_SINT},
 460
 461       /* 16 bits per component */
 462       {PIPE_FORMAT_R16_UNORM,              R16_UNORM},
 463       {PIPE_FORMAT_R16G16_UNORM,           R16G16_UNORM},
 464       {PIPE_FORMAT_R16G16B16_UNORM,        R16G16B16_UNORM},
 465       {PIPE_FORMAT_R16G16B16A16_UNORM,     R16G16B16A16_UNORM},
 466       {PIPE_FORMAT_R16G16B16X16_UNORM,     R16G16B16X16_UNORM},
 467
 468       {PIPE_FORMAT_R16_USCALED,            R16_USCALED},
 469       {PIPE_FORMAT_R16G16_USCALED,         R16G16_USCALED},
 470       {PIPE_FORMAT_R16G16B16_USCALED,      R16G16B16_USCALED},
 471       {PIPE_FORMAT_R16G16B16A16_USCALED,   R16G16B16A16_USCALED},
 472
 473       {PIPE_FORMAT_R16_SNORM,              R16_SNORM},
 474       {PIPE_FORMAT_R16G16_SNORM,           R16G16_SNORM},
 475       {PIPE_FORMAT_R16G16B16_SNORM,        R16G16B16_SNORM},
 476       {PIPE_FORMAT_R16G16B16A16_SNORM,     R16G16B16A16_SNORM},
 477
 478       {PIPE_FORMAT_R16_SSCALED,            R16_SSCALED},
 479       {PIPE_FORMAT_R16G16_SSCALED,         R16G16_SSCALED},
 480       {PIPE_FORMAT_R16G16B16_SSCALED,      R16G16B16_SSCALED},
 481       {PIPE_FORMAT_R16G16B16A16_SSCALED,   R16G16B16A16_SSCALED},
 482
 483       {PIPE_FORMAT_R16_UINT,               R16_UINT},
 484       {PIPE_FORMAT_R16G16_UINT,            R16G16_UINT},
 485       {PIPE_FORMAT_R16G16B16_UINT,         R16G16B16_UINT},
 486       {PIPE_FORMAT_R16G16B16A16_UINT,      R16G16B16A16_UINT},
 487
 488       {PIPE_FORMAT_R16_SINT,               R16_SINT},
 489       {PIPE_FORMAT_R16G16_SINT,            R16G16_SINT},
 490       {PIPE_FORMAT_R16G16B16_SINT,         R16G16B16_SINT},
 491       {PIPE_FORMAT_R16G16B16A16_SINT,      R16G16B16A16_SINT},
 492
 493       {PIPE_FORMAT_R16_FLOAT,              R16_FLOAT},
 494       {PIPE_FORMAT_R16G16_FLOAT,           R16G16_FLOAT},
 495       {PIPE_FORMAT_R16G16B16_FLOAT,        R16G16B16_FLOAT},
 496       {PIPE_FORMAT_R16G16B16A16_FLOAT,     R16G16B16A16_FLOAT},
 497       {PIPE_FORMAT_R16G16B16X16_FLOAT,     R16G16B16X16_FLOAT},
 498
 499       /* 8 bits per component */
 500       {PIPE_FORMAT_R8_UNORM,               R8_UNORM},
 501       {PIPE_FORMAT_R8G8_UNORM,             R8G8_UNORM},
 502       {PIPE_FORMAT_R8G8B8_UNORM,           R8G8B8_UNORM},
 503       {PIPE_FORMAT_R8G8B8_SRGB,            R8G8B8_UNORM_SRGB},
 504       {PIPE_FORMAT_R8G8B8A8_UNORM,         R8G8B8A8_UNORM},
 505       {PIPE_FORMAT_R8G8B8A8_SRGB,          R8G8B8A8_UNORM_SRGB},
 506       {PIPE_FORMAT_R8G8B8X8_UNORM,         R8G8B8X8_UNORM},
 507       {PIPE_FORMAT_R8G8B8X8_SRGB,          R8G8B8X8_UNORM_SRGB},
 508
 509       {PIPE_FORMAT_R8_USCALED,             R8_USCALED},
 510       {PIPE_FORMAT_R8G8_USCALED,           R8G8_USCALED},
 511       {PIPE_FORMAT_R8G8B8_USCALED,         R8G8B8_USCALED},
 512       {PIPE_FORMAT_R8G8B8A8_USCALED,       R8G8B8A8_USCALED},
 513
 514       {PIPE_FORMAT_R8_SNORM,               R8_SNORM},
 515       {PIPE_FORMAT_R8G8_SNORM,             R8G8_SNORM},
 516       {PIPE_FORMAT_R8G8B8_SNORM,           R8G8B8_SNORM},
 517       {PIPE_FORMAT_R8G8B8A8_SNORM,         R8G8B8A8_SNORM},
 518
 519       {PIPE_FORMAT_R8_SSCALED,             R8_SSCALED},
 520       {PIPE_FORMAT_R8G8_SSCALED,           R8G8_SSCALED},
 521       {PIPE_FORMAT_R8G8B8_SSCALED,         R8G8B8_SSCALED},
 522       {PIPE_FORMAT_R8G8B8A8_SSCALED,       R8G8B8A8_SSCALED},
 523
 524       {PIPE_FORMAT_R8_UINT,                R8_UINT},
 525       {PIPE_FORMAT_R8G8_UINT,              R8G8_UINT},
 526       {PIPE_FORMAT_R8G8B8_UINT,            R8G8B8_UINT},
 527       {PIPE_FORMAT_R8G8B8A8_UINT,          R8G8B8A8_UINT},
 528
 529       {PIPE_FORMAT_R8_SINT,                R8_SINT},
 530       {PIPE_FORMAT_R8G8_SINT,              R8G8_SINT},
 531       {PIPE_FORMAT_R8G8B8_SINT,            R8G8B8_SINT},
 532       {PIPE_FORMAT_R8G8B8A8_SINT,          R8G8B8A8_SINT},
 533
 534       /* These formats have entries in SWR but don't have Load/StoreTile
 535        * implementations. That means these aren't renderable, and thus having
 536        * a mapping entry here is detrimental.
 537        */
 538       /*
 539
 540       {PIPE_FORMAT_L8_UNORM,               L8_UNORM},
 541       {PIPE_FORMAT_I8_UNORM,               I8_UNORM},
 542       {PIPE_FORMAT_L8A8_UNORM,             L8A8_UNORM},
 543       {PIPE_FORMAT_L16_UNORM,              L16_UNORM},
 544       {PIPE_FORMAT_UYVY,                   YCRCB_SWAPUVY},
 545
 546       {PIPE_FORMAT_L8_SRGB,                L8_UNORM_SRGB},
 547       {PIPE_FORMAT_L8A8_SRGB,              L8A8_UNORM_SRGB},
 548
 549       {PIPE_FORMAT_DXT1_RGBA,              BC1_UNORM},
 550       {PIPE_FORMAT_DXT3_RGBA,              BC2_UNORM},
 551       {PIPE_FORMAT_DXT5_RGBA,              BC3_UNORM},
 552
 553       {PIPE_FORMAT_DXT1_SRGBA,             BC1_UNORM_SRGB},
 554       {PIPE_FORMAT_DXT3_SRGBA,             BC2_UNORM_SRGB},
 555       {PIPE_FORMAT_DXT5_SRGBA,             BC3_UNORM_SRGB},
 556
 557       {PIPE_FORMAT_RGTC1_UNORM,            BC4_UNORM},
 558       {PIPE_FORMAT_RGTC1_SNORM,            BC4_SNORM},
 559       {PIPE_FORMAT_RGTC2_UNORM,            BC5_UNORM},
 560       {PIPE_FORMAT_RGTC2_SNORM,            BC5_SNORM},
 561
 562       {PIPE_FORMAT_L16A16_UNORM,           L16A16_UNORM},
 563       {PIPE_FORMAT_I16_UNORM,              I16_UNORM},
 564       {PIPE_FORMAT_L16_FLOAT,              L16_FLOAT},
 565       {PIPE_FORMAT_L16A16_FLOAT,           L16A16_FLOAT},
 566       {PIPE_FORMAT_I16_FLOAT,              I16_FLOAT},
 567       {PIPE_FORMAT_L32_FLOAT,              L32_FLOAT},
 568       {PIPE_FORMAT_L32A32_FLOAT,           L32A32_FLOAT},
 569       {PIPE_FORMAT_I32_FLOAT,              I32_FLOAT},
 570
 571       {PIPE_FORMAT_I8_UINT,                I8_UINT},
 572       {PIPE_FORMAT_L8_UINT,                L8_UINT},
 573       {PIPE_FORMAT_L8A8_UINT,              L8A8_UINT},
 574
 575       {PIPE_FORMAT_I8_SINT,                I8_SINT},
 576       {PIPE_FORMAT_L8_SINT,                L8_SINT},
 577       {PIPE_FORMAT_L8A8_SINT,              L8A8_SINT},
 578
 579       */
 580    };
 581
 582    auto it = mesa2swr.find(format);
 583    if (it == mesa2swr.end())
 584       return (SWR_FORMAT)-1;
 585    else
 586       return it->second;
 587 }
 588
 589 static boolean
 590 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
 591 {
 592    struct sw_winsys *winsys = screen->winsys;
 593    struct sw_displaytarget *dt;
 594
 595    const unsigned width = align(res->swr.width, res->swr.halign);
 596    const unsigned height = align(res->swr.height, res->swr.valign);
 597
 598    UINT stride;
 599    dt = winsys->displaytarget_create(winsys,
 600                                      res->base.bind,
 601                                      res->base.format,
 602                                      width, height,
 603                                      64, NULL,
 604                                      &stride);
 605
 606    if (dt == NULL)
 607       return FALSE;
 608
 609    void *map = winsys->displaytarget_map(winsys, dt, 0);
 610
 611    res->display_target = dt;
 612    res->swr.pBaseAddress = (uint8_t*) map;
 613
 614    /* Clear the display target surface */
 615    if (map)
 616       memset(map, 0, height * stride);
 617
 618    winsys->displaytarget_unmap(winsys, dt);
 619
 620    return TRUE;
 621 }
 622
 623 static bool
 624 swr_texture_layout(struct swr_screen *screen,
 625                    struct swr_resource *res,
 626                    boolean allocate)
 627 {
 628    struct pipe_resource *pt = &res->base;
 629
 630    pipe_format fmt = pt->format;
 631    const struct util_format_description *desc = util_format_description(fmt);
 632
 633    res->has_depth = util_format_has_depth(desc);
 634    res->has_stencil = util_format_has_stencil(desc);
 635
 636    if (res->has_stencil && !res->has_depth)
 637       fmt = PIPE_FORMAT_R8_UINT;
 638
 639    /* We always use the SWR layout. For 2D and 3D textures this looks like:
 640     *
 641     * |<------- pitch ------->|
 642     * +=======================+-------
 643     * |Array 0                |   ^
 644     * |                       |   |
 645     * |        Level 0        |   |
 646     * |                       |   |
 647     * |                       | qpitch
 648     * +-----------+-----------+   |
 649     * |           | L2L2L2L2  |   |
 650     * |  Level 1  | L3L3      |   |
 651     * |           | L4        |   v
 652     * +===========+===========+-------
 653     * |Array 1                |
 654     * |                       |
 655     * |        Level 0        |
 656     * |                       |
 657     * |                       |
 658     * +-----------+-----------+
 659     * |           | L2L2L2L2  |
 660     * |  Level 1  | L3L3      |
 661     * |           | L4        |
 662     * +===========+===========+
 663     *
 664     * The overall width in bytes is known as the pitch, while the overall
 665     * height in rows is the qpitch. Array slices are laid out logically below
 666     * one another, qpitch rows apart. For 3D surfaces, the "level" values are
 667     * just invalid for the higher array numbers (since depth is also
 668     * minified). 1D and 1D array surfaces are stored effectively the same way,
 669     * except that pitch never plays into it. All the levels are logically
 670     * adjacent to each other on the X axis. The qpitch becomes the number of
 671     * elements between array slices, while the pitch is unused.
 672     *
 673     * Each level's sizes are subject to the valign and halign settings of the
 674     * surface. For compressed formats that swr is unaware of, we will use an
 675     * appropriately-sized uncompressed format, and scale the widths/heights.
 676     *
 677     * This surface is stored inside res->swr. For depth/stencil textures,
 678     * res->secondary will have an identically-laid-out but R8_UINT-formatted
 679     * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
 680     * texels, to simplify map/unmap logic which copies the stencil values
 681     * in/out.
 682     */
 683
 684    res->swr.width = pt->width0;
 685    res->swr.height = pt->height0;
 686    res->swr.type = swr_convert_target_type(pt->target);
 687    res->swr.tileMode = SWR_TILE_NONE;
 688    res->swr.format = mesa_to_swr_format(fmt);
 689    res->swr.numSamples = std::max(1u, pt->nr_samples);
 690
 691    if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
 692       res->swr.halign = KNOB_MACROTILE_X_DIM;
 693       res->swr.valign = KNOB_MACROTILE_Y_DIM;
 694    } else {
 695       res->swr.halign = 1;
 696       res->swr.valign = 1;
 697    }
 698
 699    unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
 700    unsigned width = align(pt->width0, halign);
 701    if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
 702       for (int level = 1; level <= pt->last_level; level++)
 703          width += align(u_minify(pt->width0, level), halign);
 704       res->swr.pitch = util_format_get_blocksize(fmt);
 705       res->swr.qpitch = util_format_get_nblocksx(fmt, width);
 706    } else {
 707       // The pitch is the overall width of the texture in bytes. Most of the
 708       // time this is the pitch of level 0 since all the other levels fit
 709       // underneath it. However in some degenerate situations, the width of
 710       // level1 + level2 may be larger. In that case, we use those
 711       // widths. This can happen if, e.g. halign is 32, and the width of level
 712       // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
 713       // be 32 each, adding up to 64.
 714       unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
 715       if (pt->last_level > 1) {
 716          width = std::max<uint32_t>(
 717                width,
 718                align(u_minify(pt->width0, 1), halign) +
 719                align(u_minify(pt->width0, 2), halign));
 720       }
 721       res->swr.pitch = util_format_get_stride(fmt, width);
 722
 723       // The qpitch is controlled by either the height of the second LOD, or
 724       // the combination of all the later LODs.
 725       unsigned height = align(pt->height0, valign);
 726       if (pt->last_level == 1) {
 727          height += align(u_minify(pt->height0, 1), valign);
 728       } else if (pt->last_level > 1) {
 729          unsigned level1 = align(u_minify(pt->height0, 1), valign);
 730          unsigned level2 = 0;
 731          for (int level = 2; level <= pt->last_level; level++) {
 732             level2 += align(u_minify(pt->height0, level), valign);
 733          }
 734          height += std::max(level1, level2);
 735       }
 736       res->swr.qpitch = util_format_get_nblocksy(fmt, height);
 737    }
 738
 739    if (pt->target == PIPE_TEXTURE_3D)
 740       res->swr.depth = pt->depth0;
 741    else
 742       res->swr.depth = pt->array_size;
 743
 744    // Fix up swr format if necessary so that LOD offset computation works
 745    if (res->swr.format == (SWR_FORMAT)-1) {
 746       switch (util_format_get_blocksize(fmt)) {
 747       default:
 748          unreachable("Unexpected format block size");
 749       case 1: res->swr.format = R8_UINT; break;
 750       case 2: res->swr.format = R16_UINT; break;
 751       case 4: res->swr.format = R32_UINT; break;
 752       case 8:
 753          if (util_format_is_compressed(fmt))
 754             res->swr.format = BC4_UNORM;
 755          else
 756             res->swr.format = R32G32_UINT;
 757          break;
 758       case 16:
 759          if (util_format_is_compressed(fmt))
 760             res->swr.format = BC5_UNORM;
 761          else
 762             res->swr.format = R32G32B32A32_UINT;
 763          break;
 764       }
 765    }
 766
 767    for (int level = 0; level <= pt->last_level; level++) {
 768       res->mip_offsets[level] =
 769          ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
 770    }
 771
 772    size_t total_size =
 773       (size_t)res->swr.depth * res->swr.qpitch * res->swr.pitch;
 774    if (total_size > SWR_MAX_TEXTURE_SIZE)
 775       return false;
 776
 777    if (allocate) {
 778       res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
 779
 780       if (res->has_depth && res->has_stencil) {
 781          res->secondary = res->swr;
 782          res->secondary.format = R8_UINT;
 783          res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
 784
 785          for (int level = 0; level <= pt->last_level; level++) {
 786             res->secondary_mip_offsets[level] =
 787                ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
 788          }
 789
 790          res->secondary.pBaseAddress = (uint8_t *)AlignedMalloc(
 791             res->secondary.depth * res->secondary.qpitch *
 792             res->secondary.pitch, 64);
 793       }
 794    }
 795
 796    return true;
 797 }
 798
 799 static boolean
 800 swr_can_create_resource(struct pipe_screen *screen,
 801                         const struct pipe_resource *templat)
 802 {
 803    struct swr_resource res;
 804    memset(&res, 0, sizeof(res));
 805    res.base = *templat;
 806    return swr_texture_layout(swr_screen(screen), &res, false);
 807 }
 808
 809 static struct pipe_resource *
 810 swr_resource_create(struct pipe_screen *_screen,
 811                     const struct pipe_resource *templat)
 812 {
 813    struct swr_screen *screen = swr_screen(_screen);
 814    struct swr_resource *res = CALLOC_STRUCT(swr_resource);
 815    if (!res)
 816       return NULL;
 817
 818    res->base = *templat;
 819    pipe_reference_init(&res->base.reference, 1);
 820    res->base.screen = &screen->base;
 821
 822    if (swr_resource_is_texture(&res->base)) {
 823       if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 824                             | PIPE_BIND_SHARED)) {
 825          /* displayable surface
 826           * first call swr_texture_layout without allocating to finish
 827           * filling out the SWR_SURFAE_STATE in res */
 828          swr_texture_layout(screen, res, false);
 829          if (!swr_displaytarget_layout(screen, res))
 830             goto fail;
 831       } else {
 832          /* texture map */
 833          if (!swr_texture_layout(screen, res, true))
 834             goto fail;
 835       }
 836    } else {
 837       /* other data (vertex buffer, const buffer, etc) */
 838       assert(util_format_get_blocksize(templat->format) == 1);
 839       assert(templat->height0 == 1);
 840       assert(templat->depth0 == 1);
 841       assert(templat->last_level == 0);
 842
 843       /* Easiest to just call swr_texture_layout, as it sets up
 844        * SWR_SURFAE_STATE in res */
 845       if (!swr_texture_layout(screen, res, true))
 846          goto fail;
 847    }
 848
 849    return &res->base;
 850
 851 fail:
 852    FREE(res);
 853    return NULL;
 854 }
 855
 856 static void
 857 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
 858 {
 859    struct swr_screen *screen = swr_screen(p_screen);
 860    struct swr_resource *spr = swr_resource(pt);
 861    struct pipe_context *pipe = screen->pipe;
 862
 863    /* Only wait on fence if the resource is being used */
 864    if (pipe && spr->status) {
 865       /* But, if there's no fence pending, submit one.
 866        * XXX: Remove once draw timestamps are implmented. */
 867       if (!swr_is_fence_pending(screen->flush_fence))
 868          swr_fence_submit(swr_context(pipe), screen->flush_fence);
 869
 870       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 871       swr_resource_unused(pt);
 872    }
 873
 874    /*
 875     * Free resource primary surface.  If resource is display target, winsys
 876     * manages the buffer and will free it on displaytarget_destroy.
 877     */
 878    if (spr->display_target) {
 879       /* display target */
 880       struct sw_winsys *winsys = screen->winsys;
 881       winsys->displaytarget_destroy(winsys, spr->display_target);
 882    } else
 883       AlignedFree(spr->swr.pBaseAddress);
 884
 885    AlignedFree(spr->secondary.pBaseAddress);
 886
 887    FREE(spr);
 888 }
 889
 890
 891 static void
 892 swr_flush_frontbuffer(struct pipe_screen *p_screen,
 893                       struct pipe_resource *resource,
 894                       unsigned level,
 895                       unsigned layer,
 896                       void *context_private,
 897                       struct pipe_box *sub_box)
 898 {
 899    struct swr_screen *screen = swr_screen(p_screen);
 900    struct sw_winsys *winsys = screen->winsys;
 901    struct swr_resource *spr = swr_resource(resource);
 902    struct pipe_context *pipe = screen->pipe;
 903
 904    if (pipe) {
 905       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 906       swr_resource_unused(resource);
 907       SwrEndFrame(swr_context(pipe)->swrContext);
 908    }
 909
 910    debug_assert(spr->display_target);
 911    if (spr->display_target)
 912       winsys->displaytarget_display(
 913          winsys, spr->display_target, context_private, sub_box);
 914 }
 915
 916
 917 static void
 918 swr_destroy_screen(struct pipe_screen *p_screen)
 919 {
 920    struct swr_screen *screen = swr_screen(p_screen);
 921    struct sw_winsys *winsys = screen->winsys;
 922
 923    fprintf(stderr, "SWR destroy screen!\n");
 924
 925    swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 926    swr_fence_reference(p_screen, &screen->flush_fence, NULL);
 927
 928    JitDestroyContext(screen->hJitMgr);
 929
 930    if (winsys->destroy)
 931       winsys->destroy(winsys);
 932
 933    FREE(screen);
 934 }
 935
 936 PUBLIC
 937 struct pipe_screen *
 938 swr_create_screen_internal(struct sw_winsys *winsys)
 939 {
 940    struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
 941
 942    if (!screen)
 943       return NULL;
 944
 945    if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
 946       g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152);
 947    }
 948
 949    if (!lp_build_init()) {
 950       FREE(screen);
 951       return NULL;
 952    }
 953
 954    screen->winsys = winsys;
 955    screen->base.get_name = swr_get_name;
 956    screen->base.get_vendor = swr_get_vendor;
 957    screen->base.is_format_supported = swr_is_format_supported;
 958    screen->base.context_create = swr_create_context;
 959    screen->base.can_create_resource = swr_can_create_resource;
 960
 961    screen->base.destroy = swr_destroy_screen;
 962    screen->base.get_param = swr_get_param;
 963    screen->base.get_shader_param = swr_get_shader_param;
 964    screen->base.get_paramf = swr_get_paramf;
 965
 966    screen->base.resource_create = swr_resource_create;
 967    screen->base.resource_destroy = swr_resource_destroy;
 968
 969    screen->base.flush_frontbuffer = swr_flush_frontbuffer;
 970
 971    screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
 972
 973    swr_fence_init(&screen->base);
 974
 975    util_format_s3tc_init();
 976
 977    return &screen->base;
 978 }
 979