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[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned storage_sample_count,
89 unsigned bind)
90 {
91 struct swr_screen *screen = swr_screen(_screen);
92 struct sw_winsys *winsys = screen->winsys;
93 const struct util_format_description *format_desc;
94
95 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
96 || target == PIPE_TEXTURE_1D_ARRAY
97 || target == PIPE_TEXTURE_2D
98 || target == PIPE_TEXTURE_2D_ARRAY
99 || target == PIPE_TEXTURE_RECT
100 || target == PIPE_TEXTURE_3D
101 || target == PIPE_TEXTURE_CUBE
102 || target == PIPE_TEXTURE_CUBE_ARRAY);
103
104 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
105 return false;
106
107 format_desc = util_format_description(format);
108 if (!format_desc)
109 return FALSE;
110
111 if ((sample_count > screen->msaa_max_count)
112 || !util_is_power_of_two_or_zero(sample_count))
113 return FALSE;
114
115 if (bind & PIPE_BIND_DISPLAY_TARGET) {
116 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
117 return FALSE;
118 }
119
120 if (bind & PIPE_BIND_RENDER_TARGET) {
121 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
122 return FALSE;
123
124 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
125 return FALSE;
126
127 /*
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside the state trackers.
131 */
132 if (format_desc->block.width != 1 || format_desc->block.height != 1)
133 return FALSE;
134 }
135
136 if (bind & PIPE_BIND_DEPTH_STENCIL) {
137 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
138 return FALSE;
139
140 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
141 return FALSE;
142 }
143
144 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
145 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
146 return FALSE;
147 }
148
149 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
150 format != PIPE_FORMAT_ETC1_RGB8) {
151 return FALSE;
152 }
153
154 return TRUE;
155 }
156
157 static int
158 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
159 {
160 switch (param) {
161 /* limits */
162 case PIPE_CAP_MAX_RENDER_TARGETS:
163 return PIPE_MAX_COLOR_BUFS;
164 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
165 return SWR_MAX_TEXTURE_2D_LEVELS;
166 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
167 return SWR_MAX_TEXTURE_3D_LEVELS;
168 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
169 return SWR_MAX_TEXTURE_CUBE_LEVELS;
170 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
171 return MAX_SO_STREAMS;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
173 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
174 return MAX_ATTRIBUTES * 4;
175 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
176 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
177 return 1024;
178 case PIPE_CAP_MAX_VERTEX_STREAMS:
179 return 1;
180 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
181 return 2048;
182 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
183 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
184 case PIPE_CAP_MIN_TEXEL_OFFSET:
185 return -8;
186 case PIPE_CAP_MAX_TEXEL_OFFSET:
187 return 7;
188 case PIPE_CAP_GLSL_FEATURE_LEVEL:
189 return 330;
190 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
191 return 140;
192 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
193 return 16;
194 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
195 return 64;
196 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
197 return 65536;
198 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
199 return 0;
200 case PIPE_CAP_MAX_VIEWPORTS:
201 return 1;
202 case PIPE_CAP_ENDIANNESS:
203 return PIPE_ENDIAN_NATIVE;
204 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
205 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
206 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
207 return 0;
208
209 /* supported features */
210 case PIPE_CAP_NPOT_TEXTURES:
211 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
212 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
213 case PIPE_CAP_SM3:
214 case PIPE_CAP_POINT_SPRITE:
215 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
216 case PIPE_CAP_OCCLUSION_QUERY:
217 case PIPE_CAP_QUERY_TIME_ELAPSED:
218 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
219 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
220 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
221 case PIPE_CAP_TEXTURE_SWIZZLE:
222 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
223 case PIPE_CAP_INDEP_BLEND_ENABLE:
224 case PIPE_CAP_INDEP_BLEND_FUNC:
225 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
226 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
227 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
228 case PIPE_CAP_DEPTH_CLIP_DISABLE:
229 case PIPE_CAP_PRIMITIVE_RESTART:
230 case PIPE_CAP_TGSI_INSTANCEID:
231 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
232 case PIPE_CAP_START_INSTANCE:
233 case PIPE_CAP_SEAMLESS_CUBE_MAP:
234 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
235 case PIPE_CAP_CONDITIONAL_RENDER:
236 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
237 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
238 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
239 case PIPE_CAP_USER_VERTEX_BUFFERS:
240 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
241 case PIPE_CAP_QUERY_TIMESTAMP:
242 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
243 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
244 case PIPE_CAP_DRAW_INDIRECT:
245 case PIPE_CAP_UMA:
246 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
247 case PIPE_CAP_CLIP_HALFZ:
248 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
249 case PIPE_CAP_DEPTH_BOUNDS_TEST:
250 case PIPE_CAP_CLEAR_TEXTURE:
251 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
252 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
253 case PIPE_CAP_CULL_DISTANCE:
254 case PIPE_CAP_CUBE_MAP_ARRAY:
255 case PIPE_CAP_DOUBLES:
256 return 1;
257
258 /* MSAA support
259 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
260 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
261 case PIPE_CAP_TEXTURE_MULTISAMPLE:
262 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
263 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
264 case PIPE_CAP_FAKE_SW_MSAA:
265 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
266
267 /* fetch jit change for 2-4GB buffers requires alignment */
268 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
269 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
270 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
271 return 1;
272
273 /* unsupported features */
274 case PIPE_CAP_ANISOTROPIC_FILTER:
275 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
276 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
277 case PIPE_CAP_SHADER_STENCIL_EXPORT:
278 case PIPE_CAP_TEXTURE_BARRIER:
279 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
280 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
281 case PIPE_CAP_COMPUTE:
282 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
283 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
284 case PIPE_CAP_TGSI_TEXCOORD:
285 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
286 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
287 case PIPE_CAP_TEXTURE_GATHER_SM5:
288 case PIPE_CAP_TEXTURE_QUERY_LOD:
289 case PIPE_CAP_SAMPLE_SHADING:
290 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
291 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
292 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
293 case PIPE_CAP_SAMPLER_VIEW_TARGET:
294 case PIPE_CAP_VERTEXID_NOBASE:
295 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
296 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
297 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
298 case PIPE_CAP_TGSI_TXQS:
299 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
300 case PIPE_CAP_SHAREABLE_SHADERS:
301 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
302 case PIPE_CAP_DRAW_PARAMETERS:
303 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
304 case PIPE_CAP_MULTI_DRAW_INDIRECT:
305 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
306 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
307 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
308 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
309 case PIPE_CAP_INVALIDATE_BUFFER:
310 case PIPE_CAP_GENERATE_MIPMAP:
311 case PIPE_CAP_STRING_MARKER:
312 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
313 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
314 case PIPE_CAP_QUERY_BUFFER_OBJECT:
315 case PIPE_CAP_QUERY_MEMORY_INFO:
316 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
317 case PIPE_CAP_PCI_GROUP:
318 case PIPE_CAP_PCI_BUS:
319 case PIPE_CAP_PCI_DEVICE:
320 case PIPE_CAP_PCI_FUNCTION:
321 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
322 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
323 case PIPE_CAP_TGSI_VOTE:
324 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
325 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
326 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
327 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
328 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
329 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
330 case PIPE_CAP_NATIVE_FENCE_FD:
331 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
332 case PIPE_CAP_TGSI_FS_FBFETCH:
333 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
334 case PIPE_CAP_INT64:
335 case PIPE_CAP_INT64_DIVMOD:
336 case PIPE_CAP_TGSI_TEX_TXF_LZ:
337 case PIPE_CAP_TGSI_CLOCK:
338 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
339 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
340 case PIPE_CAP_TGSI_BALLOT:
341 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
342 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
343 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
344 case PIPE_CAP_POST_DEPTH_COVERAGE:
345 case PIPE_CAP_BINDLESS_TEXTURE:
346 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
347 case PIPE_CAP_QUERY_SO_OVERFLOW:
348 case PIPE_CAP_MEMOBJ:
349 case PIPE_CAP_LOAD_CONSTBUF:
350 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
351 case PIPE_CAP_TILE_RASTER_ORDER:
352 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
353 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
354 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
355 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
356 case PIPE_CAP_FENCE_SIGNAL:
357 case PIPE_CAP_CONSTBUF0_FLAGS:
358 case PIPE_CAP_PACKED_UNIFORMS:
359 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
360 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
361 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
362 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
363 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
364 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
365 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
366 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
367 return 0;
368 case PIPE_CAP_MAX_GS_INVOCATIONS:
369 return 32;
370 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
371 return 1 << 27;
372
373 case PIPE_CAP_VENDOR_ID:
374 return 0xFFFFFFFF;
375 case PIPE_CAP_DEVICE_ID:
376 return 0xFFFFFFFF;
377 case PIPE_CAP_ACCELERATED:
378 return 0;
379 case PIPE_CAP_VIDEO_MEMORY: {
380 /* XXX: Do we want to return the full amount of system memory ? */
381 uint64_t system_memory;
382
383 if (!os_get_total_physical_memory(&system_memory))
384 return 0;
385
386 return (int)(system_memory >> 20);
387 }
388 }
389
390 /* should only get here on unhandled cases */
391 debug_printf("Unexpected PIPE_CAP %d query\n", param);
392 return 0;
393 }
394
395 static int
396 swr_get_shader_param(struct pipe_screen *screen,
397 enum pipe_shader_type shader,
398 enum pipe_shader_cap param)
399 {
400 if (shader == PIPE_SHADER_VERTEX ||
401 shader == PIPE_SHADER_FRAGMENT ||
402 shader == PIPE_SHADER_GEOMETRY)
403 return gallivm_get_shader_param(param);
404
405 // Todo: tesselation, compute
406 return 0;
407 }
408
409
410 static float
411 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
412 {
413 switch (param) {
414 case PIPE_CAPF_MAX_LINE_WIDTH:
415 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
416 case PIPE_CAPF_MAX_POINT_WIDTH:
417 return 255.0; /* arbitrary */
418 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
419 return 0.0;
420 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
421 return 0.0;
422 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
423 return 16.0; /* arbitrary */
424 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
425 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
426 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
427 return 0.0f;
428 }
429 /* should only get here on unhandled cases */
430 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
431 return 0.0;
432 }
433
434 SWR_FORMAT
435 mesa_to_swr_format(enum pipe_format format)
436 {
437 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
438 /* depth / stencil */
439 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
440 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
441 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
442 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
443 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
444
445 /* alpha */
446 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
447 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
448 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
449 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
450
451 /* odd sizes, bgr */
452 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
453 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
454 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
455 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
456 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
457 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
458 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
459 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
460 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
461
462 /* rgb10a2 */
463 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
464 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
465 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
466 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
467 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
468
469 /* rgb10x2 */
470 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
471
472 /* bgr10a2 */
473 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
474 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
475 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
476 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
477 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
478
479 /* bgr10x2 */
480 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
481
482 /* r11g11b10 */
483 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
484
485 /* 32 bits per component */
486 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
487 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
488 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
489 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
490 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
491
492 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
493 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
494 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
495 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
496
497 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
498 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
499 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
500 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
501
502 {PIPE_FORMAT_R32_UINT, R32_UINT},
503 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
504 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
505 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
506
507 {PIPE_FORMAT_R32_SINT, R32_SINT},
508 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
509 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
510 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
511
512 /* 16 bits per component */
513 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
514 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
515 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
516 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
517 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
518
519 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
520 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
521 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
522 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
523
524 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
525 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
526 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
527 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
528
529 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
530 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
531 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
532 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
533
534 {PIPE_FORMAT_R16_UINT, R16_UINT},
535 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
536 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
537 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
538
539 {PIPE_FORMAT_R16_SINT, R16_SINT},
540 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
541 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
542 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
543
544 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
545 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
546 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
547 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
548 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
549
550 /* 8 bits per component */
551 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
552 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
553 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
554 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
555 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
556 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
557 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
558 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
559
560 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
561 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
562 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
563 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
564
565 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
566 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
567 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
568 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
569
570 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
571 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
572 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
573 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
574
575 {PIPE_FORMAT_R8_UINT, R8_UINT},
576 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
577 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
578 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
579
580 {PIPE_FORMAT_R8_SINT, R8_SINT},
581 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
582 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
583 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
584
585 /* These formats are valid for vertex data, but should not be used
586 * for render targets.
587 */
588
589 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
590 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
591 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
592 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
593
594 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
595 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
596 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
597 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
598
599 /* These formats have entries in SWR but don't have Load/StoreTile
600 * implementations. That means these aren't renderable, and thus having
601 * a mapping entry here is detrimental.
602 */
603 /*
604
605 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
606 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
607 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
608 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
609 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
610
611 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
612 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
613
614 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
615 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
616 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
617
618 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
619 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
620 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
621
622 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
623 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
624 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
625 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
626
627 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
628 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
629 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
630 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
631 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
632 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
633 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
634 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
635
636 {PIPE_FORMAT_I8_UINT, I8_UINT},
637 {PIPE_FORMAT_L8_UINT, L8_UINT},
638 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
639
640 {PIPE_FORMAT_I8_SINT, I8_SINT},
641 {PIPE_FORMAT_L8_SINT, L8_SINT},
642 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
643
644 */
645 };
646
647 auto it = mesa2swr.find(format);
648 if (it == mesa2swr.end())
649 return (SWR_FORMAT)-1;
650 else
651 return it->second;
652 }
653
654 static boolean
655 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
656 {
657 struct sw_winsys *winsys = screen->winsys;
658 struct sw_displaytarget *dt;
659
660 const unsigned width = align(res->swr.width, res->swr.halign);
661 const unsigned height = align(res->swr.height, res->swr.valign);
662
663 UINT stride;
664 dt = winsys->displaytarget_create(winsys,
665 res->base.bind,
666 res->base.format,
667 width, height,
668 64, NULL,
669 &stride);
670
671 if (dt == NULL)
672 return FALSE;
673
674 void *map = winsys->displaytarget_map(winsys, dt, 0);
675
676 res->display_target = dt;
677 res->swr.xpBaseAddress = (gfxptr_t)map;
678
679 /* Clear the display target surface */
680 if (map)
681 memset(map, 0, height * stride);
682
683 winsys->displaytarget_unmap(winsys, dt);
684
685 return TRUE;
686 }
687
688 static bool
689 swr_texture_layout(struct swr_screen *screen,
690 struct swr_resource *res,
691 boolean allocate)
692 {
693 struct pipe_resource *pt = &res->base;
694
695 pipe_format fmt = pt->format;
696 const struct util_format_description *desc = util_format_description(fmt);
697
698 res->has_depth = util_format_has_depth(desc);
699 res->has_stencil = util_format_has_stencil(desc);
700
701 if (res->has_stencil && !res->has_depth)
702 fmt = PIPE_FORMAT_R8_UINT;
703
704 /* We always use the SWR layout. For 2D and 3D textures this looks like:
705 *
706 * |<------- pitch ------->|
707 * +=======================+-------
708 * |Array 0 | ^
709 * | | |
710 * | Level 0 | |
711 * | | |
712 * | | qpitch
713 * +-----------+-----------+ |
714 * | | L2L2L2L2 | |
715 * | Level 1 | L3L3 | |
716 * | | L4 | v
717 * +===========+===========+-------
718 * |Array 1 |
719 * | |
720 * | Level 0 |
721 * | |
722 * | |
723 * +-----------+-----------+
724 * | | L2L2L2L2 |
725 * | Level 1 | L3L3 |
726 * | | L4 |
727 * +===========+===========+
728 *
729 * The overall width in bytes is known as the pitch, while the overall
730 * height in rows is the qpitch. Array slices are laid out logically below
731 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
732 * just invalid for the higher array numbers (since depth is also
733 * minified). 1D and 1D array surfaces are stored effectively the same way,
734 * except that pitch never plays into it. All the levels are logically
735 * adjacent to each other on the X axis. The qpitch becomes the number of
736 * elements between array slices, while the pitch is unused.
737 *
738 * Each level's sizes are subject to the valign and halign settings of the
739 * surface. For compressed formats that swr is unaware of, we will use an
740 * appropriately-sized uncompressed format, and scale the widths/heights.
741 *
742 * This surface is stored inside res->swr. For depth/stencil textures,
743 * res->secondary will have an identically-laid-out but R8_UINT-formatted
744 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
745 * texels, to simplify map/unmap logic which copies the stencil values
746 * in/out.
747 */
748
749 res->swr.width = pt->width0;
750 res->swr.height = pt->height0;
751 res->swr.type = swr_convert_target_type(pt->target);
752 res->swr.tileMode = SWR_TILE_NONE;
753 res->swr.format = mesa_to_swr_format(fmt);
754 res->swr.numSamples = std::max(1u, pt->nr_samples);
755
756 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
757 res->swr.halign = KNOB_MACROTILE_X_DIM;
758 res->swr.valign = KNOB_MACROTILE_Y_DIM;
759
760 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
761 * surface sample count. */
762 if (screen->msaa_force_enable) {
763 res->swr.numSamples = screen->msaa_max_count;
764 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
765 res->swr.numSamples);
766 }
767 } else {
768 res->swr.halign = 1;
769 res->swr.valign = 1;
770 }
771
772 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
773 unsigned width = align(pt->width0, halign);
774 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
775 for (int level = 1; level <= pt->last_level; level++)
776 width += align(u_minify(pt->width0, level), halign);
777 res->swr.pitch = util_format_get_blocksize(fmt);
778 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
779 } else {
780 // The pitch is the overall width of the texture in bytes. Most of the
781 // time this is the pitch of level 0 since all the other levels fit
782 // underneath it. However in some degenerate situations, the width of
783 // level1 + level2 may be larger. In that case, we use those
784 // widths. This can happen if, e.g. halign is 32, and the width of level
785 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
786 // be 32 each, adding up to 64.
787 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
788 if (pt->last_level > 1) {
789 width = std::max<uint32_t>(
790 width,
791 align(u_minify(pt->width0, 1), halign) +
792 align(u_minify(pt->width0, 2), halign));
793 }
794 res->swr.pitch = util_format_get_stride(fmt, width);
795
796 // The qpitch is controlled by either the height of the second LOD, or
797 // the combination of all the later LODs.
798 unsigned height = align(pt->height0, valign);
799 if (pt->last_level == 1) {
800 height += align(u_minify(pt->height0, 1), valign);
801 } else if (pt->last_level > 1) {
802 unsigned level1 = align(u_minify(pt->height0, 1), valign);
803 unsigned level2 = 0;
804 for (int level = 2; level <= pt->last_level; level++) {
805 level2 += align(u_minify(pt->height0, level), valign);
806 }
807 height += std::max(level1, level2);
808 }
809 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
810 }
811
812 if (pt->target == PIPE_TEXTURE_3D)
813 res->swr.depth = pt->depth0;
814 else
815 res->swr.depth = pt->array_size;
816
817 // Fix up swr format if necessary so that LOD offset computation works
818 if (res->swr.format == (SWR_FORMAT)-1) {
819 switch (util_format_get_blocksize(fmt)) {
820 default:
821 unreachable("Unexpected format block size");
822 case 1: res->swr.format = R8_UINT; break;
823 case 2: res->swr.format = R16_UINT; break;
824 case 4: res->swr.format = R32_UINT; break;
825 case 8:
826 if (util_format_is_compressed(fmt))
827 res->swr.format = BC4_UNORM;
828 else
829 res->swr.format = R32G32_UINT;
830 break;
831 case 16:
832 if (util_format_is_compressed(fmt))
833 res->swr.format = BC5_UNORM;
834 else
835 res->swr.format = R32G32B32A32_UINT;
836 break;
837 }
838 }
839
840 for (int level = 0; level <= pt->last_level; level++) {
841 res->mip_offsets[level] =
842 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
843 }
844
845 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
846 res->swr.pitch * res->swr.numSamples;
847 if (total_size > SWR_MAX_TEXTURE_SIZE)
848 return false;
849
850 if (allocate) {
851 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
852 if (!res->swr.xpBaseAddress)
853 return false;
854
855 if (res->has_depth && res->has_stencil) {
856 res->secondary = res->swr;
857 res->secondary.format = R8_UINT;
858 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
859
860 for (int level = 0; level <= pt->last_level; level++) {
861 res->secondary_mip_offsets[level] =
862 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
863 }
864
865 total_size = res->secondary.depth * res->secondary.qpitch *
866 res->secondary.pitch * res->secondary.numSamples;
867
868 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
869 if (!res->secondary.xpBaseAddress) {
870 AlignedFree((void *)res->swr.xpBaseAddress);
871 return false;
872 }
873 }
874 }
875
876 return true;
877 }
878
879 static boolean
880 swr_can_create_resource(struct pipe_screen *screen,
881 const struct pipe_resource *templat)
882 {
883 struct swr_resource res;
884 memset(&res, 0, sizeof(res));
885 res.base = *templat;
886 return swr_texture_layout(swr_screen(screen), &res, false);
887 }
888
889 /* Helper function that conditionally creates a single-sample resolve resource
890 * and attaches it to main multisample resource. */
891 static boolean
892 swr_create_resolve_resource(struct pipe_screen *_screen,
893 struct swr_resource *msaa_res)
894 {
895 struct swr_screen *screen = swr_screen(_screen);
896
897 /* If resource is multisample, create a single-sample resolve resource */
898 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
899 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
900
901 /* Create a single-sample copy of the resource. Copy the original
902 * resource parameters and set flag to prevent recursion when re-calling
903 * resource_create */
904 struct pipe_resource alt_template = msaa_res->base;
905 alt_template.nr_samples = 0;
906 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
907
908 /* Note: Display_target is a special single-sample resource, only the
909 * display_target has been created already. */
910 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
911 | PIPE_BIND_SHARED)) {
912 /* Allocate the multisample buffers. */
913 if (!swr_texture_layout(screen, msaa_res, true))
914 return false;
915
916 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
917 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
918 alt_template.bind = PIPE_BIND_RENDER_TARGET;
919 }
920
921 /* Allocate single-sample resolve surface */
922 struct pipe_resource *alt;
923 alt = _screen->resource_create(_screen, &alt_template);
924 if (!alt)
925 return false;
926
927 /* Attach it to the multisample resource */
928 msaa_res->resolve_target = alt;
929
930 /* Hang resolve surface state off the multisample surface state to so
931 * StoreTiles knows where to resolve the surface. */
932 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
933 }
934
935 return true; /* success */
936 }
937
938 static struct pipe_resource *
939 swr_resource_create(struct pipe_screen *_screen,
940 const struct pipe_resource *templat)
941 {
942 struct swr_screen *screen = swr_screen(_screen);
943 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
944 if (!res)
945 return NULL;
946
947 res->base = *templat;
948 pipe_reference_init(&res->base.reference, 1);
949 res->base.screen = &screen->base;
950
951 if (swr_resource_is_texture(&res->base)) {
952 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
953 | PIPE_BIND_SHARED)) {
954 /* displayable surface
955 * first call swr_texture_layout without allocating to finish
956 * filling out the SWR_SURFACE_STATE in res */
957 swr_texture_layout(screen, res, false);
958 if (!swr_displaytarget_layout(screen, res))
959 goto fail;
960 } else {
961 /* texture map */
962 if (!swr_texture_layout(screen, res, true))
963 goto fail;
964 }
965
966 /* If resource was multisample, create resolve resource and attach
967 * it to multisample resource. */
968 if (!swr_create_resolve_resource(_screen, res))
969 goto fail;
970
971 } else {
972 /* other data (vertex buffer, const buffer, etc) */
973 assert(util_format_get_blocksize(templat->format) == 1);
974 assert(templat->height0 == 1);
975 assert(templat->depth0 == 1);
976 assert(templat->last_level == 0);
977
978 /* Easiest to just call swr_texture_layout, as it sets up
979 * SWR_SURFACE_STATE in res */
980 if (!swr_texture_layout(screen, res, true))
981 goto fail;
982 }
983
984 return &res->base;
985
986 fail:
987 FREE(res);
988 return NULL;
989 }
990
991 static void
992 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
993 {
994 struct swr_screen *screen = swr_screen(p_screen);
995 struct swr_resource *spr = swr_resource(pt);
996
997 if (spr->display_target) {
998 /* If resource is display target, winsys manages the buffer and will
999 * free it on displaytarget_destroy. */
1000 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1001
1002 struct sw_winsys *winsys = screen->winsys;
1003 winsys->displaytarget_destroy(winsys, spr->display_target);
1004
1005 if (spr->swr.numSamples > 1) {
1006 /* Free an attached resolve resource */
1007 struct swr_resource *alt = swr_resource(spr->resolve_target);
1008 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1009
1010 /* Free multisample buffer */
1011 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1012 }
1013 } else {
1014 /* For regular resources, defer deletion */
1015 swr_resource_unused(pt);
1016
1017 if (spr->swr.numSamples > 1) {
1018 /* Free an attached resolve resource */
1019 struct swr_resource *alt = swr_resource(spr->resolve_target);
1020 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1021 }
1022
1023 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1024 swr_fence_work_free(screen->flush_fence,
1025 (void*)(spr->secondary.xpBaseAddress), true);
1026
1027 /* If work queue grows too large, submit a fence to force queue to
1028 * drain. This is mainly to decrease the amount of memory used by the
1029 * piglit streaming-texture-leak test */
1030 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1031 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1032 }
1033
1034 FREE(spr);
1035 }
1036
1037
1038 static void
1039 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1040 struct pipe_resource *resource,
1041 unsigned level,
1042 unsigned layer,
1043 void *context_private,
1044 struct pipe_box *sub_box)
1045 {
1046 struct swr_screen *screen = swr_screen(p_screen);
1047 struct sw_winsys *winsys = screen->winsys;
1048 struct swr_resource *spr = swr_resource(resource);
1049 struct pipe_context *pipe = screen->pipe;
1050 struct swr_context *ctx = swr_context(pipe);
1051
1052 if (pipe) {
1053 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1054 swr_resource_unused(resource);
1055 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1056 }
1057
1058 /* Multisample resolved into resolve_target at flush with store_resource */
1059 if (pipe && spr->swr.numSamples > 1) {
1060 struct pipe_resource *resolve_target = spr->resolve_target;
1061
1062 /* Once resolved, copy into display target */
1063 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1064
1065 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1066 PIPE_TRANSFER_WRITE);
1067 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1068 winsys->displaytarget_unmap(winsys, spr->display_target);
1069 }
1070
1071 debug_assert(spr->display_target);
1072 if (spr->display_target)
1073 winsys->displaytarget_display(
1074 winsys, spr->display_target, context_private, sub_box);
1075 }
1076
1077
1078 void
1079 swr_destroy_screen_internal(struct swr_screen **screen)
1080 {
1081 struct pipe_screen *p_screen = &(*screen)->base;
1082
1083 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1084 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1085
1086 JitDestroyContext((*screen)->hJitMgr);
1087
1088 if ((*screen)->pLibrary)
1089 util_dl_close((*screen)->pLibrary);
1090
1091 FREE(*screen);
1092 *screen = NULL;
1093 }
1094
1095
1096 static void
1097 swr_destroy_screen(struct pipe_screen *p_screen)
1098 {
1099 struct swr_screen *screen = swr_screen(p_screen);
1100 struct sw_winsys *winsys = screen->winsys;
1101
1102 fprintf(stderr, "SWR destroy screen!\n");
1103
1104 if (winsys->destroy)
1105 winsys->destroy(winsys);
1106
1107 swr_destroy_screen_internal(&screen);
1108 }
1109
1110
1111 static void
1112 swr_validate_env_options(struct swr_screen *screen)
1113 {
1114 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1115 * copied to scratch space on a draw. Past this, the draw will access
1116 * user-buffer directly and then block. This is faster than queuing many
1117 * large client draws. */
1118 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1119 int client_copy_limit =
1120 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1121 if (client_copy_limit > 0)
1122 screen->client_copy_limit = client_copy_limit;
1123
1124 /* XXX msaa under development, disable by default for now */
1125 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1126
1127 /* validate env override values, within range and power of 2 */
1128 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1129 if (msaa_max_count != 1) {
1130 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1131 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1132 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1133 fprintf(stderr, "must be power of 2 between 1 and %d" \
1134 " (or 1 to disable msaa)\n",
1135 SWR_MAX_NUM_MULTISAMPLES);
1136 msaa_max_count = 1;
1137 }
1138
1139 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1140 if (msaa_max_count == 1)
1141 fprintf(stderr, "(msaa disabled)\n");
1142
1143 screen->msaa_max_count = msaa_max_count;
1144 }
1145
1146 screen->msaa_force_enable = debug_get_bool_option(
1147 "SWR_MSAA_FORCE_ENABLE", false);
1148 if (screen->msaa_force_enable)
1149 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1150 }
1151
1152
1153 struct pipe_screen *
1154 swr_create_screen_internal(struct sw_winsys *winsys)
1155 {
1156 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1157
1158 if (!screen)
1159 return NULL;
1160
1161 if (!lp_build_init()) {
1162 FREE(screen);
1163 return NULL;
1164 }
1165
1166 screen->winsys = winsys;
1167 screen->base.get_name = swr_get_name;
1168 screen->base.get_vendor = swr_get_vendor;
1169 screen->base.is_format_supported = swr_is_format_supported;
1170 screen->base.context_create = swr_create_context;
1171 screen->base.can_create_resource = swr_can_create_resource;
1172
1173 screen->base.destroy = swr_destroy_screen;
1174 screen->base.get_param = swr_get_param;
1175 screen->base.get_shader_param = swr_get_shader_param;
1176 screen->base.get_paramf = swr_get_paramf;
1177
1178 screen->base.resource_create = swr_resource_create;
1179 screen->base.resource_destroy = swr_resource_destroy;
1180
1181 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1182
1183 // Pass in "" for architecture for run-time determination
1184 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1185
1186 swr_fence_init(&screen->base);
1187
1188 swr_validate_env_options(screen);
1189
1190 return &screen->base;
1191 }
1192