1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
39 #include "state_tracker/sw_winsys.h"
42 #include "gallivm/lp_bld_limits.h"
47 #include "memory/TilingFunctions.h"
52 /* MSVC case instensitive compare */
53 #if defined(PIPE_CC_MSVC)
54 #define strcasecmp lstrcmpiA
59 * XXX Check max texture size values against core and sampler.
61 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
62 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
63 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
64 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
65 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
68 swr_get_name(struct pipe_screen
*screen
)
74 swr_get_vendor(struct pipe_screen
*screen
)
76 return "Intel Corporation";
80 swr_is_format_supported(struct pipe_screen
*screen
,
81 enum pipe_format format
,
82 enum pipe_texture_target target
,
83 unsigned sample_count
,
86 struct sw_winsys
*winsys
= swr_screen(screen
)->winsys
;
87 const struct util_format_description
*format_desc
;
89 assert(target
== PIPE_BUFFER
|| target
== PIPE_TEXTURE_1D
90 || target
== PIPE_TEXTURE_1D_ARRAY
91 || target
== PIPE_TEXTURE_2D
92 || target
== PIPE_TEXTURE_2D_ARRAY
93 || target
== PIPE_TEXTURE_RECT
94 || target
== PIPE_TEXTURE_3D
95 || target
== PIPE_TEXTURE_CUBE
96 || target
== PIPE_TEXTURE_CUBE_ARRAY
);
98 format_desc
= util_format_description(format
);
102 if (sample_count
> 1)
106 & (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
)) {
107 if (!winsys
->is_displaytarget_format_supported(winsys
, bind
, format
))
111 if (bind
& PIPE_BIND_RENDER_TARGET
) {
112 if (format_desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
115 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
119 * Although possible, it is unnatural to render into compressed or YUV
120 * surfaces. So disable these here to avoid going into weird paths
121 * inside the state trackers.
123 if (format_desc
->block
.width
!= 1 || format_desc
->block
.height
!= 1)
127 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
128 if (format_desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
131 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
135 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
||
136 format_desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
) {
140 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
141 format
!= PIPE_FORMAT_ETC1_RGB8
) {
145 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
146 return util_format_s3tc_enabled
;
153 swr_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
156 case PIPE_CAP_NPOT_TEXTURES
:
157 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
158 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
160 case PIPE_CAP_TWO_SIDED_STENCIL
:
164 case PIPE_CAP_ANISOTROPIC_FILTER
:
166 case PIPE_CAP_POINT_SPRITE
:
168 case PIPE_CAP_MAX_RENDER_TARGETS
:
169 return PIPE_MAX_COLOR_BUFS
;
170 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
172 case PIPE_CAP_OCCLUSION_QUERY
:
173 case PIPE_CAP_QUERY_TIME_ELAPSED
:
174 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
176 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
178 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
180 case PIPE_CAP_TEXTURE_SWIZZLE
:
182 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
184 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
185 return SWR_MAX_TEXTURE_2D_LEVELS
;
186 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
187 return SWR_MAX_TEXTURE_3D_LEVELS
;
188 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
189 return SWR_MAX_TEXTURE_CUBE_LEVELS
;
190 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
192 case PIPE_CAP_INDEP_BLEND_ENABLE
:
194 case PIPE_CAP_INDEP_BLEND_FUNC
:
196 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
197 return 0; // Don't support lower left frag coord.
198 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
199 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
200 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
202 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
204 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
205 return MAX_SO_STREAMS
;
206 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
207 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
208 return MAX_ATTRIBUTES
;
209 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
210 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
212 case PIPE_CAP_MAX_VERTEX_STREAMS
:
214 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
216 case PIPE_CAP_PRIMITIVE_RESTART
:
218 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
220 case PIPE_CAP_TGSI_INSTANCEID
:
221 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
222 case PIPE_CAP_START_INSTANCE
:
224 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
225 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
227 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
228 return SWR_MAX_TEXTURE_ARRAY_LAYERS
;
229 case PIPE_CAP_MIN_TEXEL_OFFSET
:
231 case PIPE_CAP_MAX_TEXEL_OFFSET
:
233 case PIPE_CAP_CONDITIONAL_RENDER
:
235 case PIPE_CAP_TEXTURE_BARRIER
:
237 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
238 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
240 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
242 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
244 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
246 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
248 case PIPE_CAP_COMPUTE
:
250 case PIPE_CAP_USER_VERTEX_BUFFERS
:
251 case PIPE_CAP_USER_INDEX_BUFFERS
:
252 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
253 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
254 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
256 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
258 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
259 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
260 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
261 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
262 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
263 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
265 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
267 case PIPE_CAP_QUERY_TIMESTAMP
:
269 case PIPE_CAP_CUBE_MAP_ARRAY
:
271 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
273 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
275 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
277 case PIPE_CAP_TGSI_TEXCOORD
:
278 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
280 case PIPE_CAP_MAX_VIEWPORTS
:
282 case PIPE_CAP_ENDIANNESS
:
283 return PIPE_ENDIAN_NATIVE
;
284 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
285 case PIPE_CAP_TEXTURE_GATHER_SM5
:
287 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
289 case PIPE_CAP_TEXTURE_QUERY_LOD
:
290 case PIPE_CAP_SAMPLE_SHADING
:
291 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
292 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
293 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
294 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
296 case PIPE_CAP_FAKE_SW_MSAA
:
298 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
299 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
301 case PIPE_CAP_DRAW_INDIRECT
:
304 case PIPE_CAP_VENDOR_ID
:
306 case PIPE_CAP_DEVICE_ID
:
308 case PIPE_CAP_ACCELERATED
:
310 case PIPE_CAP_VIDEO_MEMORY
: {
311 /* XXX: Do we want to return the full amount of system memory ? */
312 uint64_t system_memory
;
314 if (!os_get_total_physical_memory(&system_memory
))
317 return (int)(system_memory
>> 20);
321 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
323 case PIPE_CAP_CLIP_HALFZ
:
325 case PIPE_CAP_VERTEXID_NOBASE
:
327 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
329 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
331 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
333 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
335 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
337 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
339 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
340 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
342 case PIPE_CAP_CULL_DISTANCE
:
344 case PIPE_CAP_TGSI_TXQS
:
345 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
346 case PIPE_CAP_SHAREABLE_SHADERS
:
347 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
348 case PIPE_CAP_CLEAR_TEXTURE
:
349 case PIPE_CAP_DRAW_PARAMETERS
:
350 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
351 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
352 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
353 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
354 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
355 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
356 case PIPE_CAP_INVALIDATE_BUFFER
:
357 case PIPE_CAP_GENERATE_MIPMAP
:
358 case PIPE_CAP_STRING_MARKER
:
359 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
360 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
361 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
362 case PIPE_CAP_QUERY_MEMORY_INFO
:
363 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
364 case PIPE_CAP_PCI_GROUP
:
365 case PIPE_CAP_PCI_BUS
:
366 case PIPE_CAP_PCI_DEVICE
:
367 case PIPE_CAP_PCI_FUNCTION
:
368 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
369 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
370 case PIPE_CAP_TGSI_VOTE
:
371 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
372 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
373 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
374 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
378 /* should only get here on unhandled cases */
379 debug_printf("Unexpected PIPE_CAP %d query\n", param
);
384 swr_get_shader_param(struct pipe_screen
*screen
,
386 enum pipe_shader_cap param
)
388 if (shader
== PIPE_SHADER_VERTEX
|| shader
== PIPE_SHADER_FRAGMENT
)
389 return gallivm_get_shader_param(param
);
391 // Todo: geometry, tesselation, compute
397 swr_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
400 case PIPE_CAPF_MAX_LINE_WIDTH
:
401 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
402 case PIPE_CAPF_MAX_POINT_WIDTH
:
403 return 255.0; /* arbitrary */
404 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
406 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
408 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
410 case PIPE_CAPF_GUARD_BAND_LEFT
:
411 case PIPE_CAPF_GUARD_BAND_TOP
:
412 case PIPE_CAPF_GUARD_BAND_RIGHT
:
413 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
416 /* should only get here on unhandled cases */
417 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
422 mesa_to_swr_format(enum pipe_format format
)
424 static const std::map
<pipe_format
,SWR_FORMAT
> mesa2swr
= {
425 {PIPE_FORMAT_B8G8R8A8_UNORM
, B8G8R8A8_UNORM
},
426 {PIPE_FORMAT_B8G8R8X8_UNORM
, B8G8R8X8_UNORM
},
427 {PIPE_FORMAT_B5G5R5A1_UNORM
, B5G5R5A1_UNORM
},
428 {PIPE_FORMAT_B4G4R4A4_UNORM
, B4G4R4A4_UNORM
},
429 {PIPE_FORMAT_B5G6R5_UNORM
, B5G6R5_UNORM
},
430 {PIPE_FORMAT_R10G10B10A2_UNORM
, R10G10B10A2_UNORM
},
431 {PIPE_FORMAT_A8_UNORM
, A8_UNORM
},
432 {PIPE_FORMAT_Z16_UNORM
, R16_UNORM
}, // z
433 {PIPE_FORMAT_Z32_FLOAT
, R32_FLOAT
}, // z
434 {PIPE_FORMAT_Z24_UNORM_S8_UINT
, R24_UNORM_X8_TYPELESS
}, // z
435 {PIPE_FORMAT_Z24X8_UNORM
, R24_UNORM_X8_TYPELESS
}, // z
436 {PIPE_FORMAT_R32_FLOAT
, R32_FLOAT
},
437 {PIPE_FORMAT_R32G32_FLOAT
, R32G32_FLOAT
},
438 {PIPE_FORMAT_R32G32B32_FLOAT
, R32G32B32_FLOAT
},
439 {PIPE_FORMAT_R32G32B32A32_FLOAT
, R32G32B32A32_FLOAT
},
440 {PIPE_FORMAT_R32_USCALED
, R32_USCALED
},
441 {PIPE_FORMAT_R32G32_USCALED
, R32G32_USCALED
},
442 {PIPE_FORMAT_R32G32B32_USCALED
, R32G32B32_USCALED
},
443 {PIPE_FORMAT_R32G32B32A32_USCALED
, R32G32B32A32_USCALED
},
444 {PIPE_FORMAT_R32_SSCALED
, R32_SSCALED
},
445 {PIPE_FORMAT_R32G32_SSCALED
, R32G32_SSCALED
},
446 {PIPE_FORMAT_R32G32B32_SSCALED
, R32G32B32_SSCALED
},
447 {PIPE_FORMAT_R32G32B32A32_SSCALED
, R32G32B32A32_SSCALED
},
448 {PIPE_FORMAT_R16_UNORM
, R16_UNORM
},
449 {PIPE_FORMAT_R16G16_UNORM
, R16G16_UNORM
},
450 {PIPE_FORMAT_R16G16B16_UNORM
, R16G16B16_UNORM
},
451 {PIPE_FORMAT_R16G16B16A16_UNORM
, R16G16B16A16_UNORM
},
452 {PIPE_FORMAT_R16_USCALED
, R16_USCALED
},
453 {PIPE_FORMAT_R16G16_USCALED
, R16G16_USCALED
},
454 {PIPE_FORMAT_R16G16B16_USCALED
, R16G16B16_USCALED
},
455 {PIPE_FORMAT_R16G16B16A16_USCALED
, R16G16B16A16_USCALED
},
456 {PIPE_FORMAT_R16_SNORM
, R16_SNORM
},
457 {PIPE_FORMAT_R16G16_SNORM
, R16G16_SNORM
},
458 {PIPE_FORMAT_R16G16B16_SNORM
, R16G16B16_SNORM
},
459 {PIPE_FORMAT_R16G16B16A16_SNORM
, R16G16B16A16_SNORM
},
460 {PIPE_FORMAT_R16_SSCALED
, R16_SSCALED
},
461 {PIPE_FORMAT_R16G16_SSCALED
, R16G16_SSCALED
},
462 {PIPE_FORMAT_R16G16B16_SSCALED
, R16G16B16_SSCALED
},
463 {PIPE_FORMAT_R16G16B16A16_SSCALED
, R16G16B16A16_SSCALED
},
464 {PIPE_FORMAT_R8_UNORM
, R8_UNORM
},
465 {PIPE_FORMAT_R8G8_UNORM
, R8G8_UNORM
},
466 {PIPE_FORMAT_R8G8B8_UNORM
, R8G8B8_UNORM
},
467 {PIPE_FORMAT_R8G8B8A8_UNORM
, R8G8B8A8_UNORM
},
468 {PIPE_FORMAT_R8_USCALED
, R8_USCALED
},
469 {PIPE_FORMAT_R8G8_USCALED
, R8G8_USCALED
},
470 {PIPE_FORMAT_R8G8B8_USCALED
, R8G8B8_USCALED
},
471 {PIPE_FORMAT_R8G8B8A8_USCALED
, R8G8B8A8_USCALED
},
472 {PIPE_FORMAT_R8_SNORM
, R8_SNORM
},
473 {PIPE_FORMAT_R8G8_SNORM
, R8G8_SNORM
},
474 {PIPE_FORMAT_R8G8B8_SNORM
, R8G8B8_SNORM
},
475 {PIPE_FORMAT_R8G8B8A8_SNORM
, R8G8B8A8_SNORM
},
476 {PIPE_FORMAT_R8_SSCALED
, R8_SSCALED
},
477 {PIPE_FORMAT_R8G8_SSCALED
, R8G8_SSCALED
},
478 {PIPE_FORMAT_R8G8B8_SSCALED
, R8G8B8_SSCALED
},
479 {PIPE_FORMAT_R8G8B8A8_SSCALED
, R8G8B8A8_SSCALED
},
480 {PIPE_FORMAT_R16_FLOAT
, R16_FLOAT
},
481 {PIPE_FORMAT_R16G16_FLOAT
, R16G16_FLOAT
},
482 {PIPE_FORMAT_R16G16B16_FLOAT
, R16G16B16_FLOAT
},
483 {PIPE_FORMAT_R16G16B16A16_FLOAT
, R16G16B16A16_FLOAT
},
485 {PIPE_FORMAT_R8G8B8_SRGB
, R8G8B8_UNORM_SRGB
},
486 {PIPE_FORMAT_B8G8R8A8_SRGB
, B8G8R8A8_UNORM_SRGB
},
487 {PIPE_FORMAT_B8G8R8X8_SRGB
, B8G8R8X8_UNORM_SRGB
},
488 {PIPE_FORMAT_R8G8B8A8_SRGB
, R8G8B8A8_UNORM_SRGB
},
490 {PIPE_FORMAT_B5G5R5X1_UNORM
, B5G5R5X1_UNORM
},
491 {PIPE_FORMAT_R10G10B10A2_USCALED
, R10G10B10A2_USCALED
},
492 {PIPE_FORMAT_R11G11B10_FLOAT
, R11G11B10_FLOAT
},
493 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
, R32_FLOAT_X8X24_TYPELESS
}, // z
494 {PIPE_FORMAT_R10G10B10X2_USCALED
, R10G10B10X2_USCALED
},
495 {PIPE_FORMAT_B10G10R10A2_UNORM
, B10G10R10A2_UNORM
},
496 {PIPE_FORMAT_R8G8B8X8_UNORM
, R8G8B8X8_UNORM
},
498 {PIPE_FORMAT_A16_UNORM
, A16_UNORM
},
499 {PIPE_FORMAT_A16_FLOAT
, A16_FLOAT
},
500 {PIPE_FORMAT_A32_FLOAT
, A32_FLOAT
},
502 {PIPE_FORMAT_R10G10B10A2_SSCALED
, R10G10B10A2_SSCALED
},
503 {PIPE_FORMAT_R10G10B10A2_SNORM
, R10G10B10A2_SNORM
},
505 {PIPE_FORMAT_B10G10R10A2_USCALED
, B10G10R10A2_USCALED
},
506 {PIPE_FORMAT_B10G10R10A2_SSCALED
, B10G10R10A2_SSCALED
},
507 {PIPE_FORMAT_B10G10R10A2_SNORM
, B10G10R10A2_SNORM
},
509 {PIPE_FORMAT_R8_UINT
, R8_UINT
},
510 {PIPE_FORMAT_R8G8_UINT
, R8G8_UINT
},
511 {PIPE_FORMAT_R8G8B8_UINT
, R8G8B8_UINT
},
512 {PIPE_FORMAT_R8G8B8A8_UINT
, R8G8B8A8_UINT
},
514 {PIPE_FORMAT_R8_SINT
, R8_SINT
},
515 {PIPE_FORMAT_R8G8_SINT
, R8G8_SINT
},
516 {PIPE_FORMAT_R8G8B8_SINT
, R8G8B8_SINT
},
517 {PIPE_FORMAT_R8G8B8A8_SINT
, R8G8B8A8_SINT
},
519 {PIPE_FORMAT_R16_UINT
, R16_UINT
},
520 {PIPE_FORMAT_R16G16_UINT
, R16G16_UINT
},
521 {PIPE_FORMAT_R16G16B16_UINT
, R16G16B16_UINT
},
522 {PIPE_FORMAT_R16G16B16A16_UINT
, R16G16B16A16_UINT
},
524 {PIPE_FORMAT_R16_SINT
, R16_SINT
},
525 {PIPE_FORMAT_R16G16_SINT
, R16G16_SINT
},
526 {PIPE_FORMAT_R16G16B16_SINT
, R16G16B16_SINT
},
527 {PIPE_FORMAT_R16G16B16A16_SINT
, R16G16B16A16_SINT
},
529 {PIPE_FORMAT_R32_UINT
, R32_UINT
},
530 {PIPE_FORMAT_R32G32_UINT
, R32G32_UINT
},
531 {PIPE_FORMAT_R32G32B32_UINT
, R32G32B32_UINT
},
532 {PIPE_FORMAT_R32G32B32A32_UINT
, R32G32B32A32_UINT
},
534 {PIPE_FORMAT_R32_SINT
, R32_SINT
},
535 {PIPE_FORMAT_R32G32_SINT
, R32G32_SINT
},
536 {PIPE_FORMAT_R32G32B32_SINT
, R32G32B32_SINT
},
537 {PIPE_FORMAT_R32G32B32A32_SINT
, R32G32B32A32_SINT
},
539 {PIPE_FORMAT_B10G10R10A2_UINT
, B10G10R10A2_UINT
},
541 {PIPE_FORMAT_B10G10R10X2_UNORM
, B10G10R10X2_UNORM
},
542 {PIPE_FORMAT_R16G16B16X16_UNORM
, R16G16B16X16_UNORM
},
543 {PIPE_FORMAT_R16G16B16X16_FLOAT
, R16G16B16X16_FLOAT
},
544 {PIPE_FORMAT_R32G32B32X32_FLOAT
, R32G32B32X32_FLOAT
},
545 {PIPE_FORMAT_R10G10B10A2_UINT
, R10G10B10A2_UINT
},
547 {PIPE_FORMAT_B5G6R5_SRGB
, B5G6R5_UNORM_SRGB
},
549 /* These formats have entries in SWR but don't have Load/StoreTile
550 * implementations. That means these aren't renderable, and thus having
551 * a mapping entry here is detrimental.
555 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
556 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
557 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
558 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
559 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
561 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
562 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
564 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
565 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
566 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
568 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
569 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
570 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
572 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
573 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
574 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
575 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
577 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
578 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
579 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
580 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
581 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
582 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
583 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
584 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
586 {PIPE_FORMAT_I8_UINT, I8_UINT},
587 {PIPE_FORMAT_L8_UINT, L8_UINT},
588 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
590 {PIPE_FORMAT_I8_SINT, I8_SINT},
591 {PIPE_FORMAT_L8_SINT, L8_SINT},
592 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
597 auto it
= mesa2swr
.find(format
);
598 if (it
== mesa2swr
.end())
599 return (SWR_FORMAT
)-1;
605 swr_displaytarget_layout(struct swr_screen
*screen
, struct swr_resource
*res
)
607 struct sw_winsys
*winsys
= screen
->winsys
;
608 struct sw_displaytarget
*dt
;
610 const unsigned width
= align(res
->swr
.width
, res
->swr
.halign
);
611 const unsigned height
= align(res
->swr
.height
, res
->swr
.valign
);
614 dt
= winsys
->displaytarget_create(winsys
,
624 void *map
= winsys
->displaytarget_map(winsys
, dt
, 0);
626 res
->display_target
= dt
;
627 res
->swr
.pBaseAddress
= (uint8_t*) map
;
629 /* Clear the display target surface */
631 memset(map
, 0, height
* stride
);
633 winsys
->displaytarget_unmap(winsys
, dt
);
639 swr_texture_layout(struct swr_screen
*screen
,
640 struct swr_resource
*res
,
643 struct pipe_resource
*pt
= &res
->base
;
645 pipe_format fmt
= pt
->format
;
646 const struct util_format_description
*desc
= util_format_description(fmt
);
648 res
->has_depth
= util_format_has_depth(desc
);
649 res
->has_stencil
= util_format_has_stencil(desc
);
651 if (res
->has_stencil
&& !res
->has_depth
)
652 fmt
= PIPE_FORMAT_R8_UINT
;
654 /* We always use the SWR layout. For 2D and 3D textures this looks like:
656 * |<------- pitch ------->|
657 * +=======================+-------
663 * +-----------+-----------+ |
665 * | Level 1 | L3L3 | |
667 * +===========+===========+-------
673 * +-----------+-----------+
677 * +===========+===========+
679 * The overall width in bytes is known as the pitch, while the overall
680 * height in rows is the qpitch. Array slices are laid out logically below
681 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
682 * just invalid for the higher array numbers (since depth is also
683 * minified). 1D and 1D array surfaces are stored effectively the same way,
684 * except that pitch never plays into it. All the levels are logically
685 * adjacent to each other on the X axis. The qpitch becomes the number of
686 * elements between array slices, while the pitch is unused.
688 * Each level's sizes are subject to the valign and halign settings of the
689 * surface. For compressed formats that swr is unaware of, we will use an
690 * appropriately-sized uncompressed format, and scale the widths/heights.
692 * This surface is stored inside res->swr. For depth/stencil textures,
693 * res->secondary will have an identically-laid-out but R8_UINT-formatted
694 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
695 * texels, to simplify map/unmap logic which copies the stencil values
699 res
->swr
.width
= pt
->width0
;
700 res
->swr
.height
= pt
->height0
;
701 res
->swr
.type
= swr_convert_target_type(pt
->target
);
702 res
->swr
.tileMode
= SWR_TILE_NONE
;
703 res
->swr
.format
= mesa_to_swr_format(fmt
);
704 res
->swr
.numSamples
= std::max(1u, pt
->nr_samples
);
706 if (pt
->bind
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DEPTH_STENCIL
)) {
707 res
->swr
.halign
= KNOB_MACROTILE_X_DIM
;
708 res
->swr
.valign
= KNOB_MACROTILE_Y_DIM
;
714 unsigned halign
= res
->swr
.halign
* util_format_get_blockwidth(fmt
);
715 unsigned width
= align(pt
->width0
, halign
);
716 if (pt
->target
== PIPE_TEXTURE_1D
|| pt
->target
== PIPE_TEXTURE_1D_ARRAY
) {
717 for (int level
= 1; level
<= pt
->last_level
; level
++)
718 width
+= align(u_minify(pt
->width0
, level
), halign
);
719 res
->swr
.pitch
= util_format_get_blocksize(fmt
);
720 res
->swr
.qpitch
= util_format_get_nblocksx(fmt
, width
);
722 // The pitch is the overall width of the texture in bytes. Most of the
723 // time this is the pitch of level 0 since all the other levels fit
724 // underneath it. However in some degenerate situations, the width of
725 // level1 + level2 may be larger. In that case, we use those
726 // widths. This can happen if, e.g. halign is 32, and the width of level
727 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
728 // be 32 each, adding up to 64.
729 unsigned valign
= res
->swr
.valign
* util_format_get_blockheight(fmt
);
730 if (pt
->last_level
> 1) {
731 width
= std::max
<uint32_t>(
733 align(u_minify(pt
->width0
, 1), halign
) +
734 align(u_minify(pt
->width0
, 2), halign
));
736 res
->swr
.pitch
= util_format_get_stride(fmt
, width
);
738 // The qpitch is controlled by either the height of the second LOD, or
739 // the combination of all the later LODs.
740 unsigned height
= align(pt
->height0
, valign
);
741 if (pt
->last_level
== 1) {
742 height
+= align(u_minify(pt
->height0
, 1), valign
);
743 } else if (pt
->last_level
> 1) {
744 unsigned level1
= align(u_minify(pt
->height0
, 1), valign
);
746 for (int level
= 2; level
<= pt
->last_level
; level
++) {
747 level2
+= align(u_minify(pt
->height0
, level
), valign
);
749 height
+= std::max(level1
, level2
);
751 res
->swr
.qpitch
= util_format_get_nblocksy(fmt
, height
);
754 if (pt
->target
== PIPE_TEXTURE_3D
)
755 res
->swr
.depth
= pt
->depth0
;
757 res
->swr
.depth
= pt
->array_size
;
759 // Fix up swr format if necessary so that LOD offset computation works
760 if (res
->swr
.format
== (SWR_FORMAT
)-1) {
761 switch (util_format_get_blocksize(fmt
)) {
763 unreachable("Unexpected format block size");
764 case 1: res
->swr
.format
= R8_UINT
; break;
765 case 2: res
->swr
.format
= R16_UINT
; break;
766 case 4: res
->swr
.format
= R32_UINT
; break;
768 if (util_format_is_compressed(fmt
))
769 res
->swr
.format
= BC4_UNORM
;
771 res
->swr
.format
= R32G32_UINT
;
774 if (util_format_is_compressed(fmt
))
775 res
->swr
.format
= BC5_UNORM
;
777 res
->swr
.format
= R32G32B32A32_UINT
;
782 for (int level
= 0; level
<= pt
->last_level
; level
++) {
783 res
->mip_offsets
[level
] =
784 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->swr
);
788 (size_t)res
->swr
.depth
* res
->swr
.qpitch
* res
->swr
.pitch
;
789 if (total_size
> SWR_MAX_TEXTURE_SIZE
)
793 res
->swr
.pBaseAddress
= (uint8_t *)AlignedMalloc(total_size
, 64);
795 if (res
->has_depth
&& res
->has_stencil
) {
796 res
->secondary
= res
->swr
;
797 res
->secondary
.format
= R8_UINT
;
798 res
->secondary
.pitch
= res
->swr
.pitch
/ util_format_get_blocksize(fmt
);
800 for (int level
= 0; level
<= pt
->last_level
; level
++) {
801 res
->secondary_mip_offsets
[level
] =
802 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->secondary
);
805 res
->secondary
.pBaseAddress
= (uint8_t *)AlignedMalloc(
806 res
->secondary
.depth
* res
->secondary
.qpitch
*
807 res
->secondary
.pitch
, 64);
815 swr_can_create_resource(struct pipe_screen
*screen
,
816 const struct pipe_resource
*templat
)
818 struct swr_resource res
;
819 memset(&res
, 0, sizeof(res
));
821 return swr_texture_layout(swr_screen(screen
), &res
, false);
824 static struct pipe_resource
*
825 swr_resource_create(struct pipe_screen
*_screen
,
826 const struct pipe_resource
*templat
)
828 struct swr_screen
*screen
= swr_screen(_screen
);
829 struct swr_resource
*res
= CALLOC_STRUCT(swr_resource
);
833 res
->base
= *templat
;
834 pipe_reference_init(&res
->base
.reference
, 1);
835 res
->base
.screen
= &screen
->base
;
837 if (swr_resource_is_texture(&res
->base
)) {
838 if (res
->base
.bind
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
839 | PIPE_BIND_SHARED
)) {
840 /* displayable surface
841 * first call swr_texture_layout without allocating to finish
842 * filling out the SWR_SURFAE_STATE in res */
843 swr_texture_layout(screen
, res
, false);
844 if (!swr_displaytarget_layout(screen
, res
))
848 if (!swr_texture_layout(screen
, res
, true))
852 /* other data (vertex buffer, const buffer, etc) */
853 assert(util_format_get_blocksize(templat
->format
) == 1);
854 assert(templat
->height0
== 1);
855 assert(templat
->depth0
== 1);
856 assert(templat
->last_level
== 0);
858 /* Easiest to just call swr_texture_layout, as it sets up
859 * SWR_SURFAE_STATE in res */
860 if (!swr_texture_layout(screen
, res
, true))
872 swr_resource_destroy(struct pipe_screen
*p_screen
, struct pipe_resource
*pt
)
874 struct swr_screen
*screen
= swr_screen(p_screen
);
875 struct swr_resource
*spr
= swr_resource(pt
);
876 struct pipe_context
*pipe
= screen
->pipe
;
878 /* Only wait on fence if the resource is being used */
879 if (pipe
&& spr
->status
) {
880 /* But, if there's no fence pending, submit one.
881 * XXX: Remove once draw timestamps are implmented. */
882 if (!swr_is_fence_pending(screen
->flush_fence
))
883 swr_fence_submit(swr_context(pipe
), screen
->flush_fence
);
885 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
886 swr_resource_unused(pt
);
890 * Free resource primary surface. If resource is display target, winsys
891 * manages the buffer and will free it on displaytarget_destroy.
893 if (spr
->display_target
) {
895 struct sw_winsys
*winsys
= screen
->winsys
;
896 winsys
->displaytarget_destroy(winsys
, spr
->display_target
);
898 AlignedFree(spr
->swr
.pBaseAddress
);
900 AlignedFree(spr
->secondary
.pBaseAddress
);
907 swr_flush_frontbuffer(struct pipe_screen
*p_screen
,
908 struct pipe_resource
*resource
,
911 void *context_private
,
912 struct pipe_box
*sub_box
)
914 struct swr_screen
*screen
= swr_screen(p_screen
);
915 struct sw_winsys
*winsys
= screen
->winsys
;
916 struct swr_resource
*spr
= swr_resource(resource
);
917 struct pipe_context
*pipe
= screen
->pipe
;
920 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
921 swr_resource_unused(resource
);
922 SwrEndFrame(swr_context(pipe
)->swrContext
);
925 debug_assert(spr
->display_target
);
926 if (spr
->display_target
)
927 winsys
->displaytarget_display(
928 winsys
, spr
->display_target
, context_private
, sub_box
);
933 swr_destroy_screen(struct pipe_screen
*p_screen
)
935 struct swr_screen
*screen
= swr_screen(p_screen
);
936 struct sw_winsys
*winsys
= screen
->winsys
;
938 fprintf(stderr
, "SWR destroy screen!\n");
940 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
941 swr_fence_reference(p_screen
, &screen
->flush_fence
, NULL
);
943 JitDestroyContext(screen
->hJitMgr
);
946 winsys
->destroy(winsys
);
953 swr_create_screen_internal(struct sw_winsys
*winsys
)
955 struct swr_screen
*screen
= CALLOC_STRUCT(swr_screen
);
960 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
961 g_GlobalKnobs
.MAX_PRIMS_PER_DRAW
.Value(49152);
964 screen
->winsys
= winsys
;
965 screen
->base
.get_name
= swr_get_name
;
966 screen
->base
.get_vendor
= swr_get_vendor
;
967 screen
->base
.is_format_supported
= swr_is_format_supported
;
968 screen
->base
.context_create
= swr_create_context
;
969 screen
->base
.can_create_resource
= swr_can_create_resource
;
971 screen
->base
.destroy
= swr_destroy_screen
;
972 screen
->base
.get_param
= swr_get_param
;
973 screen
->base
.get_shader_param
= swr_get_shader_param
;
974 screen
->base
.get_paramf
= swr_get_paramf
;
976 screen
->base
.resource_create
= swr_resource_create
;
977 screen
->base
.resource_destroy
= swr_resource_destroy
;
979 screen
->base
.flush_frontbuffer
= swr_flush_frontbuffer
;
981 screen
->hJitMgr
= JitCreateContext(KNOB_SIMD_WIDTH
, KNOB_ARCH_STR
, "swr");
983 swr_fence_init(&screen
->base
);
985 util_format_s3tc_init();
987 return &screen
->base
;