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[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned bind)
89 {
90 struct swr_screen *screen = swr_screen(_screen);
91 struct sw_winsys *winsys = screen->winsys;
92 const struct util_format_description *format_desc;
93
94 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
95 || target == PIPE_TEXTURE_1D_ARRAY
96 || target == PIPE_TEXTURE_2D
97 || target == PIPE_TEXTURE_2D_ARRAY
98 || target == PIPE_TEXTURE_RECT
99 || target == PIPE_TEXTURE_3D
100 || target == PIPE_TEXTURE_CUBE
101 || target == PIPE_TEXTURE_CUBE_ARRAY);
102
103 format_desc = util_format_description(format);
104 if (!format_desc)
105 return FALSE;
106
107 if ((sample_count > screen->msaa_max_count)
108 || !util_is_power_of_two(sample_count))
109 return FALSE;
110
111 if (bind & PIPE_BIND_DISPLAY_TARGET) {
112 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
113 return FALSE;
114 }
115
116 if (bind & PIPE_BIND_RENDER_TARGET) {
117 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
118 return FALSE;
119
120 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
121 return FALSE;
122
123 /*
124 * Although possible, it is unnatural to render into compressed or YUV
125 * surfaces. So disable these here to avoid going into weird paths
126 * inside the state trackers.
127 */
128 if (format_desc->block.width != 1 || format_desc->block.height != 1)
129 return FALSE;
130 }
131
132 if (bind & PIPE_BIND_DEPTH_STENCIL) {
133 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
134 return FALSE;
135
136 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
137 return FALSE;
138 }
139
140 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
141 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
142 return FALSE;
143 }
144
145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
146 format != PIPE_FORMAT_ETC1_RGB8) {
147 return FALSE;
148 }
149
150 return TRUE;
151 }
152
153 static int
154 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
155 {
156 switch (param) {
157 /* limits */
158 case PIPE_CAP_MAX_RENDER_TARGETS:
159 return PIPE_MAX_COLOR_BUFS;
160 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
161 return SWR_MAX_TEXTURE_2D_LEVELS;
162 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
163 return SWR_MAX_TEXTURE_3D_LEVELS;
164 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
165 return SWR_MAX_TEXTURE_CUBE_LEVELS;
166 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
167 return MAX_SO_STREAMS;
168 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
169 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
170 return MAX_ATTRIBUTES * 4;
171 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
172 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
173 return 1024;
174 case PIPE_CAP_MAX_VERTEX_STREAMS:
175 return 1;
176 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
177 return 2048;
178 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
179 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
180 case PIPE_CAP_MIN_TEXEL_OFFSET:
181 return -8;
182 case PIPE_CAP_MAX_TEXEL_OFFSET:
183 return 7;
184 case PIPE_CAP_GLSL_FEATURE_LEVEL:
185 return 330;
186 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
187 return 16;
188 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
189 return 64;
190 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
191 return 65536;
192 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
193 return 0;
194 case PIPE_CAP_MAX_VIEWPORTS:
195 return 1;
196 case PIPE_CAP_ENDIANNESS:
197 return PIPE_ENDIAN_NATIVE;
198 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
199 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
200 return 0;
201
202 /* supported features */
203 case PIPE_CAP_NPOT_TEXTURES:
204 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
205 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
206 case PIPE_CAP_SM3:
207 case PIPE_CAP_POINT_SPRITE:
208 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
209 case PIPE_CAP_OCCLUSION_QUERY:
210 case PIPE_CAP_QUERY_TIME_ELAPSED:
211 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
212 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
213 case PIPE_CAP_TEXTURE_SWIZZLE:
214 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
215 case PIPE_CAP_INDEP_BLEND_ENABLE:
216 case PIPE_CAP_INDEP_BLEND_FUNC:
217 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
218 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
219 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
220 case PIPE_CAP_DEPTH_CLIP_DISABLE:
221 case PIPE_CAP_PRIMITIVE_RESTART:
222 case PIPE_CAP_TGSI_INSTANCEID:
223 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
224 case PIPE_CAP_START_INSTANCE:
225 case PIPE_CAP_SEAMLESS_CUBE_MAP:
226 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
227 case PIPE_CAP_CONDITIONAL_RENDER:
228 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
229 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
230 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
231 case PIPE_CAP_USER_VERTEX_BUFFERS:
232 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
233 case PIPE_CAP_QUERY_TIMESTAMP:
234 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
235 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
236 case PIPE_CAP_DRAW_INDIRECT:
237 case PIPE_CAP_UMA:
238 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
239 case PIPE_CAP_CLIP_HALFZ:
240 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
241 case PIPE_CAP_DEPTH_BOUNDS_TEST:
242 case PIPE_CAP_CLEAR_TEXTURE:
243 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
244 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
245 case PIPE_CAP_CULL_DISTANCE:
246 case PIPE_CAP_CUBE_MAP_ARRAY:
247 case PIPE_CAP_DOUBLES:
248 return 1;
249
250 /* MSAA support
251 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
252 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
253 case PIPE_CAP_TEXTURE_MULTISAMPLE:
254 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
255 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
256 case PIPE_CAP_FAKE_SW_MSAA:
257 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
258
259 /* fetch jit change for 2-4GB buffers requires alignment */
260 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
261 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
262 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
263 return 1;
264
265 /* unsupported features */
266 case PIPE_CAP_ANISOTROPIC_FILTER:
267 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
268 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
269 case PIPE_CAP_SHADER_STENCIL_EXPORT:
270 case PIPE_CAP_TEXTURE_BARRIER:
271 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
272 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
273 case PIPE_CAP_COMPUTE:
274 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
275 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
276 case PIPE_CAP_TGSI_TEXCOORD:
277 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
278 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
279 case PIPE_CAP_TEXTURE_GATHER_SM5:
280 case PIPE_CAP_TEXTURE_QUERY_LOD:
281 case PIPE_CAP_SAMPLE_SHADING:
282 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
283 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
284 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
285 case PIPE_CAP_SAMPLER_VIEW_TARGET:
286 case PIPE_CAP_VERTEXID_NOBASE:
287 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
288 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
289 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
290 case PIPE_CAP_TGSI_TXQS:
291 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
292 case PIPE_CAP_SHAREABLE_SHADERS:
293 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
294 case PIPE_CAP_DRAW_PARAMETERS:
295 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
296 case PIPE_CAP_MULTI_DRAW_INDIRECT:
297 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
298 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
299 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
300 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
301 case PIPE_CAP_INVALIDATE_BUFFER:
302 case PIPE_CAP_GENERATE_MIPMAP:
303 case PIPE_CAP_STRING_MARKER:
304 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
305 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
306 case PIPE_CAP_QUERY_BUFFER_OBJECT:
307 case PIPE_CAP_QUERY_MEMORY_INFO:
308 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
309 case PIPE_CAP_PCI_GROUP:
310 case PIPE_CAP_PCI_BUS:
311 case PIPE_CAP_PCI_DEVICE:
312 case PIPE_CAP_PCI_FUNCTION:
313 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
314 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
315 case PIPE_CAP_TGSI_VOTE:
316 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
317 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
318 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
319 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
320 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
321 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
322 case PIPE_CAP_NATIVE_FENCE_FD:
323 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
324 case PIPE_CAP_TGSI_FS_FBFETCH:
325 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
326 case PIPE_CAP_INT64:
327 case PIPE_CAP_INT64_DIVMOD:
328 case PIPE_CAP_TGSI_TEX_TXF_LZ:
329 case PIPE_CAP_TGSI_CLOCK:
330 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
331 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
332 case PIPE_CAP_TGSI_BALLOT:
333 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
334 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
335 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
336 case PIPE_CAP_POST_DEPTH_COVERAGE:
337 case PIPE_CAP_BINDLESS_TEXTURE:
338 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
339 case PIPE_CAP_QUERY_SO_OVERFLOW:
340 case PIPE_CAP_MEMOBJ:
341 case PIPE_CAP_LOAD_CONSTBUF:
342 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
343 case PIPE_CAP_TILE_RASTER_ORDER:
344 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
345 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
346 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
347 case PIPE_CAP_FENCE_SIGNAL:
348 return 0;
349
350 case PIPE_CAP_VENDOR_ID:
351 return 0xFFFFFFFF;
352 case PIPE_CAP_DEVICE_ID:
353 return 0xFFFFFFFF;
354 case PIPE_CAP_ACCELERATED:
355 return 0;
356 case PIPE_CAP_VIDEO_MEMORY: {
357 /* XXX: Do we want to return the full amount of system memory ? */
358 uint64_t system_memory;
359
360 if (!os_get_total_physical_memory(&system_memory))
361 return 0;
362
363 return (int)(system_memory >> 20);
364 }
365 }
366
367 /* should only get here on unhandled cases */
368 debug_printf("Unexpected PIPE_CAP %d query\n", param);
369 return 0;
370 }
371
372 static int
373 swr_get_shader_param(struct pipe_screen *screen,
374 enum pipe_shader_type shader,
375 enum pipe_shader_cap param)
376 {
377 if (shader == PIPE_SHADER_VERTEX ||
378 shader == PIPE_SHADER_FRAGMENT ||
379 shader == PIPE_SHADER_GEOMETRY)
380 return gallivm_get_shader_param(param);
381
382 // Todo: tesselation, compute
383 return 0;
384 }
385
386
387 static float
388 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
389 {
390 switch (param) {
391 case PIPE_CAPF_MAX_LINE_WIDTH:
392 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
393 case PIPE_CAPF_MAX_POINT_WIDTH:
394 return 255.0; /* arbitrary */
395 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
396 return 0.0;
397 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
398 return 0.0;
399 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
400 return 16.0; /* arbitrary */
401 }
402 /* should only get here on unhandled cases */
403 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
404 return 0.0;
405 }
406
407 SWR_FORMAT
408 mesa_to_swr_format(enum pipe_format format)
409 {
410 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
411 /* depth / stencil */
412 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
413 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
414 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
415 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
416 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
417
418 /* alpha */
419 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
420 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
421 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
422 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
423
424 /* odd sizes, bgr */
425 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
426 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
427 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
428 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
429 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
430 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
431 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
432 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
433 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
434
435 /* rgb10a2 */
436 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
437 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
438 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
439 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
440 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
441
442 /* rgb10x2 */
443 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
444
445 /* bgr10a2 */
446 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
447 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
448 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
449 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
450 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
451
452 /* bgr10x2 */
453 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
454
455 /* r11g11b10 */
456 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
457
458 /* 32 bits per component */
459 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
460 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
461 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
462 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
463 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
464
465 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
466 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
467 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
468 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
469
470 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
471 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
472 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
473 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
474
475 {PIPE_FORMAT_R32_UINT, R32_UINT},
476 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
477 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
478 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
479
480 {PIPE_FORMAT_R32_SINT, R32_SINT},
481 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
482 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
483 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
484
485 /* 16 bits per component */
486 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
487 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
488 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
489 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
490 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
491
492 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
493 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
494 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
495 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
496
497 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
498 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
499 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
500 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
501
502 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
503 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
504 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
505 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
506
507 {PIPE_FORMAT_R16_UINT, R16_UINT},
508 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
509 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
510 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
511
512 {PIPE_FORMAT_R16_SINT, R16_SINT},
513 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
514 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
515 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
516
517 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
518 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
519 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
520 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
521 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
522
523 /* 8 bits per component */
524 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
525 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
526 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
527 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
528 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
529 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
530 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
531 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
532
533 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
534 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
535 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
536 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
537
538 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
539 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
540 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
541 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
542
543 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
544 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
545 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
546 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
547
548 {PIPE_FORMAT_R8_UINT, R8_UINT},
549 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
550 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
551 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
552
553 {PIPE_FORMAT_R8_SINT, R8_SINT},
554 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
555 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
556 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
557
558 /* These formats are valid for vertex data, but should not be used
559 * for render targets.
560 */
561
562 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
563 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
564 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
565 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
566
567 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
568 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
569 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
570 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
571
572 /* These formats have entries in SWR but don't have Load/StoreTile
573 * implementations. That means these aren't renderable, and thus having
574 * a mapping entry here is detrimental.
575 */
576 /*
577
578 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
579 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
580 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
581 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
582 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
583
584 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
585 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
586
587 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
588 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
589 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
590
591 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
592 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
593 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
594
595 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
596 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
597 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
598 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
599
600 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
601 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
602 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
603 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
604 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
605 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
606 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
607 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
608
609 {PIPE_FORMAT_I8_UINT, I8_UINT},
610 {PIPE_FORMAT_L8_UINT, L8_UINT},
611 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
612
613 {PIPE_FORMAT_I8_SINT, I8_SINT},
614 {PIPE_FORMAT_L8_SINT, L8_SINT},
615 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
616
617 */
618 };
619
620 auto it = mesa2swr.find(format);
621 if (it == mesa2swr.end())
622 return (SWR_FORMAT)-1;
623 else
624 return it->second;
625 }
626
627 static boolean
628 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
629 {
630 struct sw_winsys *winsys = screen->winsys;
631 struct sw_displaytarget *dt;
632
633 const unsigned width = align(res->swr.width, res->swr.halign);
634 const unsigned height = align(res->swr.height, res->swr.valign);
635
636 UINT stride;
637 dt = winsys->displaytarget_create(winsys,
638 res->base.bind,
639 res->base.format,
640 width, height,
641 64, NULL,
642 &stride);
643
644 if (dt == NULL)
645 return FALSE;
646
647 void *map = winsys->displaytarget_map(winsys, dt, 0);
648
649 res->display_target = dt;
650 res->swr.xpBaseAddress = (gfxptr_t)map;
651
652 /* Clear the display target surface */
653 if (map)
654 memset(map, 0, height * stride);
655
656 winsys->displaytarget_unmap(winsys, dt);
657
658 return TRUE;
659 }
660
661 static bool
662 swr_texture_layout(struct swr_screen *screen,
663 struct swr_resource *res,
664 boolean allocate)
665 {
666 struct pipe_resource *pt = &res->base;
667
668 pipe_format fmt = pt->format;
669 const struct util_format_description *desc = util_format_description(fmt);
670
671 res->has_depth = util_format_has_depth(desc);
672 res->has_stencil = util_format_has_stencil(desc);
673
674 if (res->has_stencil && !res->has_depth)
675 fmt = PIPE_FORMAT_R8_UINT;
676
677 /* We always use the SWR layout. For 2D and 3D textures this looks like:
678 *
679 * |<------- pitch ------->|
680 * +=======================+-------
681 * |Array 0 | ^
682 * | | |
683 * | Level 0 | |
684 * | | |
685 * | | qpitch
686 * +-----------+-----------+ |
687 * | | L2L2L2L2 | |
688 * | Level 1 | L3L3 | |
689 * | | L4 | v
690 * +===========+===========+-------
691 * |Array 1 |
692 * | |
693 * | Level 0 |
694 * | |
695 * | |
696 * +-----------+-----------+
697 * | | L2L2L2L2 |
698 * | Level 1 | L3L3 |
699 * | | L4 |
700 * +===========+===========+
701 *
702 * The overall width in bytes is known as the pitch, while the overall
703 * height in rows is the qpitch. Array slices are laid out logically below
704 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
705 * just invalid for the higher array numbers (since depth is also
706 * minified). 1D and 1D array surfaces are stored effectively the same way,
707 * except that pitch never plays into it. All the levels are logically
708 * adjacent to each other on the X axis. The qpitch becomes the number of
709 * elements between array slices, while the pitch is unused.
710 *
711 * Each level's sizes are subject to the valign and halign settings of the
712 * surface. For compressed formats that swr is unaware of, we will use an
713 * appropriately-sized uncompressed format, and scale the widths/heights.
714 *
715 * This surface is stored inside res->swr. For depth/stencil textures,
716 * res->secondary will have an identically-laid-out but R8_UINT-formatted
717 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
718 * texels, to simplify map/unmap logic which copies the stencil values
719 * in/out.
720 */
721
722 res->swr.width = pt->width0;
723 res->swr.height = pt->height0;
724 res->swr.type = swr_convert_target_type(pt->target);
725 res->swr.tileMode = SWR_TILE_NONE;
726 res->swr.format = mesa_to_swr_format(fmt);
727 res->swr.numSamples = std::max(1u, pt->nr_samples);
728
729 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
730 res->swr.halign = KNOB_MACROTILE_X_DIM;
731 res->swr.valign = KNOB_MACROTILE_Y_DIM;
732
733 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
734 * surface sample count. */
735 if (screen->msaa_force_enable) {
736 res->swr.numSamples = screen->msaa_max_count;
737 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
738 res->swr.numSamples);
739 }
740 } else {
741 res->swr.halign = 1;
742 res->swr.valign = 1;
743 }
744
745 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
746 unsigned width = align(pt->width0, halign);
747 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
748 for (int level = 1; level <= pt->last_level; level++)
749 width += align(u_minify(pt->width0, level), halign);
750 res->swr.pitch = util_format_get_blocksize(fmt);
751 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
752 } else {
753 // The pitch is the overall width of the texture in bytes. Most of the
754 // time this is the pitch of level 0 since all the other levels fit
755 // underneath it. However in some degenerate situations, the width of
756 // level1 + level2 may be larger. In that case, we use those
757 // widths. This can happen if, e.g. halign is 32, and the width of level
758 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
759 // be 32 each, adding up to 64.
760 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
761 if (pt->last_level > 1) {
762 width = std::max<uint32_t>(
763 width,
764 align(u_minify(pt->width0, 1), halign) +
765 align(u_minify(pt->width0, 2), halign));
766 }
767 res->swr.pitch = util_format_get_stride(fmt, width);
768
769 // The qpitch is controlled by either the height of the second LOD, or
770 // the combination of all the later LODs.
771 unsigned height = align(pt->height0, valign);
772 if (pt->last_level == 1) {
773 height += align(u_minify(pt->height0, 1), valign);
774 } else if (pt->last_level > 1) {
775 unsigned level1 = align(u_minify(pt->height0, 1), valign);
776 unsigned level2 = 0;
777 for (int level = 2; level <= pt->last_level; level++) {
778 level2 += align(u_minify(pt->height0, level), valign);
779 }
780 height += std::max(level1, level2);
781 }
782 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
783 }
784
785 if (pt->target == PIPE_TEXTURE_3D)
786 res->swr.depth = pt->depth0;
787 else
788 res->swr.depth = pt->array_size;
789
790 // Fix up swr format if necessary so that LOD offset computation works
791 if (res->swr.format == (SWR_FORMAT)-1) {
792 switch (util_format_get_blocksize(fmt)) {
793 default:
794 unreachable("Unexpected format block size");
795 case 1: res->swr.format = R8_UINT; break;
796 case 2: res->swr.format = R16_UINT; break;
797 case 4: res->swr.format = R32_UINT; break;
798 case 8:
799 if (util_format_is_compressed(fmt))
800 res->swr.format = BC4_UNORM;
801 else
802 res->swr.format = R32G32_UINT;
803 break;
804 case 16:
805 if (util_format_is_compressed(fmt))
806 res->swr.format = BC5_UNORM;
807 else
808 res->swr.format = R32G32B32A32_UINT;
809 break;
810 }
811 }
812
813 for (int level = 0; level <= pt->last_level; level++) {
814 res->mip_offsets[level] =
815 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
816 }
817
818 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
819 res->swr.pitch * res->swr.numSamples;
820 if (total_size > SWR_MAX_TEXTURE_SIZE)
821 return false;
822
823 if (allocate) {
824 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
825 if (!res->swr.xpBaseAddress)
826 return false;
827
828 if (res->has_depth && res->has_stencil) {
829 res->secondary = res->swr;
830 res->secondary.format = R8_UINT;
831 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
832
833 for (int level = 0; level <= pt->last_level; level++) {
834 res->secondary_mip_offsets[level] =
835 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
836 }
837
838 total_size = res->secondary.depth * res->secondary.qpitch *
839 res->secondary.pitch * res->secondary.numSamples;
840
841 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
842 if (!res->secondary.xpBaseAddress) {
843 AlignedFree((void *)res->swr.xpBaseAddress);
844 return false;
845 }
846 }
847 }
848
849 return true;
850 }
851
852 static boolean
853 swr_can_create_resource(struct pipe_screen *screen,
854 const struct pipe_resource *templat)
855 {
856 struct swr_resource res;
857 memset(&res, 0, sizeof(res));
858 res.base = *templat;
859 return swr_texture_layout(swr_screen(screen), &res, false);
860 }
861
862 /* Helper function that conditionally creates a single-sample resolve resource
863 * and attaches it to main multisample resource. */
864 static boolean
865 swr_create_resolve_resource(struct pipe_screen *_screen,
866 struct swr_resource *msaa_res)
867 {
868 struct swr_screen *screen = swr_screen(_screen);
869
870 /* If resource is multisample, create a single-sample resolve resource */
871 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
872 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
873
874 /* Create a single-sample copy of the resource. Copy the original
875 * resource parameters and set flag to prevent recursion when re-calling
876 * resource_create */
877 struct pipe_resource alt_template = msaa_res->base;
878 alt_template.nr_samples = 0;
879 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
880
881 /* Note: Display_target is a special single-sample resource, only the
882 * display_target has been created already. */
883 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
884 | PIPE_BIND_SHARED)) {
885 /* Allocate the multisample buffers. */
886 if (!swr_texture_layout(screen, msaa_res, true))
887 return false;
888
889 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
890 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
891 alt_template.bind = PIPE_BIND_RENDER_TARGET;
892 }
893
894 /* Allocate single-sample resolve surface */
895 struct pipe_resource *alt;
896 alt = _screen->resource_create(_screen, &alt_template);
897 if (!alt)
898 return false;
899
900 /* Attach it to the multisample resource */
901 msaa_res->resolve_target = alt;
902
903 /* Hang resolve surface state off the multisample surface state to so
904 * StoreTiles knows where to resolve the surface. */
905 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
906 }
907
908 return true; /* success */
909 }
910
911 static struct pipe_resource *
912 swr_resource_create(struct pipe_screen *_screen,
913 const struct pipe_resource *templat)
914 {
915 struct swr_screen *screen = swr_screen(_screen);
916 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
917 if (!res)
918 return NULL;
919
920 res->base = *templat;
921 pipe_reference_init(&res->base.reference, 1);
922 res->base.screen = &screen->base;
923
924 if (swr_resource_is_texture(&res->base)) {
925 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
926 | PIPE_BIND_SHARED)) {
927 /* displayable surface
928 * first call swr_texture_layout without allocating to finish
929 * filling out the SWR_SURFACE_STATE in res */
930 swr_texture_layout(screen, res, false);
931 if (!swr_displaytarget_layout(screen, res))
932 goto fail;
933 } else {
934 /* texture map */
935 if (!swr_texture_layout(screen, res, true))
936 goto fail;
937 }
938
939 /* If resource was multisample, create resolve resource and attach
940 * it to multisample resource. */
941 if (!swr_create_resolve_resource(_screen, res))
942 goto fail;
943
944 } else {
945 /* other data (vertex buffer, const buffer, etc) */
946 assert(util_format_get_blocksize(templat->format) == 1);
947 assert(templat->height0 == 1);
948 assert(templat->depth0 == 1);
949 assert(templat->last_level == 0);
950
951 /* Easiest to just call swr_texture_layout, as it sets up
952 * SWR_SURFACE_STATE in res */
953 if (!swr_texture_layout(screen, res, true))
954 goto fail;
955 }
956
957 return &res->base;
958
959 fail:
960 FREE(res);
961 return NULL;
962 }
963
964 static void
965 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
966 {
967 struct swr_screen *screen = swr_screen(p_screen);
968 struct swr_resource *spr = swr_resource(pt);
969
970 if (spr->display_target) {
971 /* If resource is display target, winsys manages the buffer and will
972 * free it on displaytarget_destroy. */
973 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
974
975 struct sw_winsys *winsys = screen->winsys;
976 winsys->displaytarget_destroy(winsys, spr->display_target);
977
978 if (spr->swr.numSamples > 1) {
979 /* Free an attached resolve resource */
980 struct swr_resource *alt = swr_resource(spr->resolve_target);
981 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
982
983 /* Free multisample buffer */
984 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
985 }
986 } else {
987 /* For regular resources, defer deletion */
988 swr_resource_unused(pt);
989
990 if (spr->swr.numSamples > 1) {
991 /* Free an attached resolve resource */
992 struct swr_resource *alt = swr_resource(spr->resolve_target);
993 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
994 }
995
996 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
997 swr_fence_work_free(screen->flush_fence,
998 (void*)(spr->secondary.xpBaseAddress), true);
999
1000 /* If work queue grows too large, submit a fence to force queue to
1001 * drain. This is mainly to decrease the amount of memory used by the
1002 * piglit streaming-texture-leak test */
1003 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1004 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1005 }
1006
1007 FREE(spr);
1008 }
1009
1010
1011 static void
1012 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1013 struct pipe_resource *resource,
1014 unsigned level,
1015 unsigned layer,
1016 void *context_private,
1017 struct pipe_box *sub_box)
1018 {
1019 struct swr_screen *screen = swr_screen(p_screen);
1020 struct sw_winsys *winsys = screen->winsys;
1021 struct swr_resource *spr = swr_resource(resource);
1022 struct pipe_context *pipe = screen->pipe;
1023 struct swr_context *ctx = swr_context(pipe);
1024
1025 if (pipe) {
1026 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1027 swr_resource_unused(resource);
1028 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1029 }
1030
1031 /* Multisample resolved into resolve_target at flush with store_resource */
1032 if (pipe && spr->swr.numSamples > 1) {
1033 struct pipe_resource *resolve_target = spr->resolve_target;
1034
1035 /* Once resolved, copy into display target */
1036 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1037
1038 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1039 PIPE_TRANSFER_WRITE);
1040 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1041 winsys->displaytarget_unmap(winsys, spr->display_target);
1042 }
1043
1044 debug_assert(spr->display_target);
1045 if (spr->display_target)
1046 winsys->displaytarget_display(
1047 winsys, spr->display_target, context_private, sub_box);
1048 }
1049
1050
1051 void
1052 swr_destroy_screen_internal(struct swr_screen **screen)
1053 {
1054 struct pipe_screen *p_screen = &(*screen)->base;
1055
1056 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1057 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1058
1059 JitDestroyContext((*screen)->hJitMgr);
1060
1061 if ((*screen)->pLibrary)
1062 util_dl_close((*screen)->pLibrary);
1063
1064 FREE(*screen);
1065 *screen = NULL;
1066 }
1067
1068
1069 static void
1070 swr_destroy_screen(struct pipe_screen *p_screen)
1071 {
1072 struct swr_screen *screen = swr_screen(p_screen);
1073 struct sw_winsys *winsys = screen->winsys;
1074
1075 fprintf(stderr, "SWR destroy screen!\n");
1076
1077 if (winsys->destroy)
1078 winsys->destroy(winsys);
1079
1080 swr_destroy_screen_internal(&screen);
1081 }
1082
1083
1084 static void
1085 swr_validate_env_options(struct swr_screen *screen)
1086 {
1087 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1088 * copied to scratch space on a draw. Past this, the draw will access
1089 * user-buffer directly and then block. This is faster than queuing many
1090 * large client draws. */
1091 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1092 int client_copy_limit =
1093 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1094 if (client_copy_limit > 0)
1095 screen->client_copy_limit = client_copy_limit;
1096
1097 /* XXX msaa under development, disable by default for now */
1098 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1099
1100 /* validate env override values, within range and power of 2 */
1101 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1102 if (msaa_max_count != 1) {
1103 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1104 || !util_is_power_of_two(msaa_max_count)) {
1105 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1106 fprintf(stderr, "must be power of 2 between 1 and %d" \
1107 " (or 1 to disable msaa)\n",
1108 SWR_MAX_NUM_MULTISAMPLES);
1109 msaa_max_count = 1;
1110 }
1111
1112 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1113 if (msaa_max_count == 1)
1114 fprintf(stderr, "(msaa disabled)\n");
1115
1116 screen->msaa_max_count = msaa_max_count;
1117 }
1118
1119 screen->msaa_force_enable = debug_get_bool_option(
1120 "SWR_MSAA_FORCE_ENABLE", false);
1121 if (screen->msaa_force_enable)
1122 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1123 }
1124
1125
1126 PUBLIC
1127 struct pipe_screen *
1128 swr_create_screen_internal(struct sw_winsys *winsys)
1129 {
1130 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1131 memset(screen, 0, sizeof(struct swr_screen));
1132
1133 if (!screen)
1134 return NULL;
1135
1136 if (!lp_build_init()) {
1137 FREE(screen);
1138 return NULL;
1139 }
1140
1141 screen->winsys = winsys;
1142 screen->base.get_name = swr_get_name;
1143 screen->base.get_vendor = swr_get_vendor;
1144 screen->base.is_format_supported = swr_is_format_supported;
1145 screen->base.context_create = swr_create_context;
1146 screen->base.can_create_resource = swr_can_create_resource;
1147
1148 screen->base.destroy = swr_destroy_screen;
1149 screen->base.get_param = swr_get_param;
1150 screen->base.get_shader_param = swr_get_shader_param;
1151 screen->base.get_paramf = swr_get_paramf;
1152
1153 screen->base.resource_create = swr_resource_create;
1154 screen->base.resource_destroy = swr_resource_destroy;
1155
1156 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1157
1158 // Pass in "" for architecture for run-time determination
1159 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1160
1161 swr_fence_init(&screen->base);
1162
1163 swr_validate_env_options(screen);
1164
1165 return &screen->base;
1166 }
1167