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gallium: Split out PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE.
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned storage_sample_count,
89 unsigned bind)
90 {
91 struct swr_screen *screen = swr_screen(_screen);
92 struct sw_winsys *winsys = screen->winsys;
93 const struct util_format_description *format_desc;
94
95 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
96 || target == PIPE_TEXTURE_1D_ARRAY
97 || target == PIPE_TEXTURE_2D
98 || target == PIPE_TEXTURE_2D_ARRAY
99 || target == PIPE_TEXTURE_RECT
100 || target == PIPE_TEXTURE_3D
101 || target == PIPE_TEXTURE_CUBE
102 || target == PIPE_TEXTURE_CUBE_ARRAY);
103
104 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
105 return false;
106
107 format_desc = util_format_description(format);
108 if (!format_desc)
109 return FALSE;
110
111 if ((sample_count > screen->msaa_max_count)
112 || !util_is_power_of_two_or_zero(sample_count))
113 return FALSE;
114
115 if (bind & PIPE_BIND_DISPLAY_TARGET) {
116 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
117 return FALSE;
118 }
119
120 if (bind & PIPE_BIND_RENDER_TARGET) {
121 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
122 return FALSE;
123
124 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
125 return FALSE;
126
127 /*
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside the state trackers.
131 */
132 if (format_desc->block.width != 1 || format_desc->block.height != 1)
133 return FALSE;
134 }
135
136 if (bind & PIPE_BIND_DEPTH_STENCIL) {
137 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
138 return FALSE;
139
140 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
141 return FALSE;
142 }
143
144 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
145 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
146 return FALSE;
147 }
148
149 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
150 format != PIPE_FORMAT_ETC1_RGB8) {
151 return FALSE;
152 }
153
154 return TRUE;
155 }
156
157 static int
158 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
159 {
160 switch (param) {
161 /* limits */
162 case PIPE_CAP_MAX_RENDER_TARGETS:
163 return PIPE_MAX_COLOR_BUFS;
164 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
165 return SWR_MAX_TEXTURE_2D_LEVELS;
166 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
167 return SWR_MAX_TEXTURE_3D_LEVELS;
168 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
169 return SWR_MAX_TEXTURE_CUBE_LEVELS;
170 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
171 return MAX_SO_STREAMS;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
173 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
174 return MAX_ATTRIBUTES * 4;
175 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
176 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
177 return 1024;
178 case PIPE_CAP_MAX_VERTEX_STREAMS:
179 return 1;
180 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
181 return 2048;
182 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
183 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
184 case PIPE_CAP_MIN_TEXEL_OFFSET:
185 return -8;
186 case PIPE_CAP_MAX_TEXEL_OFFSET:
187 return 7;
188 case PIPE_CAP_GLSL_FEATURE_LEVEL:
189 return 330;
190 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
191 return 140;
192 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
193 return 16;
194 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
195 return 64;
196 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
197 return 65536;
198 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
199 return 0;
200 case PIPE_CAP_MAX_VIEWPORTS:
201 return 1;
202 case PIPE_CAP_ENDIANNESS:
203 return PIPE_ENDIAN_NATIVE;
204 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
205 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
206 return 0;
207
208 /* supported features */
209 case PIPE_CAP_NPOT_TEXTURES:
210 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
211 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
212 case PIPE_CAP_SM3:
213 case PIPE_CAP_POINT_SPRITE:
214 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
215 case PIPE_CAP_OCCLUSION_QUERY:
216 case PIPE_CAP_QUERY_TIME_ELAPSED:
217 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
218 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
219 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
220 case PIPE_CAP_TEXTURE_SWIZZLE:
221 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
222 case PIPE_CAP_INDEP_BLEND_ENABLE:
223 case PIPE_CAP_INDEP_BLEND_FUNC:
224 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
225 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
226 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
227 case PIPE_CAP_DEPTH_CLIP_DISABLE:
228 case PIPE_CAP_PRIMITIVE_RESTART:
229 case PIPE_CAP_TGSI_INSTANCEID:
230 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
231 case PIPE_CAP_START_INSTANCE:
232 case PIPE_CAP_SEAMLESS_CUBE_MAP:
233 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
234 case PIPE_CAP_CONDITIONAL_RENDER:
235 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
236 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
237 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
238 case PIPE_CAP_USER_VERTEX_BUFFERS:
239 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
240 case PIPE_CAP_QUERY_TIMESTAMP:
241 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
242 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
243 case PIPE_CAP_DRAW_INDIRECT:
244 case PIPE_CAP_UMA:
245 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
246 case PIPE_CAP_CLIP_HALFZ:
247 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
248 case PIPE_CAP_DEPTH_BOUNDS_TEST:
249 case PIPE_CAP_CLEAR_TEXTURE:
250 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
251 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
252 case PIPE_CAP_CULL_DISTANCE:
253 case PIPE_CAP_CUBE_MAP_ARRAY:
254 case PIPE_CAP_DOUBLES:
255 return 1;
256
257 /* MSAA support
258 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
259 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
260 case PIPE_CAP_TEXTURE_MULTISAMPLE:
261 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
262 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
263 case PIPE_CAP_FAKE_SW_MSAA:
264 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
265
266 /* fetch jit change for 2-4GB buffers requires alignment */
267 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
268 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
269 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
270 return 1;
271
272 /* unsupported features */
273 case PIPE_CAP_ANISOTROPIC_FILTER:
274 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
275 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
276 case PIPE_CAP_SHADER_STENCIL_EXPORT:
277 case PIPE_CAP_TEXTURE_BARRIER:
278 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
279 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
280 case PIPE_CAP_COMPUTE:
281 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
282 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
283 case PIPE_CAP_TGSI_TEXCOORD:
284 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
285 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
286 case PIPE_CAP_TEXTURE_GATHER_SM5:
287 case PIPE_CAP_TEXTURE_QUERY_LOD:
288 case PIPE_CAP_SAMPLE_SHADING:
289 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
290 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
291 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
292 case PIPE_CAP_SAMPLER_VIEW_TARGET:
293 case PIPE_CAP_VERTEXID_NOBASE:
294 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
295 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
296 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
297 case PIPE_CAP_TGSI_TXQS:
298 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
299 case PIPE_CAP_SHAREABLE_SHADERS:
300 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
301 case PIPE_CAP_DRAW_PARAMETERS:
302 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
303 case PIPE_CAP_MULTI_DRAW_INDIRECT:
304 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
305 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
306 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
307 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
308 case PIPE_CAP_INVALIDATE_BUFFER:
309 case PIPE_CAP_GENERATE_MIPMAP:
310 case PIPE_CAP_STRING_MARKER:
311 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
312 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
313 case PIPE_CAP_QUERY_BUFFER_OBJECT:
314 case PIPE_CAP_QUERY_MEMORY_INFO:
315 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
316 case PIPE_CAP_PCI_GROUP:
317 case PIPE_CAP_PCI_BUS:
318 case PIPE_CAP_PCI_DEVICE:
319 case PIPE_CAP_PCI_FUNCTION:
320 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
321 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
322 case PIPE_CAP_TGSI_VOTE:
323 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
324 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
325 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
326 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
327 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
328 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
329 case PIPE_CAP_NATIVE_FENCE_FD:
330 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
331 case PIPE_CAP_TGSI_FS_FBFETCH:
332 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
333 case PIPE_CAP_INT64:
334 case PIPE_CAP_INT64_DIVMOD:
335 case PIPE_CAP_TGSI_TEX_TXF_LZ:
336 case PIPE_CAP_TGSI_CLOCK:
337 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
338 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
339 case PIPE_CAP_TGSI_BALLOT:
340 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
341 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
342 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
343 case PIPE_CAP_POST_DEPTH_COVERAGE:
344 case PIPE_CAP_BINDLESS_TEXTURE:
345 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
346 case PIPE_CAP_QUERY_SO_OVERFLOW:
347 case PIPE_CAP_MEMOBJ:
348 case PIPE_CAP_LOAD_CONSTBUF:
349 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
350 case PIPE_CAP_TILE_RASTER_ORDER:
351 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
352 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
353 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
354 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
355 case PIPE_CAP_FENCE_SIGNAL:
356 case PIPE_CAP_CONSTBUF0_FLAGS:
357 case PIPE_CAP_PACKED_UNIFORMS:
358 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
359 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
360 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
361 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
362 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
363 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
364 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
365 return 0;
366 case PIPE_CAP_MAX_GS_INVOCATIONS:
367 return 32;
368 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
369 return 1 << 27;
370
371 case PIPE_CAP_VENDOR_ID:
372 return 0xFFFFFFFF;
373 case PIPE_CAP_DEVICE_ID:
374 return 0xFFFFFFFF;
375 case PIPE_CAP_ACCELERATED:
376 return 0;
377 case PIPE_CAP_VIDEO_MEMORY: {
378 /* XXX: Do we want to return the full amount of system memory ? */
379 uint64_t system_memory;
380
381 if (!os_get_total_physical_memory(&system_memory))
382 return 0;
383
384 return (int)(system_memory >> 20);
385 }
386 }
387
388 /* should only get here on unhandled cases */
389 debug_printf("Unexpected PIPE_CAP %d query\n", param);
390 return 0;
391 }
392
393 static int
394 swr_get_shader_param(struct pipe_screen *screen,
395 enum pipe_shader_type shader,
396 enum pipe_shader_cap param)
397 {
398 if (shader == PIPE_SHADER_VERTEX ||
399 shader == PIPE_SHADER_FRAGMENT ||
400 shader == PIPE_SHADER_GEOMETRY)
401 return gallivm_get_shader_param(param);
402
403 // Todo: tesselation, compute
404 return 0;
405 }
406
407
408 static float
409 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
410 {
411 switch (param) {
412 case PIPE_CAPF_MAX_LINE_WIDTH:
413 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
414 case PIPE_CAPF_MAX_POINT_WIDTH:
415 return 255.0; /* arbitrary */
416 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
417 return 0.0;
418 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
419 return 0.0;
420 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
421 return 16.0; /* arbitrary */
422 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
423 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
424 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
425 return 0.0f;
426 }
427 /* should only get here on unhandled cases */
428 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
429 return 0.0;
430 }
431
432 SWR_FORMAT
433 mesa_to_swr_format(enum pipe_format format)
434 {
435 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
436 /* depth / stencil */
437 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
438 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
439 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
440 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
441 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
442
443 /* alpha */
444 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
445 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
446 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
447 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
448
449 /* odd sizes, bgr */
450 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
451 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
452 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
453 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
454 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
455 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
456 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
457 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
458 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
459
460 /* rgb10a2 */
461 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
462 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
463 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
464 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
465 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
466
467 /* rgb10x2 */
468 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
469
470 /* bgr10a2 */
471 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
472 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
473 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
474 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
475 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
476
477 /* bgr10x2 */
478 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
479
480 /* r11g11b10 */
481 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
482
483 /* 32 bits per component */
484 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
485 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
486 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
487 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
488 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
489
490 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
491 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
492 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
493 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
494
495 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
496 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
497 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
498 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
499
500 {PIPE_FORMAT_R32_UINT, R32_UINT},
501 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
502 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
503 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
504
505 {PIPE_FORMAT_R32_SINT, R32_SINT},
506 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
507 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
508 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
509
510 /* 16 bits per component */
511 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
512 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
513 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
514 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
515 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
516
517 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
518 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
519 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
520 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
521
522 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
523 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
524 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
525 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
526
527 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
528 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
529 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
530 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
531
532 {PIPE_FORMAT_R16_UINT, R16_UINT},
533 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
534 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
535 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
536
537 {PIPE_FORMAT_R16_SINT, R16_SINT},
538 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
539 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
540 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
541
542 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
543 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
544 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
545 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
546 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
547
548 /* 8 bits per component */
549 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
550 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
551 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
552 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
553 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
554 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
555 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
556 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
557
558 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
559 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
560 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
561 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
562
563 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
564 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
565 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
566 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
567
568 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
569 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
570 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
571 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
572
573 {PIPE_FORMAT_R8_UINT, R8_UINT},
574 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
575 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
576 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
577
578 {PIPE_FORMAT_R8_SINT, R8_SINT},
579 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
580 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
581 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
582
583 /* These formats are valid for vertex data, but should not be used
584 * for render targets.
585 */
586
587 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
588 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
589 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
590 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
591
592 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
593 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
594 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
595 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
596
597 /* These formats have entries in SWR but don't have Load/StoreTile
598 * implementations. That means these aren't renderable, and thus having
599 * a mapping entry here is detrimental.
600 */
601 /*
602
603 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
604 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
605 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
606 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
607 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
608
609 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
610 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
611
612 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
613 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
614 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
615
616 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
617 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
618 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
619
620 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
621 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
622 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
623 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
624
625 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
626 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
627 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
628 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
629 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
630 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
631 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
632 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
633
634 {PIPE_FORMAT_I8_UINT, I8_UINT},
635 {PIPE_FORMAT_L8_UINT, L8_UINT},
636 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
637
638 {PIPE_FORMAT_I8_SINT, I8_SINT},
639 {PIPE_FORMAT_L8_SINT, L8_SINT},
640 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
641
642 */
643 };
644
645 auto it = mesa2swr.find(format);
646 if (it == mesa2swr.end())
647 return (SWR_FORMAT)-1;
648 else
649 return it->second;
650 }
651
652 static boolean
653 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
654 {
655 struct sw_winsys *winsys = screen->winsys;
656 struct sw_displaytarget *dt;
657
658 const unsigned width = align(res->swr.width, res->swr.halign);
659 const unsigned height = align(res->swr.height, res->swr.valign);
660
661 UINT stride;
662 dt = winsys->displaytarget_create(winsys,
663 res->base.bind,
664 res->base.format,
665 width, height,
666 64, NULL,
667 &stride);
668
669 if (dt == NULL)
670 return FALSE;
671
672 void *map = winsys->displaytarget_map(winsys, dt, 0);
673
674 res->display_target = dt;
675 res->swr.xpBaseAddress = (gfxptr_t)map;
676
677 /* Clear the display target surface */
678 if (map)
679 memset(map, 0, height * stride);
680
681 winsys->displaytarget_unmap(winsys, dt);
682
683 return TRUE;
684 }
685
686 static bool
687 swr_texture_layout(struct swr_screen *screen,
688 struct swr_resource *res,
689 boolean allocate)
690 {
691 struct pipe_resource *pt = &res->base;
692
693 pipe_format fmt = pt->format;
694 const struct util_format_description *desc = util_format_description(fmt);
695
696 res->has_depth = util_format_has_depth(desc);
697 res->has_stencil = util_format_has_stencil(desc);
698
699 if (res->has_stencil && !res->has_depth)
700 fmt = PIPE_FORMAT_R8_UINT;
701
702 /* We always use the SWR layout. For 2D and 3D textures this looks like:
703 *
704 * |<------- pitch ------->|
705 * +=======================+-------
706 * |Array 0 | ^
707 * | | |
708 * | Level 0 | |
709 * | | |
710 * | | qpitch
711 * +-----------+-----------+ |
712 * | | L2L2L2L2 | |
713 * | Level 1 | L3L3 | |
714 * | | L4 | v
715 * +===========+===========+-------
716 * |Array 1 |
717 * | |
718 * | Level 0 |
719 * | |
720 * | |
721 * +-----------+-----------+
722 * | | L2L2L2L2 |
723 * | Level 1 | L3L3 |
724 * | | L4 |
725 * +===========+===========+
726 *
727 * The overall width in bytes is known as the pitch, while the overall
728 * height in rows is the qpitch. Array slices are laid out logically below
729 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
730 * just invalid for the higher array numbers (since depth is also
731 * minified). 1D and 1D array surfaces are stored effectively the same way,
732 * except that pitch never plays into it. All the levels are logically
733 * adjacent to each other on the X axis. The qpitch becomes the number of
734 * elements between array slices, while the pitch is unused.
735 *
736 * Each level's sizes are subject to the valign and halign settings of the
737 * surface. For compressed formats that swr is unaware of, we will use an
738 * appropriately-sized uncompressed format, and scale the widths/heights.
739 *
740 * This surface is stored inside res->swr. For depth/stencil textures,
741 * res->secondary will have an identically-laid-out but R8_UINT-formatted
742 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
743 * texels, to simplify map/unmap logic which copies the stencil values
744 * in/out.
745 */
746
747 res->swr.width = pt->width0;
748 res->swr.height = pt->height0;
749 res->swr.type = swr_convert_target_type(pt->target);
750 res->swr.tileMode = SWR_TILE_NONE;
751 res->swr.format = mesa_to_swr_format(fmt);
752 res->swr.numSamples = std::max(1u, pt->nr_samples);
753
754 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
755 res->swr.halign = KNOB_MACROTILE_X_DIM;
756 res->swr.valign = KNOB_MACROTILE_Y_DIM;
757
758 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
759 * surface sample count. */
760 if (screen->msaa_force_enable) {
761 res->swr.numSamples = screen->msaa_max_count;
762 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
763 res->swr.numSamples);
764 }
765 } else {
766 res->swr.halign = 1;
767 res->swr.valign = 1;
768 }
769
770 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
771 unsigned width = align(pt->width0, halign);
772 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
773 for (int level = 1; level <= pt->last_level; level++)
774 width += align(u_minify(pt->width0, level), halign);
775 res->swr.pitch = util_format_get_blocksize(fmt);
776 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
777 } else {
778 // The pitch is the overall width of the texture in bytes. Most of the
779 // time this is the pitch of level 0 since all the other levels fit
780 // underneath it. However in some degenerate situations, the width of
781 // level1 + level2 may be larger. In that case, we use those
782 // widths. This can happen if, e.g. halign is 32, and the width of level
783 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
784 // be 32 each, adding up to 64.
785 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
786 if (pt->last_level > 1) {
787 width = std::max<uint32_t>(
788 width,
789 align(u_minify(pt->width0, 1), halign) +
790 align(u_minify(pt->width0, 2), halign));
791 }
792 res->swr.pitch = util_format_get_stride(fmt, width);
793
794 // The qpitch is controlled by either the height of the second LOD, or
795 // the combination of all the later LODs.
796 unsigned height = align(pt->height0, valign);
797 if (pt->last_level == 1) {
798 height += align(u_minify(pt->height0, 1), valign);
799 } else if (pt->last_level > 1) {
800 unsigned level1 = align(u_minify(pt->height0, 1), valign);
801 unsigned level2 = 0;
802 for (int level = 2; level <= pt->last_level; level++) {
803 level2 += align(u_minify(pt->height0, level), valign);
804 }
805 height += std::max(level1, level2);
806 }
807 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
808 }
809
810 if (pt->target == PIPE_TEXTURE_3D)
811 res->swr.depth = pt->depth0;
812 else
813 res->swr.depth = pt->array_size;
814
815 // Fix up swr format if necessary so that LOD offset computation works
816 if (res->swr.format == (SWR_FORMAT)-1) {
817 switch (util_format_get_blocksize(fmt)) {
818 default:
819 unreachable("Unexpected format block size");
820 case 1: res->swr.format = R8_UINT; break;
821 case 2: res->swr.format = R16_UINT; break;
822 case 4: res->swr.format = R32_UINT; break;
823 case 8:
824 if (util_format_is_compressed(fmt))
825 res->swr.format = BC4_UNORM;
826 else
827 res->swr.format = R32G32_UINT;
828 break;
829 case 16:
830 if (util_format_is_compressed(fmt))
831 res->swr.format = BC5_UNORM;
832 else
833 res->swr.format = R32G32B32A32_UINT;
834 break;
835 }
836 }
837
838 for (int level = 0; level <= pt->last_level; level++) {
839 res->mip_offsets[level] =
840 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
841 }
842
843 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
844 res->swr.pitch * res->swr.numSamples;
845 if (total_size > SWR_MAX_TEXTURE_SIZE)
846 return false;
847
848 if (allocate) {
849 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
850 if (!res->swr.xpBaseAddress)
851 return false;
852
853 if (res->has_depth && res->has_stencil) {
854 res->secondary = res->swr;
855 res->secondary.format = R8_UINT;
856 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
857
858 for (int level = 0; level <= pt->last_level; level++) {
859 res->secondary_mip_offsets[level] =
860 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
861 }
862
863 total_size = res->secondary.depth * res->secondary.qpitch *
864 res->secondary.pitch * res->secondary.numSamples;
865
866 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
867 if (!res->secondary.xpBaseAddress) {
868 AlignedFree((void *)res->swr.xpBaseAddress);
869 return false;
870 }
871 }
872 }
873
874 return true;
875 }
876
877 static boolean
878 swr_can_create_resource(struct pipe_screen *screen,
879 const struct pipe_resource *templat)
880 {
881 struct swr_resource res;
882 memset(&res, 0, sizeof(res));
883 res.base = *templat;
884 return swr_texture_layout(swr_screen(screen), &res, false);
885 }
886
887 /* Helper function that conditionally creates a single-sample resolve resource
888 * and attaches it to main multisample resource. */
889 static boolean
890 swr_create_resolve_resource(struct pipe_screen *_screen,
891 struct swr_resource *msaa_res)
892 {
893 struct swr_screen *screen = swr_screen(_screen);
894
895 /* If resource is multisample, create a single-sample resolve resource */
896 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
897 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
898
899 /* Create a single-sample copy of the resource. Copy the original
900 * resource parameters and set flag to prevent recursion when re-calling
901 * resource_create */
902 struct pipe_resource alt_template = msaa_res->base;
903 alt_template.nr_samples = 0;
904 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
905
906 /* Note: Display_target is a special single-sample resource, only the
907 * display_target has been created already. */
908 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
909 | PIPE_BIND_SHARED)) {
910 /* Allocate the multisample buffers. */
911 if (!swr_texture_layout(screen, msaa_res, true))
912 return false;
913
914 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
915 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
916 alt_template.bind = PIPE_BIND_RENDER_TARGET;
917 }
918
919 /* Allocate single-sample resolve surface */
920 struct pipe_resource *alt;
921 alt = _screen->resource_create(_screen, &alt_template);
922 if (!alt)
923 return false;
924
925 /* Attach it to the multisample resource */
926 msaa_res->resolve_target = alt;
927
928 /* Hang resolve surface state off the multisample surface state to so
929 * StoreTiles knows where to resolve the surface. */
930 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
931 }
932
933 return true; /* success */
934 }
935
936 static struct pipe_resource *
937 swr_resource_create(struct pipe_screen *_screen,
938 const struct pipe_resource *templat)
939 {
940 struct swr_screen *screen = swr_screen(_screen);
941 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
942 if (!res)
943 return NULL;
944
945 res->base = *templat;
946 pipe_reference_init(&res->base.reference, 1);
947 res->base.screen = &screen->base;
948
949 if (swr_resource_is_texture(&res->base)) {
950 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
951 | PIPE_BIND_SHARED)) {
952 /* displayable surface
953 * first call swr_texture_layout without allocating to finish
954 * filling out the SWR_SURFACE_STATE in res */
955 swr_texture_layout(screen, res, false);
956 if (!swr_displaytarget_layout(screen, res))
957 goto fail;
958 } else {
959 /* texture map */
960 if (!swr_texture_layout(screen, res, true))
961 goto fail;
962 }
963
964 /* If resource was multisample, create resolve resource and attach
965 * it to multisample resource. */
966 if (!swr_create_resolve_resource(_screen, res))
967 goto fail;
968
969 } else {
970 /* other data (vertex buffer, const buffer, etc) */
971 assert(util_format_get_blocksize(templat->format) == 1);
972 assert(templat->height0 == 1);
973 assert(templat->depth0 == 1);
974 assert(templat->last_level == 0);
975
976 /* Easiest to just call swr_texture_layout, as it sets up
977 * SWR_SURFACE_STATE in res */
978 if (!swr_texture_layout(screen, res, true))
979 goto fail;
980 }
981
982 return &res->base;
983
984 fail:
985 FREE(res);
986 return NULL;
987 }
988
989 static void
990 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
991 {
992 struct swr_screen *screen = swr_screen(p_screen);
993 struct swr_resource *spr = swr_resource(pt);
994
995 if (spr->display_target) {
996 /* If resource is display target, winsys manages the buffer and will
997 * free it on displaytarget_destroy. */
998 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
999
1000 struct sw_winsys *winsys = screen->winsys;
1001 winsys->displaytarget_destroy(winsys, spr->display_target);
1002
1003 if (spr->swr.numSamples > 1) {
1004 /* Free an attached resolve resource */
1005 struct swr_resource *alt = swr_resource(spr->resolve_target);
1006 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1007
1008 /* Free multisample buffer */
1009 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1010 }
1011 } else {
1012 /* For regular resources, defer deletion */
1013 swr_resource_unused(pt);
1014
1015 if (spr->swr.numSamples > 1) {
1016 /* Free an attached resolve resource */
1017 struct swr_resource *alt = swr_resource(spr->resolve_target);
1018 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1019 }
1020
1021 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1022 swr_fence_work_free(screen->flush_fence,
1023 (void*)(spr->secondary.xpBaseAddress), true);
1024
1025 /* If work queue grows too large, submit a fence to force queue to
1026 * drain. This is mainly to decrease the amount of memory used by the
1027 * piglit streaming-texture-leak test */
1028 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1029 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1030 }
1031
1032 FREE(spr);
1033 }
1034
1035
1036 static void
1037 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1038 struct pipe_resource *resource,
1039 unsigned level,
1040 unsigned layer,
1041 void *context_private,
1042 struct pipe_box *sub_box)
1043 {
1044 struct swr_screen *screen = swr_screen(p_screen);
1045 struct sw_winsys *winsys = screen->winsys;
1046 struct swr_resource *spr = swr_resource(resource);
1047 struct pipe_context *pipe = screen->pipe;
1048 struct swr_context *ctx = swr_context(pipe);
1049
1050 if (pipe) {
1051 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1052 swr_resource_unused(resource);
1053 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1054 }
1055
1056 /* Multisample resolved into resolve_target at flush with store_resource */
1057 if (pipe && spr->swr.numSamples > 1) {
1058 struct pipe_resource *resolve_target = spr->resolve_target;
1059
1060 /* Once resolved, copy into display target */
1061 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1062
1063 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1064 PIPE_TRANSFER_WRITE);
1065 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1066 winsys->displaytarget_unmap(winsys, spr->display_target);
1067 }
1068
1069 debug_assert(spr->display_target);
1070 if (spr->display_target)
1071 winsys->displaytarget_display(
1072 winsys, spr->display_target, context_private, sub_box);
1073 }
1074
1075
1076 void
1077 swr_destroy_screen_internal(struct swr_screen **screen)
1078 {
1079 struct pipe_screen *p_screen = &(*screen)->base;
1080
1081 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1082 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1083
1084 JitDestroyContext((*screen)->hJitMgr);
1085
1086 if ((*screen)->pLibrary)
1087 util_dl_close((*screen)->pLibrary);
1088
1089 FREE(*screen);
1090 *screen = NULL;
1091 }
1092
1093
1094 static void
1095 swr_destroy_screen(struct pipe_screen *p_screen)
1096 {
1097 struct swr_screen *screen = swr_screen(p_screen);
1098 struct sw_winsys *winsys = screen->winsys;
1099
1100 fprintf(stderr, "SWR destroy screen!\n");
1101
1102 if (winsys->destroy)
1103 winsys->destroy(winsys);
1104
1105 swr_destroy_screen_internal(&screen);
1106 }
1107
1108
1109 static void
1110 swr_validate_env_options(struct swr_screen *screen)
1111 {
1112 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1113 * copied to scratch space on a draw. Past this, the draw will access
1114 * user-buffer directly and then block. This is faster than queuing many
1115 * large client draws. */
1116 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1117 int client_copy_limit =
1118 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1119 if (client_copy_limit > 0)
1120 screen->client_copy_limit = client_copy_limit;
1121
1122 /* XXX msaa under development, disable by default for now */
1123 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1124
1125 /* validate env override values, within range and power of 2 */
1126 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1127 if (msaa_max_count != 1) {
1128 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1129 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1130 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1131 fprintf(stderr, "must be power of 2 between 1 and %d" \
1132 " (or 1 to disable msaa)\n",
1133 SWR_MAX_NUM_MULTISAMPLES);
1134 msaa_max_count = 1;
1135 }
1136
1137 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1138 if (msaa_max_count == 1)
1139 fprintf(stderr, "(msaa disabled)\n");
1140
1141 screen->msaa_max_count = msaa_max_count;
1142 }
1143
1144 screen->msaa_force_enable = debug_get_bool_option(
1145 "SWR_MSAA_FORCE_ENABLE", false);
1146 if (screen->msaa_force_enable)
1147 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1148 }
1149
1150
1151 struct pipe_screen *
1152 swr_create_screen_internal(struct sw_winsys *winsys)
1153 {
1154 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1155
1156 if (!screen)
1157 return NULL;
1158
1159 if (!lp_build_init()) {
1160 FREE(screen);
1161 return NULL;
1162 }
1163
1164 screen->winsys = winsys;
1165 screen->base.get_name = swr_get_name;
1166 screen->base.get_vendor = swr_get_vendor;
1167 screen->base.is_format_supported = swr_is_format_supported;
1168 screen->base.context_create = swr_create_context;
1169 screen->base.can_create_resource = swr_can_create_resource;
1170
1171 screen->base.destroy = swr_destroy_screen;
1172 screen->base.get_param = swr_get_param;
1173 screen->base.get_shader_param = swr_get_shader_param;
1174 screen->base.get_paramf = swr_get_paramf;
1175
1176 screen->base.resource_create = swr_resource_create;
1177 screen->base.resource_destroy = swr_resource_destroy;
1178
1179 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1180
1181 // Pass in "" for architecture for run-time determination
1182 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1183
1184 swr_fence_init(&screen->base);
1185
1186 swr_validate_env_options(screen);
1187
1188 return &screen->base;
1189 }
1190