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gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /* MSVC case instensitive compare */
50 #if defined(PIPE_CC_MSVC)
51 #define strcasecmp lstrcmpiA
52 #endif
53
54 /*
55 * Max texture sizes
56 * XXX Check max texture size values against core and sampler.
57 */
58 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
59 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
60 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
61 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
62 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
63
64 /* Flag indicates creation of alternate surface, to prevent recursive loop
65 * in resource creation when msaa_force_enable is set. */
66 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
67
68
69 static const char *
70 swr_get_name(struct pipe_screen *screen)
71 {
72 static char buf[100];
73 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
74 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
75 lp_native_vector_width );
76 return buf;
77 }
78
79 static const char *
80 swr_get_vendor(struct pipe_screen *screen)
81 {
82 return "Intel Corporation";
83 }
84
85 static boolean
86 swr_is_format_supported(struct pipe_screen *_screen,
87 enum pipe_format format,
88 enum pipe_texture_target target,
89 unsigned sample_count,
90 unsigned bind)
91 {
92 struct swr_screen *screen = swr_screen(_screen);
93 struct sw_winsys *winsys = screen->winsys;
94 const struct util_format_description *format_desc;
95
96 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
97 || target == PIPE_TEXTURE_1D_ARRAY
98 || target == PIPE_TEXTURE_2D
99 || target == PIPE_TEXTURE_2D_ARRAY
100 || target == PIPE_TEXTURE_RECT
101 || target == PIPE_TEXTURE_3D
102 || target == PIPE_TEXTURE_CUBE
103 || target == PIPE_TEXTURE_CUBE_ARRAY);
104
105 format_desc = util_format_description(format);
106 if (!format_desc)
107 return FALSE;
108
109 if ((sample_count > screen->msaa_max_count)
110 || !util_is_power_of_two(sample_count))
111 return FALSE;
112
113 if (bind & PIPE_BIND_DISPLAY_TARGET) {
114 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
115 return FALSE;
116 }
117
118 if (bind & PIPE_BIND_RENDER_TARGET) {
119 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
120 return FALSE;
121
122 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
123 return FALSE;
124
125 /*
126 * Although possible, it is unnatural to render into compressed or YUV
127 * surfaces. So disable these here to avoid going into weird paths
128 * inside the state trackers.
129 */
130 if (format_desc->block.width != 1 || format_desc->block.height != 1)
131 return FALSE;
132 }
133
134 if (bind & PIPE_BIND_DEPTH_STENCIL) {
135 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
136 return FALSE;
137
138 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
139 return FALSE;
140 }
141
142 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
143 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
144 return FALSE;
145 }
146
147 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
148 format != PIPE_FORMAT_ETC1_RGB8) {
149 return FALSE;
150 }
151
152 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
153 return util_format_s3tc_enabled;
154 }
155
156 return TRUE;
157 }
158
159 static int
160 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
161 {
162 switch (param) {
163 /* limits */
164 case PIPE_CAP_MAX_RENDER_TARGETS:
165 return PIPE_MAX_COLOR_BUFS;
166 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
167 return SWR_MAX_TEXTURE_2D_LEVELS;
168 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
169 return SWR_MAX_TEXTURE_3D_LEVELS;
170 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
171 return SWR_MAX_TEXTURE_CUBE_LEVELS;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
173 return MAX_SO_STREAMS;
174 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
175 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
176 return MAX_ATTRIBUTES * 4;
177 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
178 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
179 return 1024;
180 case PIPE_CAP_MAX_VERTEX_STREAMS:
181 return 1;
182 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
183 return 2048;
184 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
185 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
186 case PIPE_CAP_MIN_TEXEL_OFFSET:
187 return -8;
188 case PIPE_CAP_MAX_TEXEL_OFFSET:
189 return 7;
190 case PIPE_CAP_GLSL_FEATURE_LEVEL:
191 return 330;
192 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
193 return 16;
194 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
195 return 64;
196 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
197 return 65536;
198 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
199 return 0;
200 case PIPE_CAP_MAX_VIEWPORTS:
201 return 1;
202 case PIPE_CAP_ENDIANNESS:
203 return PIPE_ENDIAN_NATIVE;
204 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
205 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
206 return 0;
207
208 /* supported features */
209 case PIPE_CAP_NPOT_TEXTURES:
210 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
211 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
212 case PIPE_CAP_TWO_SIDED_STENCIL:
213 case PIPE_CAP_SM3:
214 case PIPE_CAP_POINT_SPRITE:
215 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
216 case PIPE_CAP_OCCLUSION_QUERY:
217 case PIPE_CAP_QUERY_TIME_ELAPSED:
218 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
219 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
220 case PIPE_CAP_TEXTURE_SHADOW_MAP:
221 case PIPE_CAP_TEXTURE_SWIZZLE:
222 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
223 case PIPE_CAP_INDEP_BLEND_ENABLE:
224 case PIPE_CAP_INDEP_BLEND_FUNC:
225 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
226 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
227 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
228 case PIPE_CAP_DEPTH_CLIP_DISABLE:
229 case PIPE_CAP_PRIMITIVE_RESTART:
230 case PIPE_CAP_TGSI_INSTANCEID:
231 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
232 case PIPE_CAP_START_INSTANCE:
233 case PIPE_CAP_SEAMLESS_CUBE_MAP:
234 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
235 case PIPE_CAP_CONDITIONAL_RENDER:
236 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
237 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
238 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
239 case PIPE_CAP_USER_VERTEX_BUFFERS:
240 case PIPE_CAP_USER_CONSTANT_BUFFERS:
241 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
242 case PIPE_CAP_QUERY_TIMESTAMP:
243 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
244 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
245 case PIPE_CAP_DRAW_INDIRECT:
246 case PIPE_CAP_UMA:
247 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
248 case PIPE_CAP_CLIP_HALFZ:
249 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
250 case PIPE_CAP_DEPTH_BOUNDS_TEST:
251 case PIPE_CAP_CLEAR_TEXTURE:
252 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
253 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
254 case PIPE_CAP_CULL_DISTANCE:
255 case PIPE_CAP_CUBE_MAP_ARRAY:
256 case PIPE_CAP_DOUBLES:
257 return 1;
258
259 /* MSAA support
260 * If user has explicitly set max_sample_count = 0 (via SWR_MSAA_MAX_COUNT)
261 * then disable all MSAA support and go back to old caps. */
262 case PIPE_CAP_TEXTURE_MULTISAMPLE:
263 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
264 return swr_screen(screen)->msaa_max_count ? 1 : 0;
265 case PIPE_CAP_FAKE_SW_MSAA:
266 return swr_screen(screen)->msaa_max_count ? 0 : 1;
267
268 /* unsupported features */
269 case PIPE_CAP_ANISOTROPIC_FILTER:
270 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
271 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
272 case PIPE_CAP_SHADER_STENCIL_EXPORT:
273 case PIPE_CAP_TEXTURE_BARRIER:
274 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
275 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
276 case PIPE_CAP_COMPUTE:
277 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
278 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
279 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
280 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
281 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
282 case PIPE_CAP_TGSI_TEXCOORD:
283 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
284 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
285 case PIPE_CAP_TEXTURE_GATHER_SM5:
286 case PIPE_CAP_TEXTURE_QUERY_LOD:
287 case PIPE_CAP_SAMPLE_SHADING:
288 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
289 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
290 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
291 case PIPE_CAP_SAMPLER_VIEW_TARGET:
292 case PIPE_CAP_VERTEXID_NOBASE:
293 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
294 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
295 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
296 case PIPE_CAP_TGSI_TXQS:
297 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
298 case PIPE_CAP_SHAREABLE_SHADERS:
299 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
300 case PIPE_CAP_DRAW_PARAMETERS:
301 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
302 case PIPE_CAP_MULTI_DRAW_INDIRECT:
303 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
304 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
305 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
306 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
307 case PIPE_CAP_INVALIDATE_BUFFER:
308 case PIPE_CAP_GENERATE_MIPMAP:
309 case PIPE_CAP_STRING_MARKER:
310 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
311 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
312 case PIPE_CAP_QUERY_BUFFER_OBJECT:
313 case PIPE_CAP_QUERY_MEMORY_INFO:
314 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
315 case PIPE_CAP_PCI_GROUP:
316 case PIPE_CAP_PCI_BUS:
317 case PIPE_CAP_PCI_DEVICE:
318 case PIPE_CAP_PCI_FUNCTION:
319 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
320 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
321 case PIPE_CAP_TGSI_VOTE:
322 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
323 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
324 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
325 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
326 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
327 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
328 case PIPE_CAP_NATIVE_FENCE_FD:
329 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
330 case PIPE_CAP_TGSI_FS_FBFETCH:
331 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
332 case PIPE_CAP_INT64:
333 case PIPE_CAP_INT64_DIVMOD:
334 case PIPE_CAP_TGSI_TEX_TXF_LZ:
335 case PIPE_CAP_TGSI_CLOCK:
336 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
337 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
338 case PIPE_CAP_TGSI_BALLOT:
339 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
340 return 0;
341
342 case PIPE_CAP_VENDOR_ID:
343 return 0xFFFFFFFF;
344 case PIPE_CAP_DEVICE_ID:
345 return 0xFFFFFFFF;
346 case PIPE_CAP_ACCELERATED:
347 return 0;
348 case PIPE_CAP_VIDEO_MEMORY: {
349 /* XXX: Do we want to return the full amount of system memory ? */
350 uint64_t system_memory;
351
352 if (!os_get_total_physical_memory(&system_memory))
353 return 0;
354
355 return (int)(system_memory >> 20);
356 }
357 }
358
359 /* should only get here on unhandled cases */
360 debug_printf("Unexpected PIPE_CAP %d query\n", param);
361 return 0;
362 }
363
364 static int
365 swr_get_shader_param(struct pipe_screen *screen,
366 enum pipe_shader_type shader,
367 enum pipe_shader_cap param)
368 {
369 if (shader == PIPE_SHADER_VERTEX ||
370 shader == PIPE_SHADER_FRAGMENT ||
371 shader == PIPE_SHADER_GEOMETRY)
372 return gallivm_get_shader_param(param);
373
374 // Todo: tesselation, compute
375 return 0;
376 }
377
378
379 static float
380 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
381 {
382 switch (param) {
383 case PIPE_CAPF_MAX_LINE_WIDTH:
384 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
385 case PIPE_CAPF_MAX_POINT_WIDTH:
386 return 255.0; /* arbitrary */
387 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
388 return 0.0;
389 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
390 return 0.0;
391 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
392 return 16.0; /* arbitrary */
393 case PIPE_CAPF_GUARD_BAND_LEFT:
394 case PIPE_CAPF_GUARD_BAND_TOP:
395 case PIPE_CAPF_GUARD_BAND_RIGHT:
396 case PIPE_CAPF_GUARD_BAND_BOTTOM:
397 return 0.0;
398 }
399 /* should only get here on unhandled cases */
400 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
401 return 0.0;
402 }
403
404 SWR_FORMAT
405 mesa_to_swr_format(enum pipe_format format)
406 {
407 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
408 /* depth / stencil */
409 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
410 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
411 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
412 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
413 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
414
415 /* alpha */
416 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
417 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
418 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
419 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
420
421 /* odd sizes, bgr */
422 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
423 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
424 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
425 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
426 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
427 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
428 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
429 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
430 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
431
432 /* rgb10a2 */
433 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
434 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
435 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
436 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
437 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
438
439 /* rgb10x2 */
440 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
441
442 /* bgr10a2 */
443 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
444 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
445 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
446 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
447 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
448
449 /* bgr10x2 */
450 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
451
452 /* r11g11b10 */
453 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
454
455 /* 32 bits per component */
456 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
457 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
458 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
459 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
460 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
461
462 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
463 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
464 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
465 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
466
467 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
468 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
469 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
470 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
471
472 {PIPE_FORMAT_R32_UINT, R32_UINT},
473 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
474 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
475 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
476
477 {PIPE_FORMAT_R32_SINT, R32_SINT},
478 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
479 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
480 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
481
482 /* 16 bits per component */
483 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
484 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
485 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
486 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
487 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
488
489 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
490 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
491 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
492 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
493
494 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
495 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
496 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
497 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
498
499 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
500 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
501 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
502 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
503
504 {PIPE_FORMAT_R16_UINT, R16_UINT},
505 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
506 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
507 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
508
509 {PIPE_FORMAT_R16_SINT, R16_SINT},
510 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
511 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
512 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
513
514 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
515 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
516 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
517 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
518 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
519
520 /* 8 bits per component */
521 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
522 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
523 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
524 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
525 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
526 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
527 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
528 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
529
530 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
531 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
532 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
533 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
534
535 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
536 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
537 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
538 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
539
540 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
541 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
542 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
543 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
544
545 {PIPE_FORMAT_R8_UINT, R8_UINT},
546 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
547 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
548 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
549
550 {PIPE_FORMAT_R8_SINT, R8_SINT},
551 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
552 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
553 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
554
555 /* These formats are valid for vertex data, but should not be used
556 * for render targets.
557 */
558
559 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
560 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
561 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
562 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
563
564 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
565 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
566 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
567 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
568
569 /* These formats have entries in SWR but don't have Load/StoreTile
570 * implementations. That means these aren't renderable, and thus having
571 * a mapping entry here is detrimental.
572 */
573 /*
574
575 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
576 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
577 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
578 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
579 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
580
581 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
582 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
583
584 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
585 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
586 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
587
588 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
589 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
590 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
591
592 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
593 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
594 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
595 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
596
597 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
598 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
599 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
600 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
601 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
602 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
603 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
604 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
605
606 {PIPE_FORMAT_I8_UINT, I8_UINT},
607 {PIPE_FORMAT_L8_UINT, L8_UINT},
608 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
609
610 {PIPE_FORMAT_I8_SINT, I8_SINT},
611 {PIPE_FORMAT_L8_SINT, L8_SINT},
612 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
613
614 */
615 };
616
617 auto it = mesa2swr.find(format);
618 if (it == mesa2swr.end())
619 return (SWR_FORMAT)-1;
620 else
621 return it->second;
622 }
623
624 static boolean
625 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
626 {
627 struct sw_winsys *winsys = screen->winsys;
628 struct sw_displaytarget *dt;
629
630 const unsigned width = align(res->swr.width, res->swr.halign);
631 const unsigned height = align(res->swr.height, res->swr.valign);
632
633 UINT stride;
634 dt = winsys->displaytarget_create(winsys,
635 res->base.bind,
636 res->base.format,
637 width, height,
638 64, NULL,
639 &stride);
640
641 if (dt == NULL)
642 return FALSE;
643
644 void *map = winsys->displaytarget_map(winsys, dt, 0);
645
646 res->display_target = dt;
647 res->swr.pBaseAddress = (uint8_t*) map;
648
649 /* Clear the display target surface */
650 if (map)
651 memset(map, 0, height * stride);
652
653 winsys->displaytarget_unmap(winsys, dt);
654
655 return TRUE;
656 }
657
658 static bool
659 swr_texture_layout(struct swr_screen *screen,
660 struct swr_resource *res,
661 boolean allocate)
662 {
663 struct pipe_resource *pt = &res->base;
664
665 pipe_format fmt = pt->format;
666 const struct util_format_description *desc = util_format_description(fmt);
667
668 res->has_depth = util_format_has_depth(desc);
669 res->has_stencil = util_format_has_stencil(desc);
670
671 if (res->has_stencil && !res->has_depth)
672 fmt = PIPE_FORMAT_R8_UINT;
673
674 /* We always use the SWR layout. For 2D and 3D textures this looks like:
675 *
676 * |<------- pitch ------->|
677 * +=======================+-------
678 * |Array 0 | ^
679 * | | |
680 * | Level 0 | |
681 * | | |
682 * | | qpitch
683 * +-----------+-----------+ |
684 * | | L2L2L2L2 | |
685 * | Level 1 | L3L3 | |
686 * | | L4 | v
687 * +===========+===========+-------
688 * |Array 1 |
689 * | |
690 * | Level 0 |
691 * | |
692 * | |
693 * +-----------+-----------+
694 * | | L2L2L2L2 |
695 * | Level 1 | L3L3 |
696 * | | L4 |
697 * +===========+===========+
698 *
699 * The overall width in bytes is known as the pitch, while the overall
700 * height in rows is the qpitch. Array slices are laid out logically below
701 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
702 * just invalid for the higher array numbers (since depth is also
703 * minified). 1D and 1D array surfaces are stored effectively the same way,
704 * except that pitch never plays into it. All the levels are logically
705 * adjacent to each other on the X axis. The qpitch becomes the number of
706 * elements between array slices, while the pitch is unused.
707 *
708 * Each level's sizes are subject to the valign and halign settings of the
709 * surface. For compressed formats that swr is unaware of, we will use an
710 * appropriately-sized uncompressed format, and scale the widths/heights.
711 *
712 * This surface is stored inside res->swr. For depth/stencil textures,
713 * res->secondary will have an identically-laid-out but R8_UINT-formatted
714 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
715 * texels, to simplify map/unmap logic which copies the stencil values
716 * in/out.
717 */
718
719 res->swr.width = pt->width0;
720 res->swr.height = pt->height0;
721 res->swr.type = swr_convert_target_type(pt->target);
722 res->swr.tileMode = SWR_TILE_NONE;
723 res->swr.format = mesa_to_swr_format(fmt);
724 res->swr.numSamples = std::max(1u, pt->nr_samples);
725
726 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
727 res->swr.halign = KNOB_MACROTILE_X_DIM;
728 res->swr.valign = KNOB_MACROTILE_Y_DIM;
729
730 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
731 * surface sample count. */
732 if (screen->msaa_force_enable) {
733 res->swr.numSamples = screen->msaa_max_count;
734 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
735 res->swr.numSamples);
736 }
737 } else {
738 res->swr.halign = 1;
739 res->swr.valign = 1;
740 }
741
742 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
743 unsigned width = align(pt->width0, halign);
744 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
745 for (int level = 1; level <= pt->last_level; level++)
746 width += align(u_minify(pt->width0, level), halign);
747 res->swr.pitch = util_format_get_blocksize(fmt);
748 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
749 } else {
750 // The pitch is the overall width of the texture in bytes. Most of the
751 // time this is the pitch of level 0 since all the other levels fit
752 // underneath it. However in some degenerate situations, the width of
753 // level1 + level2 may be larger. In that case, we use those
754 // widths. This can happen if, e.g. halign is 32, and the width of level
755 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
756 // be 32 each, adding up to 64.
757 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
758 if (pt->last_level > 1) {
759 width = std::max<uint32_t>(
760 width,
761 align(u_minify(pt->width0, 1), halign) +
762 align(u_minify(pt->width0, 2), halign));
763 }
764 res->swr.pitch = util_format_get_stride(fmt, width);
765
766 // The qpitch is controlled by either the height of the second LOD, or
767 // the combination of all the later LODs.
768 unsigned height = align(pt->height0, valign);
769 if (pt->last_level == 1) {
770 height += align(u_minify(pt->height0, 1), valign);
771 } else if (pt->last_level > 1) {
772 unsigned level1 = align(u_minify(pt->height0, 1), valign);
773 unsigned level2 = 0;
774 for (int level = 2; level <= pt->last_level; level++) {
775 level2 += align(u_minify(pt->height0, level), valign);
776 }
777 height += std::max(level1, level2);
778 }
779 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
780 }
781
782 if (pt->target == PIPE_TEXTURE_3D)
783 res->swr.depth = pt->depth0;
784 else
785 res->swr.depth = pt->array_size;
786
787 // Fix up swr format if necessary so that LOD offset computation works
788 if (res->swr.format == (SWR_FORMAT)-1) {
789 switch (util_format_get_blocksize(fmt)) {
790 default:
791 unreachable("Unexpected format block size");
792 case 1: res->swr.format = R8_UINT; break;
793 case 2: res->swr.format = R16_UINT; break;
794 case 4: res->swr.format = R32_UINT; break;
795 case 8:
796 if (util_format_is_compressed(fmt))
797 res->swr.format = BC4_UNORM;
798 else
799 res->swr.format = R32G32_UINT;
800 break;
801 case 16:
802 if (util_format_is_compressed(fmt))
803 res->swr.format = BC5_UNORM;
804 else
805 res->swr.format = R32G32B32A32_UINT;
806 break;
807 }
808 }
809
810 for (int level = 0; level <= pt->last_level; level++) {
811 res->mip_offsets[level] =
812 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
813 }
814
815 size_t total_size = res->swr.depth * res->swr.qpitch * res->swr.pitch *
816 res->swr.numSamples;
817 if (total_size > SWR_MAX_TEXTURE_SIZE)
818 return false;
819
820 if (allocate) {
821 res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
822
823 if (res->has_depth && res->has_stencil) {
824 res->secondary = res->swr;
825 res->secondary.format = R8_UINT;
826 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
827
828 for (int level = 0; level <= pt->last_level; level++) {
829 res->secondary_mip_offsets[level] =
830 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
831 }
832
833 total_size = res->secondary.depth * res->secondary.qpitch *
834 res->secondary.pitch * res->secondary.numSamples;
835
836 res->secondary.pBaseAddress = (uint8_t *) AlignedMalloc(total_size,
837 64);
838 }
839 }
840
841 return true;
842 }
843
844 static boolean
845 swr_can_create_resource(struct pipe_screen *screen,
846 const struct pipe_resource *templat)
847 {
848 struct swr_resource res;
849 memset(&res, 0, sizeof(res));
850 res.base = *templat;
851 return swr_texture_layout(swr_screen(screen), &res, false);
852 }
853
854 /* Helper function that conditionally creates a single-sample resolve resource
855 * and attaches it to main multisample resource. */
856 static boolean
857 swr_create_resolve_resource(struct pipe_screen *_screen,
858 struct swr_resource *msaa_res)
859 {
860 struct swr_screen *screen = swr_screen(_screen);
861
862 /* If resource is multisample, create a single-sample resolve resource */
863 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
864 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
865
866 /* Create a single-sample copy of the resource. Copy the original
867 * resource parameters and set flag to prevent recursion when re-calling
868 * resource_create */
869 struct pipe_resource alt_template = msaa_res->base;
870 alt_template.nr_samples = 0;
871 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
872
873 /* Note: Display_target is a special single-sample resource, only the
874 * display_target has been created already. */
875 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
876 | PIPE_BIND_SHARED)) {
877 /* Allocate the multisample buffers. */
878 if (!swr_texture_layout(screen, msaa_res, true))
879 return false;
880
881 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
882 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
883 alt_template.bind = PIPE_BIND_RENDER_TARGET;
884 }
885
886 /* Allocate single-sample resolve surface */
887 struct pipe_resource *alt;
888 alt = _screen->resource_create(_screen, &alt_template);
889 if (!alt)
890 return false;
891
892 /* Attach it to the multisample resource */
893 msaa_res->resolve_target = alt;
894 }
895
896 return true; /* success */
897 }
898
899 static struct pipe_resource *
900 swr_resource_create(struct pipe_screen *_screen,
901 const struct pipe_resource *templat)
902 {
903 struct swr_screen *screen = swr_screen(_screen);
904 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
905 if (!res)
906 return NULL;
907
908 res->base = *templat;
909 pipe_reference_init(&res->base.reference, 1);
910 res->base.screen = &screen->base;
911
912 if (swr_resource_is_texture(&res->base)) {
913 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
914 | PIPE_BIND_SHARED)) {
915 /* displayable surface
916 * first call swr_texture_layout without allocating to finish
917 * filling out the SWR_SURFACE_STATE in res */
918 swr_texture_layout(screen, res, false);
919 if (!swr_displaytarget_layout(screen, res))
920 goto fail;
921 } else {
922 /* texture map */
923 if (!swr_texture_layout(screen, res, true))
924 goto fail;
925 }
926
927 /* If resource was multisample, create resolve resource and attach
928 * it to multisample resource. */
929 if (!swr_create_resolve_resource(_screen, res))
930 goto fail;
931
932 } else {
933 /* other data (vertex buffer, const buffer, etc) */
934 assert(util_format_get_blocksize(templat->format) == 1);
935 assert(templat->height0 == 1);
936 assert(templat->depth0 == 1);
937 assert(templat->last_level == 0);
938
939 /* Easiest to just call swr_texture_layout, as it sets up
940 * SWR_SURFACE_STATE in res */
941 if (!swr_texture_layout(screen, res, true))
942 goto fail;
943 }
944
945 return &res->base;
946
947 fail:
948 FREE(res);
949 return NULL;
950 }
951
952 static void
953 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
954 {
955 struct swr_screen *screen = swr_screen(p_screen);
956 struct swr_resource *spr = swr_resource(pt);
957
958 if (spr->display_target) {
959 /* If resource is display target, winsys manages the buffer and will
960 * free it on displaytarget_destroy. */
961 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
962
963 struct sw_winsys *winsys = screen->winsys;
964 winsys->displaytarget_destroy(winsys, spr->display_target);
965
966 if (spr->swr.numSamples > 1) {
967 /* Free an attached resolve resource */
968 struct swr_resource *alt = swr_resource(spr->resolve_target);
969 swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true);
970
971 /* Free multisample buffer */
972 swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
973 }
974 } else {
975 /* For regular resources, defer deletion */
976 swr_resource_unused(pt);
977
978 if (spr->swr.numSamples > 1) {
979 /* Free an attached resolve resource */
980 struct swr_resource *alt = swr_resource(spr->resolve_target);
981 swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true);
982 }
983
984 swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
985 swr_fence_work_free(screen->flush_fence,
986 spr->secondary.pBaseAddress, true);
987 }
988
989 FREE(spr);
990 }
991
992
993 static void
994 swr_flush_frontbuffer(struct pipe_screen *p_screen,
995 struct pipe_resource *resource,
996 unsigned level,
997 unsigned layer,
998 void *context_private,
999 struct pipe_box *sub_box)
1000 {
1001 struct swr_screen *screen = swr_screen(p_screen);
1002 struct sw_winsys *winsys = screen->winsys;
1003 struct swr_resource *spr = swr_resource(resource);
1004 struct pipe_context *pipe = screen->pipe;
1005
1006 if (pipe) {
1007 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1008 swr_resource_unused(resource);
1009 SwrEndFrame(swr_context(pipe)->swrContext);
1010 }
1011
1012 /* Multisample surfaces need to be resolved before present */
1013 if (pipe && spr->swr.numSamples > 1) {
1014 struct pipe_resource *resolve_target = spr->resolve_target;
1015
1016 /* Do an inline surface resolve into the resolve target resource
1017 * XXX: This works, just not optimal. Work on using a pipelined blit. */
1018 swr_do_msaa_resolve(resource, resolve_target);
1019
1020 /* Once resolved, copy into display target */
1021 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1022
1023 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1024 PIPE_TRANSFER_WRITE);
1025 memcpy(map, resolve->pBaseAddress, resolve->pitch * resolve->height);
1026 winsys->displaytarget_unmap(winsys, spr->display_target);
1027 }
1028
1029 debug_assert(spr->display_target);
1030 if (spr->display_target)
1031 winsys->displaytarget_display(
1032 winsys, spr->display_target, context_private, sub_box);
1033 }
1034
1035
1036 static void
1037 swr_destroy_screen(struct pipe_screen *p_screen)
1038 {
1039 struct swr_screen *screen = swr_screen(p_screen);
1040 struct sw_winsys *winsys = screen->winsys;
1041
1042 fprintf(stderr, "SWR destroy screen!\n");
1043
1044 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1045 swr_fence_reference(p_screen, &screen->flush_fence, NULL);
1046
1047 JitDestroyContext(screen->hJitMgr);
1048
1049 if (winsys->destroy)
1050 winsys->destroy(winsys);
1051
1052 FREE(screen);
1053 }
1054
1055 PUBLIC
1056 struct pipe_screen *
1057 swr_create_screen_internal(struct sw_winsys *winsys)
1058 {
1059 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1060
1061 if (!screen)
1062 return NULL;
1063
1064 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
1065 g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152);
1066 }
1067
1068 if (!lp_build_init()) {
1069 FREE(screen);
1070 return NULL;
1071 }
1072
1073 screen->winsys = winsys;
1074 screen->base.get_name = swr_get_name;
1075 screen->base.get_vendor = swr_get_vendor;
1076 screen->base.is_format_supported = swr_is_format_supported;
1077 screen->base.context_create = swr_create_context;
1078 screen->base.can_create_resource = swr_can_create_resource;
1079
1080 screen->base.destroy = swr_destroy_screen;
1081 screen->base.get_param = swr_get_param;
1082 screen->base.get_shader_param = swr_get_shader_param;
1083 screen->base.get_paramf = swr_get_paramf;
1084
1085 screen->base.resource_create = swr_resource_create;
1086 screen->base.resource_destroy = swr_resource_destroy;
1087
1088 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1089
1090 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
1091
1092 swr_fence_init(&screen->base);
1093
1094 util_format_s3tc_init();
1095
1096 /* XXX msaa under development, disable by default for now */
1097 screen->msaa_max_count = 0; /* was SWR_MAX_NUM_MULTISAMPLES; */
1098
1099 /* validate env override values, within range and power of 2 */
1100 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 0);
1101 if (msaa_max_count) {
1102 if ((msaa_max_count < 0) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1103 || !util_is_power_of_two(msaa_max_count)) {
1104 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1105 fprintf(stderr, "must be power of 2 between 1 and %d" \
1106 " (or 0 to disable msaa)\n",
1107 SWR_MAX_NUM_MULTISAMPLES);
1108 msaa_max_count = 0;
1109 }
1110
1111 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1112 if (!msaa_max_count)
1113 fprintf(stderr, "(msaa disabled)\n");
1114
1115 screen->msaa_max_count = msaa_max_count;
1116 }
1117
1118 screen->msaa_force_enable = debug_get_bool_option(
1119 "SWR_MSAA_FORCE_ENABLE", false);
1120 if (screen->msaa_force_enable)
1121 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1122
1123 return &screen->base;
1124 }
1125