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swr/swr: Enable ARB_viewport_array
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_screen.h"
40
41 #include "state_tracker/sw_winsys.h"
42
43 #include "jit_api.h"
44
45 #include "memory/TilingFunctions.h"
46
47 #include <stdio.h>
48 #include <map>
49
50 /*
51 * Max texture sizes
52 * XXX Check max texture size values against core and sampler.
53 */
54 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
55 #define SWR_MAX_TEXTURE_2D_SIZE 8192
56 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
57 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
58 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
59
60 /* Default max client_copy_limit */
61 #define SWR_CLIENT_COPY_LIMIT 8192
62
63 /* Flag indicates creation of alternate surface, to prevent recursive loop
64 * in resource creation when msaa_force_enable is set. */
65 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
66
67
68 static const char *
69 swr_get_name(struct pipe_screen *screen)
70 {
71 static char buf[100];
72 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
73 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
74 lp_native_vector_width );
75 return buf;
76 }
77
78 static const char *
79 swr_get_vendor(struct pipe_screen *screen)
80 {
81 return "Intel Corporation";
82 }
83
84 static boolean
85 swr_is_format_supported(struct pipe_screen *_screen,
86 enum pipe_format format,
87 enum pipe_texture_target target,
88 unsigned sample_count,
89 unsigned storage_sample_count,
90 unsigned bind)
91 {
92 struct swr_screen *screen = swr_screen(_screen);
93 struct sw_winsys *winsys = screen->winsys;
94 const struct util_format_description *format_desc;
95
96 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
97 || target == PIPE_TEXTURE_1D_ARRAY
98 || target == PIPE_TEXTURE_2D
99 || target == PIPE_TEXTURE_2D_ARRAY
100 || target == PIPE_TEXTURE_RECT
101 || target == PIPE_TEXTURE_3D
102 || target == PIPE_TEXTURE_CUBE
103 || target == PIPE_TEXTURE_CUBE_ARRAY);
104
105 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
106 return false;
107
108 format_desc = util_format_description(format);
109 if (!format_desc)
110 return FALSE;
111
112 if ((sample_count > screen->msaa_max_count)
113 || !util_is_power_of_two_or_zero(sample_count))
114 return FALSE;
115
116 if (bind & PIPE_BIND_DISPLAY_TARGET) {
117 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
118 return FALSE;
119 }
120
121 if (bind & PIPE_BIND_RENDER_TARGET) {
122 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
123 return FALSE;
124
125 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
126 return FALSE;
127
128 /*
129 * Although possible, it is unnatural to render into compressed or YUV
130 * surfaces. So disable these here to avoid going into weird paths
131 * inside the state trackers.
132 */
133 if (format_desc->block.width != 1 || format_desc->block.height != 1)
134 return FALSE;
135 }
136
137 if (bind & PIPE_BIND_DEPTH_STENCIL) {
138 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
139 return FALSE;
140
141 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
142 return FALSE;
143 }
144
145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
146 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
147 return FALSE;
148 }
149
150 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
151 format != PIPE_FORMAT_ETC1_RGB8) {
152 return FALSE;
153 }
154
155 if ((bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) &&
156 ((bind & PIPE_BIND_DISPLAY_TARGET) == 0)) {
157 /* Disable all 3-channel formats, where channel size != 32 bits.
158 * In some cases we run into crashes (in generate_unswizzled_blend()),
159 * for 3-channel RGB16 variants, there was an apparent LLVM bug.
160 * In any case, disabling the shallower 3-channel formats avoids a
161 * number of issues with GL_ARB_copy_image support.
162 */
163 if (format_desc->is_array &&
164 format_desc->nr_channels == 3 &&
165 format_desc->block.bits != 96) {
166 return FALSE;
167 }
168 }
169
170 return TRUE;
171 }
172
173 static int
174 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
175 {
176 switch (param) {
177 /* limits */
178 case PIPE_CAP_MAX_RENDER_TARGETS:
179 return PIPE_MAX_COLOR_BUFS;
180 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
181 return SWR_MAX_TEXTURE_2D_SIZE;
182 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
183 return SWR_MAX_TEXTURE_3D_LEVELS;
184 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
185 return SWR_MAX_TEXTURE_CUBE_LEVELS;
186 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
187 return MAX_SO_STREAMS;
188 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
189 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
190 return MAX_ATTRIBUTES * 4;
191 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
192 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
193 return 1024;
194 case PIPE_CAP_MAX_VERTEX_STREAMS:
195 return 1;
196 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
197 return 2048;
198 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
199 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
200 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
201 case PIPE_CAP_MIN_TEXEL_OFFSET:
202 return -8;
203 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
204 case PIPE_CAP_MAX_TEXEL_OFFSET:
205 return 7;
206 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
207 return 4;
208 case PIPE_CAP_GLSL_FEATURE_LEVEL:
209 return 330;
210 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
211 return 140;
212 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
213 return 16;
214 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
215 return 64;
216 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
217 return 65536;
218 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
219 return 1;
220 case PIPE_CAP_MAX_VIEWPORTS:
221 return KNOB_NUM_VIEWPORTS_SCISSORS;
222 case PIPE_CAP_ENDIANNESS:
223 return PIPE_ENDIAN_NATIVE;
224 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
225 return 0;
226
227 /* supported features */
228 case PIPE_CAP_NPOT_TEXTURES:
229 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
230 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
231 case PIPE_CAP_SM3:
232 case PIPE_CAP_POINT_SPRITE:
233 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
234 case PIPE_CAP_OCCLUSION_QUERY:
235 case PIPE_CAP_QUERY_TIME_ELAPSED:
236 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
237 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
238 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
239 case PIPE_CAP_TEXTURE_SWIZZLE:
240 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
241 case PIPE_CAP_INDEP_BLEND_ENABLE:
242 case PIPE_CAP_INDEP_BLEND_FUNC:
243 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
244 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
245 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
246 case PIPE_CAP_DEPTH_CLIP_DISABLE:
247 case PIPE_CAP_PRIMITIVE_RESTART:
248 case PIPE_CAP_TGSI_INSTANCEID:
249 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
250 case PIPE_CAP_START_INSTANCE:
251 case PIPE_CAP_SEAMLESS_CUBE_MAP:
252 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
253 case PIPE_CAP_CONDITIONAL_RENDER:
254 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
255 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
256 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
257 case PIPE_CAP_USER_VERTEX_BUFFERS:
258 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
259 case PIPE_CAP_QUERY_TIMESTAMP:
260 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
261 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
262 case PIPE_CAP_DRAW_INDIRECT:
263 case PIPE_CAP_UMA:
264 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
265 case PIPE_CAP_CLIP_HALFZ:
266 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
267 case PIPE_CAP_DEPTH_BOUNDS_TEST:
268 case PIPE_CAP_CLEAR_TEXTURE:
269 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
270 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
271 case PIPE_CAP_CULL_DISTANCE:
272 case PIPE_CAP_CUBE_MAP_ARRAY:
273 case PIPE_CAP_DOUBLES:
274 case PIPE_CAP_TEXTURE_QUERY_LOD:
275 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
276 return 1;
277
278 /* MSAA support
279 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
280 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
281 case PIPE_CAP_TEXTURE_MULTISAMPLE:
282 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
283 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
284 case PIPE_CAP_FAKE_SW_MSAA:
285 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
286
287 /* fetch jit change for 2-4GB buffers requires alignment */
288 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
289 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
290 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
291 return 1;
292
293 /* unsupported features */
294 case PIPE_CAP_ANISOTROPIC_FILTER:
295 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
296 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
297 case PIPE_CAP_SHADER_STENCIL_EXPORT:
298 case PIPE_CAP_TEXTURE_BARRIER:
299 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
300 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
301 case PIPE_CAP_COMPUTE:
302 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
303 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
304 case PIPE_CAP_TGSI_TEXCOORD:
305 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
306 case PIPE_CAP_TEXTURE_GATHER_SM5:
307 case PIPE_CAP_SAMPLE_SHADING:
308 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
309 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
310 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
311 case PIPE_CAP_SAMPLER_VIEW_TARGET:
312 case PIPE_CAP_VERTEXID_NOBASE:
313 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
314 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
315 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
316 case PIPE_CAP_TGSI_TXQS:
317 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
318 case PIPE_CAP_SHAREABLE_SHADERS:
319 case PIPE_CAP_DRAW_PARAMETERS:
320 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
321 case PIPE_CAP_MULTI_DRAW_INDIRECT:
322 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
323 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
324 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
325 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
326 case PIPE_CAP_INVALIDATE_BUFFER:
327 case PIPE_CAP_GENERATE_MIPMAP:
328 case PIPE_CAP_STRING_MARKER:
329 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
330 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
331 case PIPE_CAP_QUERY_BUFFER_OBJECT:
332 case PIPE_CAP_QUERY_MEMORY_INFO:
333 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
334 case PIPE_CAP_PCI_GROUP:
335 case PIPE_CAP_PCI_BUS:
336 case PIPE_CAP_PCI_DEVICE:
337 case PIPE_CAP_PCI_FUNCTION:
338 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
339 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
340 case PIPE_CAP_TGSI_VOTE:
341 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
342 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
343 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
344 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
345 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
346 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
347 case PIPE_CAP_NATIVE_FENCE_FD:
348 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
349 case PIPE_CAP_FBFETCH:
350 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
351 case PIPE_CAP_INT64:
352 case PIPE_CAP_INT64_DIVMOD:
353 case PIPE_CAP_TGSI_TEX_TXF_LZ:
354 case PIPE_CAP_TGSI_CLOCK:
355 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
356 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
357 case PIPE_CAP_TGSI_BALLOT:
358 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
359 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
360 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
361 case PIPE_CAP_POST_DEPTH_COVERAGE:
362 case PIPE_CAP_BINDLESS_TEXTURE:
363 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
364 case PIPE_CAP_QUERY_SO_OVERFLOW:
365 case PIPE_CAP_MEMOBJ:
366 case PIPE_CAP_LOAD_CONSTBUF:
367 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
368 case PIPE_CAP_TILE_RASTER_ORDER:
369 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
370 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
371 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
372 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
373 case PIPE_CAP_FENCE_SIGNAL:
374 case PIPE_CAP_CONSTBUF0_FLAGS:
375 case PIPE_CAP_PACKED_UNIFORMS:
376 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
377 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
378 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
379 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
380 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
381 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
382 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
383 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
384 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
385 return 0;
386 case PIPE_CAP_MAX_GS_INVOCATIONS:
387 return 32;
388 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
389 return 1 << 27;
390 case PIPE_CAP_MAX_VARYINGS:
391 return 32;
392
393 case PIPE_CAP_VENDOR_ID:
394 return 0xFFFFFFFF;
395 case PIPE_CAP_DEVICE_ID:
396 return 0xFFFFFFFF;
397 case PIPE_CAP_ACCELERATED:
398 return 0;
399 case PIPE_CAP_VIDEO_MEMORY: {
400 /* XXX: Do we want to return the full amount of system memory ? */
401 uint64_t system_memory;
402
403 if (!os_get_total_physical_memory(&system_memory))
404 return 0;
405
406 return (int)(system_memory >> 20);
407 }
408 default:
409 return u_pipe_screen_get_param_defaults(screen, param);
410 }
411 }
412
413 static int
414 swr_get_shader_param(struct pipe_screen *screen,
415 enum pipe_shader_type shader,
416 enum pipe_shader_cap param)
417 {
418 if (shader == PIPE_SHADER_VERTEX ||
419 shader == PIPE_SHADER_FRAGMENT ||
420 shader == PIPE_SHADER_GEOMETRY)
421 return gallivm_get_shader_param(param);
422
423 // Todo: tesselation, compute
424 return 0;
425 }
426
427
428 static float
429 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
430 {
431 switch (param) {
432 case PIPE_CAPF_MAX_LINE_WIDTH:
433 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
434 case PIPE_CAPF_MAX_POINT_WIDTH:
435 return 255.0; /* arbitrary */
436 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
437 return 0.0;
438 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
439 return 0.0;
440 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
441 return 16.0; /* arbitrary */
442 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
443 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
444 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
445 return 0.0f;
446 }
447 /* should only get here on unhandled cases */
448 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
449 return 0.0;
450 }
451
452 SWR_FORMAT
453 mesa_to_swr_format(enum pipe_format format)
454 {
455 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
456 /* depth / stencil */
457 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
458 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
459 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
460 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
461 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
462
463 /* alpha */
464 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
465 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
466 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
467 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
468
469 /* odd sizes, bgr */
470 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
471 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
472 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
473 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
474 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
475 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
476 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
477 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
478 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
479
480 /* rgb10a2 */
481 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
482 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
483 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
484 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
485 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
486
487 /* rgb10x2 */
488 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
489
490 /* bgr10a2 */
491 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
492 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
493 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
494 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
495 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
496
497 /* bgr10x2 */
498 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
499
500 /* r11g11b10 */
501 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
502
503 /* 32 bits per component */
504 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
505 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
506 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
507 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
508 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
509
510 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
511 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
512 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
513 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
514
515 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
516 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
517 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
518 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
519
520 {PIPE_FORMAT_R32_UINT, R32_UINT},
521 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
522 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
523 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
524
525 {PIPE_FORMAT_R32_SINT, R32_SINT},
526 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
527 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
528 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
529
530 /* 16 bits per component */
531 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
532 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
533 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
534 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
535 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
536
537 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
538 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
539 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
540 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
541
542 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
543 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
544 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
545 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
546
547 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
548 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
549 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
550 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
551
552 {PIPE_FORMAT_R16_UINT, R16_UINT},
553 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
554 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
555 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
556
557 {PIPE_FORMAT_R16_SINT, R16_SINT},
558 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
559 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
560 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
561
562 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
563 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
564 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
565 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
566 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
567
568 /* 8 bits per component */
569 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
570 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
571 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
572 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
573 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
574 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
575 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
576 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
577
578 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
579 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
580 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
581 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
582
583 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
584 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
585 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
586 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
587
588 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
589 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
590 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
591 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
592
593 {PIPE_FORMAT_R8_UINT, R8_UINT},
594 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
595 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
596 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
597
598 {PIPE_FORMAT_R8_SINT, R8_SINT},
599 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
600 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
601 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
602
603 /* These formats are valid for vertex data, but should not be used
604 * for render targets.
605 */
606
607 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
608 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
609 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
610 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
611
612 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
613 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
614 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
615 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
616
617 /* These formats have entries in SWR but don't have Load/StoreTile
618 * implementations. That means these aren't renderable, and thus having
619 * a mapping entry here is detrimental.
620 */
621 /*
622
623 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
624 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
625 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
626 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
627 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
628
629 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
630 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
631
632 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
633 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
634 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
635
636 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
637 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
638 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
639
640 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
641 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
642 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
643 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
644
645 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
646 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
647 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
648 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
649 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
650 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
651 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
652 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
653
654 {PIPE_FORMAT_I8_UINT, I8_UINT},
655 {PIPE_FORMAT_L8_UINT, L8_UINT},
656 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
657
658 {PIPE_FORMAT_I8_SINT, I8_SINT},
659 {PIPE_FORMAT_L8_SINT, L8_SINT},
660 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
661
662 */
663 };
664
665 auto it = mesa2swr.find(format);
666 if (it == mesa2swr.end())
667 return (SWR_FORMAT)-1;
668 else
669 return it->second;
670 }
671
672 static boolean
673 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
674 {
675 struct sw_winsys *winsys = screen->winsys;
676 struct sw_displaytarget *dt;
677
678 const unsigned width = align(res->swr.width, res->swr.halign);
679 const unsigned height = align(res->swr.height, res->swr.valign);
680
681 UINT stride;
682 dt = winsys->displaytarget_create(winsys,
683 res->base.bind,
684 res->base.format,
685 width, height,
686 64, NULL,
687 &stride);
688
689 if (dt == NULL)
690 return FALSE;
691
692 void *map = winsys->displaytarget_map(winsys, dt, 0);
693
694 res->display_target = dt;
695 res->swr.xpBaseAddress = (gfxptr_t)map;
696
697 /* Clear the display target surface */
698 if (map)
699 memset(map, 0, height * stride);
700
701 winsys->displaytarget_unmap(winsys, dt);
702
703 return TRUE;
704 }
705
706 static bool
707 swr_texture_layout(struct swr_screen *screen,
708 struct swr_resource *res,
709 boolean allocate)
710 {
711 struct pipe_resource *pt = &res->base;
712
713 pipe_format fmt = pt->format;
714 const struct util_format_description *desc = util_format_description(fmt);
715
716 res->has_depth = util_format_has_depth(desc);
717 res->has_stencil = util_format_has_stencil(desc);
718
719 if (res->has_stencil && !res->has_depth)
720 fmt = PIPE_FORMAT_R8_UINT;
721
722 /* We always use the SWR layout. For 2D and 3D textures this looks like:
723 *
724 * |<------- pitch ------->|
725 * +=======================+-------
726 * |Array 0 | ^
727 * | | |
728 * | Level 0 | |
729 * | | |
730 * | | qpitch
731 * +-----------+-----------+ |
732 * | | L2L2L2L2 | |
733 * | Level 1 | L3L3 | |
734 * | | L4 | v
735 * +===========+===========+-------
736 * |Array 1 |
737 * | |
738 * | Level 0 |
739 * | |
740 * | |
741 * +-----------+-----------+
742 * | | L2L2L2L2 |
743 * | Level 1 | L3L3 |
744 * | | L4 |
745 * +===========+===========+
746 *
747 * The overall width in bytes is known as the pitch, while the overall
748 * height in rows is the qpitch. Array slices are laid out logically below
749 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
750 * just invalid for the higher array numbers (since depth is also
751 * minified). 1D and 1D array surfaces are stored effectively the same way,
752 * except that pitch never plays into it. All the levels are logically
753 * adjacent to each other on the X axis. The qpitch becomes the number of
754 * elements between array slices, while the pitch is unused.
755 *
756 * Each level's sizes are subject to the valign and halign settings of the
757 * surface. For compressed formats that swr is unaware of, we will use an
758 * appropriately-sized uncompressed format, and scale the widths/heights.
759 *
760 * This surface is stored inside res->swr. For depth/stencil textures,
761 * res->secondary will have an identically-laid-out but R8_UINT-formatted
762 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
763 * texels, to simplify map/unmap logic which copies the stencil values
764 * in/out.
765 */
766
767 res->swr.width = pt->width0;
768 res->swr.height = pt->height0;
769 res->swr.type = swr_convert_target_type(pt->target);
770 res->swr.tileMode = SWR_TILE_NONE;
771 res->swr.format = mesa_to_swr_format(fmt);
772 res->swr.numSamples = std::max(1u, pt->nr_samples);
773
774 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
775 res->swr.halign = KNOB_MACROTILE_X_DIM;
776 res->swr.valign = KNOB_MACROTILE_Y_DIM;
777
778 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
779 * surface sample count. */
780 if (screen->msaa_force_enable) {
781 res->swr.numSamples = screen->msaa_max_count;
782 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
783 res->swr.numSamples);
784 }
785 } else {
786 res->swr.halign = 1;
787 res->swr.valign = 1;
788 }
789
790 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
791 unsigned width = align(pt->width0, halign);
792 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
793 for (int level = 1; level <= pt->last_level; level++)
794 width += align(u_minify(pt->width0, level), halign);
795 res->swr.pitch = util_format_get_blocksize(fmt);
796 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
797 } else {
798 // The pitch is the overall width of the texture in bytes. Most of the
799 // time this is the pitch of level 0 since all the other levels fit
800 // underneath it. However in some degenerate situations, the width of
801 // level1 + level2 may be larger. In that case, we use those
802 // widths. This can happen if, e.g. halign is 32, and the width of level
803 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
804 // be 32 each, adding up to 64.
805 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
806 if (pt->last_level > 1) {
807 width = std::max<uint32_t>(
808 width,
809 align(u_minify(pt->width0, 1), halign) +
810 align(u_minify(pt->width0, 2), halign));
811 }
812 res->swr.pitch = util_format_get_stride(fmt, width);
813
814 // The qpitch is controlled by either the height of the second LOD, or
815 // the combination of all the later LODs.
816 unsigned height = align(pt->height0, valign);
817 if (pt->last_level == 1) {
818 height += align(u_minify(pt->height0, 1), valign);
819 } else if (pt->last_level > 1) {
820 unsigned level1 = align(u_minify(pt->height0, 1), valign);
821 unsigned level2 = 0;
822 for (int level = 2; level <= pt->last_level; level++) {
823 level2 += align(u_minify(pt->height0, level), valign);
824 }
825 height += std::max(level1, level2);
826 }
827 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
828 }
829
830 if (pt->target == PIPE_TEXTURE_3D)
831 res->swr.depth = pt->depth0;
832 else
833 res->swr.depth = pt->array_size;
834
835 // Fix up swr format if necessary so that LOD offset computation works
836 if (res->swr.format == (SWR_FORMAT)-1) {
837 switch (util_format_get_blocksize(fmt)) {
838 default:
839 unreachable("Unexpected format block size");
840 case 1: res->swr.format = R8_UINT; break;
841 case 2: res->swr.format = R16_UINT; break;
842 case 4: res->swr.format = R32_UINT; break;
843 case 8:
844 if (util_format_is_compressed(fmt))
845 res->swr.format = BC4_UNORM;
846 else
847 res->swr.format = R32G32_UINT;
848 break;
849 case 16:
850 if (util_format_is_compressed(fmt))
851 res->swr.format = BC5_UNORM;
852 else
853 res->swr.format = R32G32B32A32_UINT;
854 break;
855 }
856 }
857
858 for (int level = 0; level <= pt->last_level; level++) {
859 res->mip_offsets[level] =
860 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
861 }
862
863 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
864 res->swr.pitch * res->swr.numSamples;
865
866 // Let non-sampled textures (e.g. buffer objects) bypass the size limit
867 if (swr_resource_is_texture(&res->base) && total_size > SWR_MAX_TEXTURE_SIZE)
868 return false;
869
870 if (allocate) {
871 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
872 if (!res->swr.xpBaseAddress)
873 return false;
874
875 if (res->has_depth && res->has_stencil) {
876 res->secondary = res->swr;
877 res->secondary.format = R8_UINT;
878 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
879
880 for (int level = 0; level <= pt->last_level; level++) {
881 res->secondary_mip_offsets[level] =
882 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
883 }
884
885 total_size = res->secondary.depth * res->secondary.qpitch *
886 res->secondary.pitch * res->secondary.numSamples;
887
888 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
889 if (!res->secondary.xpBaseAddress) {
890 AlignedFree((void *)res->swr.xpBaseAddress);
891 return false;
892 }
893 }
894 }
895
896 return true;
897 }
898
899 static boolean
900 swr_can_create_resource(struct pipe_screen *screen,
901 const struct pipe_resource *templat)
902 {
903 struct swr_resource res;
904 memset(&res, 0, sizeof(res));
905 res.base = *templat;
906 return swr_texture_layout(swr_screen(screen), &res, false);
907 }
908
909 /* Helper function that conditionally creates a single-sample resolve resource
910 * and attaches it to main multisample resource. */
911 static boolean
912 swr_create_resolve_resource(struct pipe_screen *_screen,
913 struct swr_resource *msaa_res)
914 {
915 struct swr_screen *screen = swr_screen(_screen);
916
917 /* If resource is multisample, create a single-sample resolve resource */
918 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
919 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
920
921 /* Create a single-sample copy of the resource. Copy the original
922 * resource parameters and set flag to prevent recursion when re-calling
923 * resource_create */
924 struct pipe_resource alt_template = msaa_res->base;
925 alt_template.nr_samples = 0;
926 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
927
928 /* Note: Display_target is a special single-sample resource, only the
929 * display_target has been created already. */
930 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
931 | PIPE_BIND_SHARED)) {
932 /* Allocate the multisample buffers. */
933 if (!swr_texture_layout(screen, msaa_res, true))
934 return false;
935
936 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
937 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
938 alt_template.bind = PIPE_BIND_RENDER_TARGET;
939 }
940
941 /* Allocate single-sample resolve surface */
942 struct pipe_resource *alt;
943 alt = _screen->resource_create(_screen, &alt_template);
944 if (!alt)
945 return false;
946
947 /* Attach it to the multisample resource */
948 msaa_res->resolve_target = alt;
949
950 /* Hang resolve surface state off the multisample surface state to so
951 * StoreTiles knows where to resolve the surface. */
952 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
953 }
954
955 return true; /* success */
956 }
957
958 static struct pipe_resource *
959 swr_resource_create(struct pipe_screen *_screen,
960 const struct pipe_resource *templat)
961 {
962 struct swr_screen *screen = swr_screen(_screen);
963 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
964 if (!res)
965 return NULL;
966
967 res->base = *templat;
968 pipe_reference_init(&res->base.reference, 1);
969 res->base.screen = &screen->base;
970
971 if (swr_resource_is_texture(&res->base)) {
972 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
973 | PIPE_BIND_SHARED)) {
974 /* displayable surface
975 * first call swr_texture_layout without allocating to finish
976 * filling out the SWR_SURFACE_STATE in res */
977 swr_texture_layout(screen, res, false);
978 if (!swr_displaytarget_layout(screen, res))
979 goto fail;
980 } else {
981 /* texture map */
982 if (!swr_texture_layout(screen, res, true))
983 goto fail;
984 }
985
986 /* If resource was multisample, create resolve resource and attach
987 * it to multisample resource. */
988 if (!swr_create_resolve_resource(_screen, res))
989 goto fail;
990
991 } else {
992 /* other data (vertex buffer, const buffer, etc) */
993 assert(util_format_get_blocksize(templat->format) == 1);
994 assert(templat->height0 == 1);
995 assert(templat->depth0 == 1);
996 assert(templat->last_level == 0);
997
998 /* Easiest to just call swr_texture_layout, as it sets up
999 * SWR_SURFACE_STATE in res */
1000 if (!swr_texture_layout(screen, res, true))
1001 goto fail;
1002 }
1003
1004 return &res->base;
1005
1006 fail:
1007 FREE(res);
1008 return NULL;
1009 }
1010
1011 static void
1012 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
1013 {
1014 struct swr_screen *screen = swr_screen(p_screen);
1015 struct swr_resource *spr = swr_resource(pt);
1016
1017 if (spr->display_target) {
1018 /* If resource is display target, winsys manages the buffer and will
1019 * free it on displaytarget_destroy. */
1020 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1021
1022 struct sw_winsys *winsys = screen->winsys;
1023 winsys->displaytarget_destroy(winsys, spr->display_target);
1024
1025 if (spr->swr.numSamples > 1) {
1026 /* Free an attached resolve resource */
1027 struct swr_resource *alt = swr_resource(spr->resolve_target);
1028 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1029
1030 /* Free multisample buffer */
1031 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1032 }
1033 } else {
1034 /* For regular resources, defer deletion */
1035 swr_resource_unused(pt);
1036
1037 if (spr->swr.numSamples > 1) {
1038 /* Free an attached resolve resource */
1039 struct swr_resource *alt = swr_resource(spr->resolve_target);
1040 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1041 }
1042
1043 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1044 swr_fence_work_free(screen->flush_fence,
1045 (void*)(spr->secondary.xpBaseAddress), true);
1046
1047 /* If work queue grows too large, submit a fence to force queue to
1048 * drain. This is mainly to decrease the amount of memory used by the
1049 * piglit streaming-texture-leak test */
1050 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1051 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1052 }
1053
1054 FREE(spr);
1055 }
1056
1057
1058 static void
1059 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1060 struct pipe_resource *resource,
1061 unsigned level,
1062 unsigned layer,
1063 void *context_private,
1064 struct pipe_box *sub_box)
1065 {
1066 struct swr_screen *screen = swr_screen(p_screen);
1067 struct sw_winsys *winsys = screen->winsys;
1068 struct swr_resource *spr = swr_resource(resource);
1069 struct pipe_context *pipe = screen->pipe;
1070 struct swr_context *ctx = swr_context(pipe);
1071
1072 if (pipe) {
1073 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1074 swr_resource_unused(resource);
1075 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1076 }
1077
1078 /* Multisample resolved into resolve_target at flush with store_resource */
1079 if (pipe && spr->swr.numSamples > 1) {
1080 struct pipe_resource *resolve_target = spr->resolve_target;
1081
1082 /* Once resolved, copy into display target */
1083 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1084
1085 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1086 PIPE_TRANSFER_WRITE);
1087 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1088 winsys->displaytarget_unmap(winsys, spr->display_target);
1089 }
1090
1091 debug_assert(spr->display_target);
1092 if (spr->display_target)
1093 winsys->displaytarget_display(
1094 winsys, spr->display_target, context_private, sub_box);
1095 }
1096
1097
1098 void
1099 swr_destroy_screen_internal(struct swr_screen **screen)
1100 {
1101 struct pipe_screen *p_screen = &(*screen)->base;
1102
1103 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1104 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1105
1106 JitDestroyContext((*screen)->hJitMgr);
1107
1108 if ((*screen)->pLibrary)
1109 util_dl_close((*screen)->pLibrary);
1110
1111 FREE(*screen);
1112 *screen = NULL;
1113 }
1114
1115
1116 static void
1117 swr_destroy_screen(struct pipe_screen *p_screen)
1118 {
1119 struct swr_screen *screen = swr_screen(p_screen);
1120 struct sw_winsys *winsys = screen->winsys;
1121
1122 fprintf(stderr, "SWR destroy screen!\n");
1123
1124 if (winsys->destroy)
1125 winsys->destroy(winsys);
1126
1127 swr_destroy_screen_internal(&screen);
1128 }
1129
1130
1131 static void
1132 swr_validate_env_options(struct swr_screen *screen)
1133 {
1134 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1135 * copied to scratch space on a draw. Past this, the draw will access
1136 * user-buffer directly and then block. This is faster than queuing many
1137 * large client draws. */
1138 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1139 int client_copy_limit =
1140 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1141 if (client_copy_limit > 0)
1142 screen->client_copy_limit = client_copy_limit;
1143
1144 /* XXX msaa under development, disable by default for now */
1145 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1146
1147 /* validate env override values, within range and power of 2 */
1148 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1149 if (msaa_max_count != 1) {
1150 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1151 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1152 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1153 fprintf(stderr, "must be power of 2 between 1 and %d" \
1154 " (or 1 to disable msaa)\n",
1155 SWR_MAX_NUM_MULTISAMPLES);
1156 msaa_max_count = 1;
1157 }
1158
1159 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1160 if (msaa_max_count == 1)
1161 fprintf(stderr, "(msaa disabled)\n");
1162
1163 screen->msaa_max_count = msaa_max_count;
1164 }
1165
1166 screen->msaa_force_enable = debug_get_bool_option(
1167 "SWR_MSAA_FORCE_ENABLE", false);
1168 if (screen->msaa_force_enable)
1169 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1170 }
1171
1172
1173 struct pipe_screen *
1174 swr_create_screen_internal(struct sw_winsys *winsys)
1175 {
1176 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1177
1178 if (!screen)
1179 return NULL;
1180
1181 if (!lp_build_init()) {
1182 FREE(screen);
1183 return NULL;
1184 }
1185
1186 screen->winsys = winsys;
1187 screen->base.get_name = swr_get_name;
1188 screen->base.get_vendor = swr_get_vendor;
1189 screen->base.is_format_supported = swr_is_format_supported;
1190 screen->base.context_create = swr_create_context;
1191 screen->base.can_create_resource = swr_can_create_resource;
1192
1193 screen->base.destroy = swr_destroy_screen;
1194 screen->base.get_param = swr_get_param;
1195 screen->base.get_shader_param = swr_get_shader_param;
1196 screen->base.get_paramf = swr_get_paramf;
1197
1198 screen->base.resource_create = swr_resource_create;
1199 screen->base.resource_destroy = swr_resource_destroy;
1200
1201 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1202
1203 // Pass in "" for architecture for run-time determination
1204 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1205
1206 swr_fence_init(&screen->base);
1207
1208 swr_validate_env_options(screen);
1209
1210 return &screen->base;
1211 }
1212