1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 ***************************************************************************/
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
40 #include "state_tracker/sw_winsys.h"
43 #include "gallivm/lp_bld_limits.h"
48 #include "memory/TilingFunctions.h"
53 /* MSVC case instensitive compare */
54 #if defined(PIPE_CC_MSVC)
55 #define strcasecmp lstrcmpiA
60 * XXX Check max texture size values against core and sampler.
62 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
63 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
64 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
65 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
66 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
69 swr_get_name(struct pipe_screen
*screen
)
72 util_snprintf(buf
, sizeof(buf
), "SWR (LLVM %u.%u, %u bits)",
73 HAVE_LLVM
>> 8, HAVE_LLVM
& 0xff,
74 lp_native_vector_width
);
79 swr_get_vendor(struct pipe_screen
*screen
)
81 return "Intel Corporation";
85 swr_is_format_supported(struct pipe_screen
*screen
,
86 enum pipe_format format
,
87 enum pipe_texture_target target
,
88 unsigned sample_count
,
91 struct sw_winsys
*winsys
= swr_screen(screen
)->winsys
;
92 const struct util_format_description
*format_desc
;
94 assert(target
== PIPE_BUFFER
|| target
== PIPE_TEXTURE_1D
95 || target
== PIPE_TEXTURE_1D_ARRAY
96 || target
== PIPE_TEXTURE_2D
97 || target
== PIPE_TEXTURE_2D_ARRAY
98 || target
== PIPE_TEXTURE_RECT
99 || target
== PIPE_TEXTURE_3D
100 || target
== PIPE_TEXTURE_CUBE
101 || target
== PIPE_TEXTURE_CUBE_ARRAY
);
103 format_desc
= util_format_description(format
);
107 if (sample_count
> 1)
111 & (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
| PIPE_BIND_SHARED
)) {
112 if (!winsys
->is_displaytarget_format_supported(winsys
, bind
, format
))
116 if (bind
& PIPE_BIND_RENDER_TARGET
) {
117 if (format_desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
)
120 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
124 * Although possible, it is unnatural to render into compressed or YUV
125 * surfaces. So disable these here to avoid going into weird paths
126 * inside the state trackers.
128 if (format_desc
->block
.width
!= 1 || format_desc
->block
.height
!= 1)
132 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
133 if (format_desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
136 if (mesa_to_swr_format(format
) == (SWR_FORMAT
)-1)
140 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
||
141 format_desc
->layout
== UTIL_FORMAT_LAYOUT_ASTC
) {
145 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
146 format
!= PIPE_FORMAT_ETC1_RGB8
) {
150 if (format_desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
151 return util_format_s3tc_enabled
;
158 swr_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
162 case PIPE_CAP_MAX_RENDER_TARGETS
:
163 return PIPE_MAX_COLOR_BUFS
;
164 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
165 return SWR_MAX_TEXTURE_2D_LEVELS
;
166 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
167 return SWR_MAX_TEXTURE_3D_LEVELS
;
168 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
169 return SWR_MAX_TEXTURE_CUBE_LEVELS
;
170 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
171 return MAX_SO_STREAMS
;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
173 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
174 return MAX_ATTRIBUTES
* 4;
175 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
176 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
178 case PIPE_CAP_MAX_VERTEX_STREAMS
:
180 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
182 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
183 return SWR_MAX_TEXTURE_ARRAY_LAYERS
;
184 case PIPE_CAP_MIN_TEXEL_OFFSET
:
186 case PIPE_CAP_MAX_TEXEL_OFFSET
:
188 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
190 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
192 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
194 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
196 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
198 case PIPE_CAP_MAX_VIEWPORTS
:
200 case PIPE_CAP_ENDIANNESS
:
201 return PIPE_ENDIAN_NATIVE
;
202 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
203 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
206 /* supported features */
207 case PIPE_CAP_NPOT_TEXTURES
:
208 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
209 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
210 case PIPE_CAP_TWO_SIDED_STENCIL
:
212 case PIPE_CAP_POINT_SPRITE
:
213 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
214 case PIPE_CAP_OCCLUSION_QUERY
:
215 case PIPE_CAP_QUERY_TIME_ELAPSED
:
216 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
217 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
218 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
219 case PIPE_CAP_TEXTURE_SWIZZLE
:
220 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
221 case PIPE_CAP_INDEP_BLEND_ENABLE
:
222 case PIPE_CAP_INDEP_BLEND_FUNC
:
223 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
224 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
225 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
226 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
227 case PIPE_CAP_PRIMITIVE_RESTART
:
228 case PIPE_CAP_TGSI_INSTANCEID
:
229 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
230 case PIPE_CAP_START_INSTANCE
:
231 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
232 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
233 case PIPE_CAP_CONDITIONAL_RENDER
:
234 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
235 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
236 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
237 case PIPE_CAP_USER_VERTEX_BUFFERS
:
238 case PIPE_CAP_USER_INDEX_BUFFERS
:
239 case PIPE_CAP_USER_CONSTANT_BUFFERS
:
240 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
241 case PIPE_CAP_QUERY_TIMESTAMP
:
242 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
243 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
244 case PIPE_CAP_FAKE_SW_MSAA
:
245 case PIPE_CAP_DRAW_INDIRECT
:
247 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
248 case PIPE_CAP_CLIP_HALFZ
:
249 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
250 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
251 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
252 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
253 case PIPE_CAP_CULL_DISTANCE
:
254 case PIPE_CAP_CUBE_MAP_ARRAY
:
257 /* unsupported features */
258 case PIPE_CAP_ANISOTROPIC_FILTER
:
259 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
260 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
261 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
262 case PIPE_CAP_TEXTURE_BARRIER
:
263 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
264 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
265 case PIPE_CAP_COMPUTE
:
266 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
267 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
268 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
269 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
270 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
271 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
272 case PIPE_CAP_TGSI_TEXCOORD
:
273 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
274 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
275 case PIPE_CAP_TEXTURE_GATHER_SM5
:
276 case PIPE_CAP_TEXTURE_QUERY_LOD
:
277 case PIPE_CAP_SAMPLE_SHADING
:
278 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
279 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
280 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
281 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
282 case PIPE_CAP_VERTEXID_NOBASE
:
283 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
284 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
285 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
286 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
287 case PIPE_CAP_TGSI_TXQS
:
288 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
289 case PIPE_CAP_SHAREABLE_SHADERS
:
290 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
291 case PIPE_CAP_CLEAR_TEXTURE
:
292 case PIPE_CAP_DRAW_PARAMETERS
:
293 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
294 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
295 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
296 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
297 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
298 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
299 case PIPE_CAP_INVALIDATE_BUFFER
:
300 case PIPE_CAP_GENERATE_MIPMAP
:
301 case PIPE_CAP_STRING_MARKER
:
302 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
303 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
304 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
305 case PIPE_CAP_QUERY_MEMORY_INFO
:
306 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
307 case PIPE_CAP_PCI_GROUP
:
308 case PIPE_CAP_PCI_BUS
:
309 case PIPE_CAP_PCI_DEVICE
:
310 case PIPE_CAP_PCI_FUNCTION
:
311 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
312 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
313 case PIPE_CAP_TGSI_VOTE
:
314 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
315 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
316 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
317 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
318 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
319 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
320 case PIPE_CAP_NATIVE_FENCE_FD
:
323 case PIPE_CAP_VENDOR_ID
:
325 case PIPE_CAP_DEVICE_ID
:
327 case PIPE_CAP_ACCELERATED
:
329 case PIPE_CAP_VIDEO_MEMORY
: {
330 /* XXX: Do we want to return the full amount of system memory ? */
331 uint64_t system_memory
;
333 if (!os_get_total_physical_memory(&system_memory
))
336 return (int)(system_memory
>> 20);
340 /* should only get here on unhandled cases */
341 debug_printf("Unexpected PIPE_CAP %d query\n", param
);
346 swr_get_shader_param(struct pipe_screen
*screen
,
348 enum pipe_shader_cap param
)
350 if (shader
== PIPE_SHADER_VERTEX
|| shader
== PIPE_SHADER_FRAGMENT
)
351 return gallivm_get_shader_param(param
);
353 // Todo: geometry, tesselation, compute
359 swr_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
362 case PIPE_CAPF_MAX_LINE_WIDTH
:
363 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
364 case PIPE_CAPF_MAX_POINT_WIDTH
:
365 return 255.0; /* arbitrary */
366 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
368 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
370 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
371 return 16.0; /* arbitrary */
372 case PIPE_CAPF_GUARD_BAND_LEFT
:
373 case PIPE_CAPF_GUARD_BAND_TOP
:
374 case PIPE_CAPF_GUARD_BAND_RIGHT
:
375 case PIPE_CAPF_GUARD_BAND_BOTTOM
:
378 /* should only get here on unhandled cases */
379 debug_printf("Unexpected PIPE_CAPF %d query\n", param
);
384 mesa_to_swr_format(enum pipe_format format
)
386 static const std::map
<pipe_format
,SWR_FORMAT
> mesa2swr
= {
387 /* depth / stencil */
388 {PIPE_FORMAT_Z16_UNORM
, R16_UNORM
}, // z
389 {PIPE_FORMAT_Z32_FLOAT
, R32_FLOAT
}, // z
390 {PIPE_FORMAT_Z24_UNORM_S8_UINT
, R24_UNORM_X8_TYPELESS
}, // z
391 {PIPE_FORMAT_Z24X8_UNORM
, R24_UNORM_X8_TYPELESS
}, // z
392 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
, R32_FLOAT_X8X24_TYPELESS
}, // z
395 {PIPE_FORMAT_A8_UNORM
, A8_UNORM
},
396 {PIPE_FORMAT_A16_UNORM
, A16_UNORM
},
397 {PIPE_FORMAT_A16_FLOAT
, A16_FLOAT
},
398 {PIPE_FORMAT_A32_FLOAT
, A32_FLOAT
},
401 {PIPE_FORMAT_B5G6R5_UNORM
, B5G6R5_UNORM
},
402 {PIPE_FORMAT_B5G6R5_SRGB
, B5G6R5_UNORM_SRGB
},
403 {PIPE_FORMAT_B5G5R5A1_UNORM
, B5G5R5A1_UNORM
},
404 {PIPE_FORMAT_B5G5R5X1_UNORM
, B5G5R5X1_UNORM
},
405 {PIPE_FORMAT_B4G4R4A4_UNORM
, B4G4R4A4_UNORM
},
406 {PIPE_FORMAT_B8G8R8A8_UNORM
, B8G8R8A8_UNORM
},
407 {PIPE_FORMAT_B8G8R8A8_SRGB
, B8G8R8A8_UNORM_SRGB
},
408 {PIPE_FORMAT_B8G8R8X8_UNORM
, B8G8R8X8_UNORM
},
409 {PIPE_FORMAT_B8G8R8X8_SRGB
, B8G8R8X8_UNORM_SRGB
},
412 {PIPE_FORMAT_R10G10B10A2_UNORM
, R10G10B10A2_UNORM
},
413 {PIPE_FORMAT_R10G10B10A2_SNORM
, R10G10B10A2_SNORM
},
414 {PIPE_FORMAT_R10G10B10A2_USCALED
, R10G10B10A2_USCALED
},
415 {PIPE_FORMAT_R10G10B10A2_SSCALED
, R10G10B10A2_SSCALED
},
416 {PIPE_FORMAT_R10G10B10A2_UINT
, R10G10B10A2_UINT
},
419 {PIPE_FORMAT_R10G10B10X2_USCALED
, R10G10B10X2_USCALED
},
422 {PIPE_FORMAT_B10G10R10A2_UNORM
, B10G10R10A2_UNORM
},
423 {PIPE_FORMAT_B10G10R10A2_SNORM
, B10G10R10A2_SNORM
},
424 {PIPE_FORMAT_B10G10R10A2_USCALED
, B10G10R10A2_USCALED
},
425 {PIPE_FORMAT_B10G10R10A2_SSCALED
, B10G10R10A2_SSCALED
},
426 {PIPE_FORMAT_B10G10R10A2_UINT
, B10G10R10A2_UINT
},
429 {PIPE_FORMAT_B10G10R10X2_UNORM
, B10G10R10X2_UNORM
},
432 {PIPE_FORMAT_R11G11B10_FLOAT
, R11G11B10_FLOAT
},
434 /* 32 bits per component */
435 {PIPE_FORMAT_R32_FLOAT
, R32_FLOAT
},
436 {PIPE_FORMAT_R32G32_FLOAT
, R32G32_FLOAT
},
437 {PIPE_FORMAT_R32G32B32_FLOAT
, R32G32B32_FLOAT
},
438 {PIPE_FORMAT_R32G32B32A32_FLOAT
, R32G32B32A32_FLOAT
},
439 {PIPE_FORMAT_R32G32B32X32_FLOAT
, R32G32B32X32_FLOAT
},
441 {PIPE_FORMAT_R32_USCALED
, R32_USCALED
},
442 {PIPE_FORMAT_R32G32_USCALED
, R32G32_USCALED
},
443 {PIPE_FORMAT_R32G32B32_USCALED
, R32G32B32_USCALED
},
444 {PIPE_FORMAT_R32G32B32A32_USCALED
, R32G32B32A32_USCALED
},
446 {PIPE_FORMAT_R32_SSCALED
, R32_SSCALED
},
447 {PIPE_FORMAT_R32G32_SSCALED
, R32G32_SSCALED
},
448 {PIPE_FORMAT_R32G32B32_SSCALED
, R32G32B32_SSCALED
},
449 {PIPE_FORMAT_R32G32B32A32_SSCALED
, R32G32B32A32_SSCALED
},
451 {PIPE_FORMAT_R32_UINT
, R32_UINT
},
452 {PIPE_FORMAT_R32G32_UINT
, R32G32_UINT
},
453 {PIPE_FORMAT_R32G32B32_UINT
, R32G32B32_UINT
},
454 {PIPE_FORMAT_R32G32B32A32_UINT
, R32G32B32A32_UINT
},
456 {PIPE_FORMAT_R32_SINT
, R32_SINT
},
457 {PIPE_FORMAT_R32G32_SINT
, R32G32_SINT
},
458 {PIPE_FORMAT_R32G32B32_SINT
, R32G32B32_SINT
},
459 {PIPE_FORMAT_R32G32B32A32_SINT
, R32G32B32A32_SINT
},
461 /* 16 bits per component */
462 {PIPE_FORMAT_R16_UNORM
, R16_UNORM
},
463 {PIPE_FORMAT_R16G16_UNORM
, R16G16_UNORM
},
464 {PIPE_FORMAT_R16G16B16_UNORM
, R16G16B16_UNORM
},
465 {PIPE_FORMAT_R16G16B16A16_UNORM
, R16G16B16A16_UNORM
},
466 {PIPE_FORMAT_R16G16B16X16_UNORM
, R16G16B16X16_UNORM
},
468 {PIPE_FORMAT_R16_USCALED
, R16_USCALED
},
469 {PIPE_FORMAT_R16G16_USCALED
, R16G16_USCALED
},
470 {PIPE_FORMAT_R16G16B16_USCALED
, R16G16B16_USCALED
},
471 {PIPE_FORMAT_R16G16B16A16_USCALED
, R16G16B16A16_USCALED
},
473 {PIPE_FORMAT_R16_SNORM
, R16_SNORM
},
474 {PIPE_FORMAT_R16G16_SNORM
, R16G16_SNORM
},
475 {PIPE_FORMAT_R16G16B16_SNORM
, R16G16B16_SNORM
},
476 {PIPE_FORMAT_R16G16B16A16_SNORM
, R16G16B16A16_SNORM
},
478 {PIPE_FORMAT_R16_SSCALED
, R16_SSCALED
},
479 {PIPE_FORMAT_R16G16_SSCALED
, R16G16_SSCALED
},
480 {PIPE_FORMAT_R16G16B16_SSCALED
, R16G16B16_SSCALED
},
481 {PIPE_FORMAT_R16G16B16A16_SSCALED
, R16G16B16A16_SSCALED
},
483 {PIPE_FORMAT_R16_UINT
, R16_UINT
},
484 {PIPE_FORMAT_R16G16_UINT
, R16G16_UINT
},
485 {PIPE_FORMAT_R16G16B16_UINT
, R16G16B16_UINT
},
486 {PIPE_FORMAT_R16G16B16A16_UINT
, R16G16B16A16_UINT
},
488 {PIPE_FORMAT_R16_SINT
, R16_SINT
},
489 {PIPE_FORMAT_R16G16_SINT
, R16G16_SINT
},
490 {PIPE_FORMAT_R16G16B16_SINT
, R16G16B16_SINT
},
491 {PIPE_FORMAT_R16G16B16A16_SINT
, R16G16B16A16_SINT
},
493 {PIPE_FORMAT_R16_FLOAT
, R16_FLOAT
},
494 {PIPE_FORMAT_R16G16_FLOAT
, R16G16_FLOAT
},
495 {PIPE_FORMAT_R16G16B16_FLOAT
, R16G16B16_FLOAT
},
496 {PIPE_FORMAT_R16G16B16A16_FLOAT
, R16G16B16A16_FLOAT
},
497 {PIPE_FORMAT_R16G16B16X16_FLOAT
, R16G16B16X16_FLOAT
},
499 /* 8 bits per component */
500 {PIPE_FORMAT_R8_UNORM
, R8_UNORM
},
501 {PIPE_FORMAT_R8G8_UNORM
, R8G8_UNORM
},
502 {PIPE_FORMAT_R8G8B8_UNORM
, R8G8B8_UNORM
},
503 {PIPE_FORMAT_R8G8B8_SRGB
, R8G8B8_UNORM_SRGB
},
504 {PIPE_FORMAT_R8G8B8A8_UNORM
, R8G8B8A8_UNORM
},
505 {PIPE_FORMAT_R8G8B8A8_SRGB
, R8G8B8A8_UNORM_SRGB
},
506 {PIPE_FORMAT_R8G8B8X8_UNORM
, R8G8B8X8_UNORM
},
507 {PIPE_FORMAT_R8G8B8X8_SRGB
, R8G8B8X8_UNORM_SRGB
},
509 {PIPE_FORMAT_R8_USCALED
, R8_USCALED
},
510 {PIPE_FORMAT_R8G8_USCALED
, R8G8_USCALED
},
511 {PIPE_FORMAT_R8G8B8_USCALED
, R8G8B8_USCALED
},
512 {PIPE_FORMAT_R8G8B8A8_USCALED
, R8G8B8A8_USCALED
},
514 {PIPE_FORMAT_R8_SNORM
, R8_SNORM
},
515 {PIPE_FORMAT_R8G8_SNORM
, R8G8_SNORM
},
516 {PIPE_FORMAT_R8G8B8_SNORM
, R8G8B8_SNORM
},
517 {PIPE_FORMAT_R8G8B8A8_SNORM
, R8G8B8A8_SNORM
},
519 {PIPE_FORMAT_R8_SSCALED
, R8_SSCALED
},
520 {PIPE_FORMAT_R8G8_SSCALED
, R8G8_SSCALED
},
521 {PIPE_FORMAT_R8G8B8_SSCALED
, R8G8B8_SSCALED
},
522 {PIPE_FORMAT_R8G8B8A8_SSCALED
, R8G8B8A8_SSCALED
},
524 {PIPE_FORMAT_R8_UINT
, R8_UINT
},
525 {PIPE_FORMAT_R8G8_UINT
, R8G8_UINT
},
526 {PIPE_FORMAT_R8G8B8_UINT
, R8G8B8_UINT
},
527 {PIPE_FORMAT_R8G8B8A8_UINT
, R8G8B8A8_UINT
},
529 {PIPE_FORMAT_R8_SINT
, R8_SINT
},
530 {PIPE_FORMAT_R8G8_SINT
, R8G8_SINT
},
531 {PIPE_FORMAT_R8G8B8_SINT
, R8G8B8_SINT
},
532 {PIPE_FORMAT_R8G8B8A8_SINT
, R8G8B8A8_SINT
},
534 /* These formats are valid for vertex data, but should not be used
535 * for render targets.
538 {PIPE_FORMAT_R32_FIXED
, R32_SFIXED
},
539 {PIPE_FORMAT_R32G32_FIXED
, R32G32_SFIXED
},
540 {PIPE_FORMAT_R32G32B32_FIXED
, R32G32B32_SFIXED
},
541 {PIPE_FORMAT_R32G32B32A32_FIXED
, R32G32B32A32_SFIXED
},
543 /* These formats have entries in SWR but don't have Load/StoreTile
544 * implementations. That means these aren't renderable, and thus having
545 * a mapping entry here is detrimental.
549 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
550 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
551 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
552 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
553 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
555 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
556 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
558 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
559 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
560 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
562 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
563 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
564 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
566 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
567 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
568 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
569 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
571 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
572 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
573 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
574 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
575 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
576 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
577 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
578 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
580 {PIPE_FORMAT_I8_UINT, I8_UINT},
581 {PIPE_FORMAT_L8_UINT, L8_UINT},
582 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
584 {PIPE_FORMAT_I8_SINT, I8_SINT},
585 {PIPE_FORMAT_L8_SINT, L8_SINT},
586 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
591 auto it
= mesa2swr
.find(format
);
592 if (it
== mesa2swr
.end())
593 return (SWR_FORMAT
)-1;
599 swr_displaytarget_layout(struct swr_screen
*screen
, struct swr_resource
*res
)
601 struct sw_winsys
*winsys
= screen
->winsys
;
602 struct sw_displaytarget
*dt
;
604 const unsigned width
= align(res
->swr
.width
, res
->swr
.halign
);
605 const unsigned height
= align(res
->swr
.height
, res
->swr
.valign
);
608 dt
= winsys
->displaytarget_create(winsys
,
618 void *map
= winsys
->displaytarget_map(winsys
, dt
, 0);
620 res
->display_target
= dt
;
621 res
->swr
.pBaseAddress
= (uint8_t*) map
;
623 /* Clear the display target surface */
625 memset(map
, 0, height
* stride
);
627 winsys
->displaytarget_unmap(winsys
, dt
);
633 swr_texture_layout(struct swr_screen
*screen
,
634 struct swr_resource
*res
,
637 struct pipe_resource
*pt
= &res
->base
;
639 pipe_format fmt
= pt
->format
;
640 const struct util_format_description
*desc
= util_format_description(fmt
);
642 res
->has_depth
= util_format_has_depth(desc
);
643 res
->has_stencil
= util_format_has_stencil(desc
);
645 if (res
->has_stencil
&& !res
->has_depth
)
646 fmt
= PIPE_FORMAT_R8_UINT
;
648 /* We always use the SWR layout. For 2D and 3D textures this looks like:
650 * |<------- pitch ------->|
651 * +=======================+-------
657 * +-----------+-----------+ |
659 * | Level 1 | L3L3 | |
661 * +===========+===========+-------
667 * +-----------+-----------+
671 * +===========+===========+
673 * The overall width in bytes is known as the pitch, while the overall
674 * height in rows is the qpitch. Array slices are laid out logically below
675 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
676 * just invalid for the higher array numbers (since depth is also
677 * minified). 1D and 1D array surfaces are stored effectively the same way,
678 * except that pitch never plays into it. All the levels are logically
679 * adjacent to each other on the X axis. The qpitch becomes the number of
680 * elements between array slices, while the pitch is unused.
682 * Each level's sizes are subject to the valign and halign settings of the
683 * surface. For compressed formats that swr is unaware of, we will use an
684 * appropriately-sized uncompressed format, and scale the widths/heights.
686 * This surface is stored inside res->swr. For depth/stencil textures,
687 * res->secondary will have an identically-laid-out but R8_UINT-formatted
688 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
689 * texels, to simplify map/unmap logic which copies the stencil values
693 res
->swr
.width
= pt
->width0
;
694 res
->swr
.height
= pt
->height0
;
695 res
->swr
.type
= swr_convert_target_type(pt
->target
);
696 res
->swr
.tileMode
= SWR_TILE_NONE
;
697 res
->swr
.format
= mesa_to_swr_format(fmt
);
698 res
->swr
.numSamples
= std::max(1u, pt
->nr_samples
);
700 if (pt
->bind
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DEPTH_STENCIL
)) {
701 res
->swr
.halign
= KNOB_MACROTILE_X_DIM
;
702 res
->swr
.valign
= KNOB_MACROTILE_Y_DIM
;
708 unsigned halign
= res
->swr
.halign
* util_format_get_blockwidth(fmt
);
709 unsigned width
= align(pt
->width0
, halign
);
710 if (pt
->target
== PIPE_TEXTURE_1D
|| pt
->target
== PIPE_TEXTURE_1D_ARRAY
) {
711 for (int level
= 1; level
<= pt
->last_level
; level
++)
712 width
+= align(u_minify(pt
->width0
, level
), halign
);
713 res
->swr
.pitch
= util_format_get_blocksize(fmt
);
714 res
->swr
.qpitch
= util_format_get_nblocksx(fmt
, width
);
716 // The pitch is the overall width of the texture in bytes. Most of the
717 // time this is the pitch of level 0 since all the other levels fit
718 // underneath it. However in some degenerate situations, the width of
719 // level1 + level2 may be larger. In that case, we use those
720 // widths. This can happen if, e.g. halign is 32, and the width of level
721 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
722 // be 32 each, adding up to 64.
723 unsigned valign
= res
->swr
.valign
* util_format_get_blockheight(fmt
);
724 if (pt
->last_level
> 1) {
725 width
= std::max
<uint32_t>(
727 align(u_minify(pt
->width0
, 1), halign
) +
728 align(u_minify(pt
->width0
, 2), halign
));
730 res
->swr
.pitch
= util_format_get_stride(fmt
, width
);
732 // The qpitch is controlled by either the height of the second LOD, or
733 // the combination of all the later LODs.
734 unsigned height
= align(pt
->height0
, valign
);
735 if (pt
->last_level
== 1) {
736 height
+= align(u_minify(pt
->height0
, 1), valign
);
737 } else if (pt
->last_level
> 1) {
738 unsigned level1
= align(u_minify(pt
->height0
, 1), valign
);
740 for (int level
= 2; level
<= pt
->last_level
; level
++) {
741 level2
+= align(u_minify(pt
->height0
, level
), valign
);
743 height
+= std::max(level1
, level2
);
745 res
->swr
.qpitch
= util_format_get_nblocksy(fmt
, height
);
748 if (pt
->target
== PIPE_TEXTURE_3D
)
749 res
->swr
.depth
= pt
->depth0
;
751 res
->swr
.depth
= pt
->array_size
;
753 // Fix up swr format if necessary so that LOD offset computation works
754 if (res
->swr
.format
== (SWR_FORMAT
)-1) {
755 switch (util_format_get_blocksize(fmt
)) {
757 unreachable("Unexpected format block size");
758 case 1: res
->swr
.format
= R8_UINT
; break;
759 case 2: res
->swr
.format
= R16_UINT
; break;
760 case 4: res
->swr
.format
= R32_UINT
; break;
762 if (util_format_is_compressed(fmt
))
763 res
->swr
.format
= BC4_UNORM
;
765 res
->swr
.format
= R32G32_UINT
;
768 if (util_format_is_compressed(fmt
))
769 res
->swr
.format
= BC5_UNORM
;
771 res
->swr
.format
= R32G32B32A32_UINT
;
776 for (int level
= 0; level
<= pt
->last_level
; level
++) {
777 res
->mip_offsets
[level
] =
778 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->swr
);
782 (size_t)res
->swr
.depth
* res
->swr
.qpitch
* res
->swr
.pitch
;
783 if (total_size
> SWR_MAX_TEXTURE_SIZE
)
787 res
->swr
.pBaseAddress
= (uint8_t *)AlignedMalloc(total_size
, 64);
789 if (res
->has_depth
&& res
->has_stencil
) {
790 res
->secondary
= res
->swr
;
791 res
->secondary
.format
= R8_UINT
;
792 res
->secondary
.pitch
= res
->swr
.pitch
/ util_format_get_blocksize(fmt
);
794 for (int level
= 0; level
<= pt
->last_level
; level
++) {
795 res
->secondary_mip_offsets
[level
] =
796 ComputeSurfaceOffset
<false>(0, 0, 0, 0, 0, level
, &res
->secondary
);
799 res
->secondary
.pBaseAddress
= (uint8_t *)AlignedMalloc(
800 res
->secondary
.depth
* res
->secondary
.qpitch
*
801 res
->secondary
.pitch
, 64);
809 swr_can_create_resource(struct pipe_screen
*screen
,
810 const struct pipe_resource
*templat
)
812 struct swr_resource res
;
813 memset(&res
, 0, sizeof(res
));
815 return swr_texture_layout(swr_screen(screen
), &res
, false);
818 static struct pipe_resource
*
819 swr_resource_create(struct pipe_screen
*_screen
,
820 const struct pipe_resource
*templat
)
822 struct swr_screen
*screen
= swr_screen(_screen
);
823 struct swr_resource
*res
= CALLOC_STRUCT(swr_resource
);
827 res
->base
= *templat
;
828 pipe_reference_init(&res
->base
.reference
, 1);
829 res
->base
.screen
= &screen
->base
;
831 if (swr_resource_is_texture(&res
->base
)) {
832 if (res
->base
.bind
& (PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
833 | PIPE_BIND_SHARED
)) {
834 /* displayable surface
835 * first call swr_texture_layout without allocating to finish
836 * filling out the SWR_SURFAE_STATE in res */
837 swr_texture_layout(screen
, res
, false);
838 if (!swr_displaytarget_layout(screen
, res
))
842 if (!swr_texture_layout(screen
, res
, true))
846 /* other data (vertex buffer, const buffer, etc) */
847 assert(util_format_get_blocksize(templat
->format
) == 1);
848 assert(templat
->height0
== 1);
849 assert(templat
->depth0
== 1);
850 assert(templat
->last_level
== 0);
852 /* Easiest to just call swr_texture_layout, as it sets up
853 * SWR_SURFAE_STATE in res */
854 if (!swr_texture_layout(screen
, res
, true))
866 swr_resource_destroy(struct pipe_screen
*p_screen
, struct pipe_resource
*pt
)
868 struct swr_screen
*screen
= swr_screen(p_screen
);
869 struct swr_resource
*spr
= swr_resource(pt
);
870 struct pipe_context
*pipe
= screen
->pipe
;
872 /* Only wait on fence if the resource is being used */
873 if (pipe
&& spr
->status
) {
874 /* But, if there's no fence pending, submit one.
875 * XXX: Remove once draw timestamps are implmented. */
876 if (!swr_is_fence_pending(screen
->flush_fence
))
877 swr_fence_submit(swr_context(pipe
), screen
->flush_fence
);
879 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
880 swr_resource_unused(pt
);
884 * Free resource primary surface. If resource is display target, winsys
885 * manages the buffer and will free it on displaytarget_destroy.
887 if (spr
->display_target
) {
889 struct sw_winsys
*winsys
= screen
->winsys
;
890 winsys
->displaytarget_destroy(winsys
, spr
->display_target
);
892 AlignedFree(spr
->swr
.pBaseAddress
);
894 AlignedFree(spr
->secondary
.pBaseAddress
);
901 swr_flush_frontbuffer(struct pipe_screen
*p_screen
,
902 struct pipe_resource
*resource
,
905 void *context_private
,
906 struct pipe_box
*sub_box
)
908 struct swr_screen
*screen
= swr_screen(p_screen
);
909 struct sw_winsys
*winsys
= screen
->winsys
;
910 struct swr_resource
*spr
= swr_resource(resource
);
911 struct pipe_context
*pipe
= screen
->pipe
;
914 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
915 swr_resource_unused(resource
);
916 SwrEndFrame(swr_context(pipe
)->swrContext
);
919 debug_assert(spr
->display_target
);
920 if (spr
->display_target
)
921 winsys
->displaytarget_display(
922 winsys
, spr
->display_target
, context_private
, sub_box
);
927 swr_destroy_screen(struct pipe_screen
*p_screen
)
929 struct swr_screen
*screen
= swr_screen(p_screen
);
930 struct sw_winsys
*winsys
= screen
->winsys
;
932 fprintf(stderr
, "SWR destroy screen!\n");
934 swr_fence_finish(p_screen
, NULL
, screen
->flush_fence
, 0);
935 swr_fence_reference(p_screen
, &screen
->flush_fence
, NULL
);
937 JitDestroyContext(screen
->hJitMgr
);
940 winsys
->destroy(winsys
);
947 swr_create_screen_internal(struct sw_winsys
*winsys
)
949 struct swr_screen
*screen
= CALLOC_STRUCT(swr_screen
);
954 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
955 g_GlobalKnobs
.MAX_PRIMS_PER_DRAW
.Value(49152);
958 if (!lp_build_init()) {
963 screen
->winsys
= winsys
;
964 screen
->base
.get_name
= swr_get_name
;
965 screen
->base
.get_vendor
= swr_get_vendor
;
966 screen
->base
.is_format_supported
= swr_is_format_supported
;
967 screen
->base
.context_create
= swr_create_context
;
968 screen
->base
.can_create_resource
= swr_can_create_resource
;
970 screen
->base
.destroy
= swr_destroy_screen
;
971 screen
->base
.get_param
= swr_get_param
;
972 screen
->base
.get_shader_param
= swr_get_shader_param
;
973 screen
->base
.get_paramf
= swr_get_paramf
;
975 screen
->base
.resource_create
= swr_resource_create
;
976 screen
->base
.resource_destroy
= swr_resource_destroy
;
978 screen
->base
.flush_frontbuffer
= swr_flush_frontbuffer
;
980 screen
->hJitMgr
= JitCreateContext(KNOB_SIMD_WIDTH
, KNOB_ARCH_STR
, "swr");
982 swr_fence_init(&screen
->base
);
984 util_format_s3tc_init();
986 return &screen
->base
;