src/gallium/drivers/swr/swr_screen.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "swr_context.h"
  25 #include "swr_public.h"
  26 #include "swr_screen.h"
  27 #include "swr_resource.h"
  28 #include "swr_fence.h"
  29 #include "gen_knobs.h"
  30
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_defines.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_format.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_cpu_detect.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39
  40 #include "state_tracker/sw_winsys.h"
  41
  42 #include "jit_api.h"
  43
  44 #include "memory/TilingFunctions.h"
  45
  46 #include <stdio.h>
  47 #include <map>
  48
  49 /* MSVC case instensitive compare */
  50 #if defined(PIPE_CC_MSVC)
  51    #define strcasecmp lstrcmpiA
  52 #endif
  53
  54 /*
  55  * Max texture sizes
  56  * XXX Check max texture size values against core and sampler.
  57  */
  58 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
  59 #define SWR_MAX_TEXTURE_2D_LEVELS 14  /* 8K x 8K for now */
  60 #define SWR_MAX_TEXTURE_3D_LEVELS 12  /* 2K x 2K x 2K for now */
  61 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14  /* 8K x 8K for now */
  62 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
  63
  64 /* Flag indicates creation of alternate surface, to prevent recursive loop
  65  * in resource creation when msaa_force_enable is set. */
  66 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  67
  68
  69 static const char *
  70 swr_get_name(struct pipe_screen *screen)
  71 {
  72    static char buf[100];
  73    util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
  74                  HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
  75                  lp_native_vector_width );
  76    return buf;
  77 }
  78
  79 static const char *
  80 swr_get_vendor(struct pipe_screen *screen)
  81 {
  82    return "Intel Corporation";
  83 }
  84
  85 static boolean
  86 swr_is_format_supported(struct pipe_screen *_screen,
  87                         enum pipe_format format,
  88                         enum pipe_texture_target target,
  89                         unsigned sample_count,
  90                         unsigned bind)
  91 {
  92    struct swr_screen *screen = swr_screen(_screen);
  93    struct sw_winsys *winsys = screen->winsys;
  94    const struct util_format_description *format_desc;
  95
  96    assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
  97           || target == PIPE_TEXTURE_1D_ARRAY
  98           || target == PIPE_TEXTURE_2D
  99           || target == PIPE_TEXTURE_2D_ARRAY
 100           || target == PIPE_TEXTURE_RECT
 101           || target == PIPE_TEXTURE_3D
 102           || target == PIPE_TEXTURE_CUBE
 103           || target == PIPE_TEXTURE_CUBE_ARRAY);
 104
 105    format_desc = util_format_description(format);
 106    if (!format_desc)
 107       return FALSE;
 108
 109    if ((sample_count > screen->msaa_max_count)
 110       || !util_is_power_of_two(sample_count))
 111       return FALSE;
 112
 113    if (bind & PIPE_BIND_DISPLAY_TARGET) {
 114       if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
 115          return FALSE;
 116    }
 117
 118    if (bind & PIPE_BIND_RENDER_TARGET) {
 119       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 120          return FALSE;
 121
 122       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 123          return FALSE;
 124
 125       /*
 126        * Although possible, it is unnatural to render into compressed or YUV
 127        * surfaces. So disable these here to avoid going into weird paths
 128        * inside the state trackers.
 129        */
 130       if (format_desc->block.width != 1 || format_desc->block.height != 1)
 131          return FALSE;
 132    }
 133
 134    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 135       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 136          return FALSE;
 137
 138       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 139          return FALSE;
 140    }
 141
 142    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
 143        format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
 144       return FALSE;
 145    }
 146
 147    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
 148        format != PIPE_FORMAT_ETC1_RGB8) {
 149       return FALSE;
 150    }
 151
 152    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 153       return util_format_s3tc_enabled;
 154    }
 155
 156    return TRUE;
 157 }
 158
 159 static int
 160 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
 161 {
 162    switch (param) {
 163       /* limits */
 164    case PIPE_CAP_MAX_RENDER_TARGETS:
 165       return PIPE_MAX_COLOR_BUFS;
 166    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 167       return SWR_MAX_TEXTURE_2D_LEVELS;
 168    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 169       return SWR_MAX_TEXTURE_3D_LEVELS;
 170    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 171       return SWR_MAX_TEXTURE_CUBE_LEVELS;
 172    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 173       return MAX_SO_STREAMS;
 174    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 175    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 176       return MAX_ATTRIBUTES * 4;
 177    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 178    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 179       return 1024;
 180    case PIPE_CAP_MAX_VERTEX_STREAMS:
 181       return 1;
 182    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 183       return 2048;
 184    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 185       return SWR_MAX_TEXTURE_ARRAY_LAYERS;
 186    case PIPE_CAP_MIN_TEXEL_OFFSET:
 187       return -8;
 188    case PIPE_CAP_MAX_TEXEL_OFFSET:
 189       return 7;
 190    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 191       return 330;
 192    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 193       return 16;
 194    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 195       return 64;
 196    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 197       return 65536;
 198    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 199       return 0;
 200    case PIPE_CAP_MAX_VIEWPORTS:
 201       return 1;
 202    case PIPE_CAP_ENDIANNESS:
 203       return PIPE_ENDIAN_NATIVE;
 204    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 205    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 206       return 0;
 207
 208       /* supported features */
 209    case PIPE_CAP_NPOT_TEXTURES:
 210    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 211    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 212    case PIPE_CAP_TWO_SIDED_STENCIL:
 213    case PIPE_CAP_SM3:
 214    case PIPE_CAP_POINT_SPRITE:
 215    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 216    case PIPE_CAP_OCCLUSION_QUERY:
 217    case PIPE_CAP_QUERY_TIME_ELAPSED:
 218    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 219    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 220    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 221    case PIPE_CAP_TEXTURE_SWIZZLE:
 222    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 223    case PIPE_CAP_INDEP_BLEND_ENABLE:
 224    case PIPE_CAP_INDEP_BLEND_FUNC:
 225    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 226    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 227    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 228    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 229    case PIPE_CAP_PRIMITIVE_RESTART:
 230    case PIPE_CAP_TGSI_INSTANCEID:
 231    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 232    case PIPE_CAP_START_INSTANCE:
 233    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 234    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 235    case PIPE_CAP_CONDITIONAL_RENDER:
 236    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 237    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 238    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 239    case PIPE_CAP_USER_VERTEX_BUFFERS:
 240    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 241    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 242    case PIPE_CAP_QUERY_TIMESTAMP:
 243    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 244    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 245    case PIPE_CAP_DRAW_INDIRECT:
 246    case PIPE_CAP_UMA:
 247    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 248    case PIPE_CAP_CLIP_HALFZ:
 249    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 250    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 251    case PIPE_CAP_CLEAR_TEXTURE:
 252    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 253    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 254    case PIPE_CAP_CULL_DISTANCE:
 255    case PIPE_CAP_CUBE_MAP_ARRAY:
 256    case PIPE_CAP_DOUBLES:
 257       return 1;
 258
 259    /* MSAA support
 260     * If user has explicitly set max_sample_count = 0 (via SWR_MSAA_MAX_COUNT)
 261     * then disable all MSAA support and go back to old caps. */
 262    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 263    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 264       return swr_screen(screen)->msaa_max_count ? 1 : 0;
 265    case PIPE_CAP_FAKE_SW_MSAA:
 266       return swr_screen(screen)->msaa_max_count ? 0 : 1;
 267
 268       /* unsupported features */
 269    case PIPE_CAP_ANISOTROPIC_FILTER:
 270    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 271    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 272    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 273    case PIPE_CAP_TEXTURE_BARRIER:
 274    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 275    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 276    case PIPE_CAP_COMPUTE:
 277    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 278    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 279    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 280    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 281    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 282    case PIPE_CAP_TGSI_TEXCOORD:
 283    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 284    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 285    case PIPE_CAP_TEXTURE_GATHER_SM5:
 286    case PIPE_CAP_TEXTURE_QUERY_LOD:
 287    case PIPE_CAP_SAMPLE_SHADING:
 288    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 289    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 290    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 291    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 292    case PIPE_CAP_VERTEXID_NOBASE:
 293    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 294    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 295    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 296    case PIPE_CAP_TGSI_TXQS:
 297    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 298    case PIPE_CAP_SHAREABLE_SHADERS:
 299    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 300    case PIPE_CAP_DRAW_PARAMETERS:
 301    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 302    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 303    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 304    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 305    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 306    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 307    case PIPE_CAP_INVALIDATE_BUFFER:
 308    case PIPE_CAP_GENERATE_MIPMAP:
 309    case PIPE_CAP_STRING_MARKER:
 310    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 311    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 312    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 313    case PIPE_CAP_QUERY_MEMORY_INFO:
 314    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 315    case PIPE_CAP_PCI_GROUP:
 316    case PIPE_CAP_PCI_BUS:
 317    case PIPE_CAP_PCI_DEVICE:
 318    case PIPE_CAP_PCI_FUNCTION:
 319    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 320    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 321    case PIPE_CAP_TGSI_VOTE:
 322    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 323    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 324    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 325    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 326    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 327    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 328    case PIPE_CAP_NATIVE_FENCE_FD:
 329    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 330    case PIPE_CAP_TGSI_FS_FBFETCH:
 331    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 332    case PIPE_CAP_INT64:
 333    case PIPE_CAP_INT64_DIVMOD:
 334    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 335    case PIPE_CAP_TGSI_CLOCK:
 336    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 337    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 338    case PIPE_CAP_TGSI_BALLOT:
 339    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 340    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 341    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 342    case PIPE_CAP_POST_DEPTH_COVERAGE:
 343    case PIPE_CAP_BINDLESS_TEXTURE:
 344       return 0;
 345
 346    case PIPE_CAP_VENDOR_ID:
 347       return 0xFFFFFFFF;
 348    case PIPE_CAP_DEVICE_ID:
 349       return 0xFFFFFFFF;
 350    case PIPE_CAP_ACCELERATED:
 351       return 0;
 352    case PIPE_CAP_VIDEO_MEMORY: {
 353       /* XXX: Do we want to return the full amount of system memory ? */
 354       uint64_t system_memory;
 355
 356       if (!os_get_total_physical_memory(&system_memory))
 357          return 0;
 358
 359       return (int)(system_memory >> 20);
 360    }
 361    }
 362
 363    /* should only get here on unhandled cases */
 364    debug_printf("Unexpected PIPE_CAP %d query\n", param);
 365    return 0;
 366 }
 367
 368 static int
 369 swr_get_shader_param(struct pipe_screen *screen,
 370                      enum pipe_shader_type shader,
 371                      enum pipe_shader_cap param)
 372 {
 373    if (shader == PIPE_SHADER_VERTEX ||
 374        shader == PIPE_SHADER_FRAGMENT ||
 375        shader == PIPE_SHADER_GEOMETRY)
 376       return gallivm_get_shader_param(param);
 377
 378    // Todo: tesselation, compute
 379    return 0;
 380 }
 381
 382
 383 static float
 384 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 385 {
 386    switch (param) {
 387    case PIPE_CAPF_MAX_LINE_WIDTH:
 388    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 389    case PIPE_CAPF_MAX_POINT_WIDTH:
 390       return 255.0; /* arbitrary */
 391    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 392       return 0.0;
 393    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 394       return 0.0;
 395    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 396       return 16.0; /* arbitrary */
 397    case PIPE_CAPF_GUARD_BAND_LEFT:
 398    case PIPE_CAPF_GUARD_BAND_TOP:
 399    case PIPE_CAPF_GUARD_BAND_RIGHT:
 400    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 401       return 0.0;
 402    }
 403    /* should only get here on unhandled cases */
 404    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 405    return 0.0;
 406 }
 407
 408 SWR_FORMAT
 409 mesa_to_swr_format(enum pipe_format format)
 410 {
 411    static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
 412       /* depth / stencil */
 413       {PIPE_FORMAT_Z16_UNORM,              R16_UNORM}, // z
 414       {PIPE_FORMAT_Z32_FLOAT,              R32_FLOAT}, // z
 415       {PIPE_FORMAT_Z24_UNORM_S8_UINT,      R24_UNORM_X8_TYPELESS}, // z
 416       {PIPE_FORMAT_Z24X8_UNORM,            R24_UNORM_X8_TYPELESS}, // z
 417       {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,   R32_FLOAT_X8X24_TYPELESS}, // z
 418
 419       /* alpha */
 420       {PIPE_FORMAT_A8_UNORM,               A8_UNORM},
 421       {PIPE_FORMAT_A16_UNORM,              A16_UNORM},
 422       {PIPE_FORMAT_A16_FLOAT,              A16_FLOAT},
 423       {PIPE_FORMAT_A32_FLOAT,              A32_FLOAT},
 424
 425       /* odd sizes, bgr */
 426       {PIPE_FORMAT_B5G6R5_UNORM,           B5G6R5_UNORM},
 427       {PIPE_FORMAT_B5G6R5_SRGB,            B5G6R5_UNORM_SRGB},
 428       {PIPE_FORMAT_B5G5R5A1_UNORM,         B5G5R5A1_UNORM},
 429       {PIPE_FORMAT_B5G5R5X1_UNORM,         B5G5R5X1_UNORM},
 430       {PIPE_FORMAT_B4G4R4A4_UNORM,         B4G4R4A4_UNORM},
 431       {PIPE_FORMAT_B8G8R8A8_UNORM,         B8G8R8A8_UNORM},
 432       {PIPE_FORMAT_B8G8R8A8_SRGB,          B8G8R8A8_UNORM_SRGB},
 433       {PIPE_FORMAT_B8G8R8X8_UNORM,         B8G8R8X8_UNORM},
 434       {PIPE_FORMAT_B8G8R8X8_SRGB,          B8G8R8X8_UNORM_SRGB},
 435
 436       /* rgb10a2 */
 437       {PIPE_FORMAT_R10G10B10A2_UNORM,      R10G10B10A2_UNORM},
 438       {PIPE_FORMAT_R10G10B10A2_SNORM,      R10G10B10A2_SNORM},
 439       {PIPE_FORMAT_R10G10B10A2_USCALED,    R10G10B10A2_USCALED},
 440       {PIPE_FORMAT_R10G10B10A2_SSCALED,    R10G10B10A2_SSCALED},
 441       {PIPE_FORMAT_R10G10B10A2_UINT,       R10G10B10A2_UINT},
 442
 443       /* rgb10x2 */
 444       {PIPE_FORMAT_R10G10B10X2_USCALED,    R10G10B10X2_USCALED},
 445
 446       /* bgr10a2 */
 447       {PIPE_FORMAT_B10G10R10A2_UNORM,      B10G10R10A2_UNORM},
 448       {PIPE_FORMAT_B10G10R10A2_SNORM,      B10G10R10A2_SNORM},
 449       {PIPE_FORMAT_B10G10R10A2_USCALED,    B10G10R10A2_USCALED},
 450       {PIPE_FORMAT_B10G10R10A2_SSCALED,    B10G10R10A2_SSCALED},
 451       {PIPE_FORMAT_B10G10R10A2_UINT,       B10G10R10A2_UINT},
 452
 453       /* bgr10x2 */
 454       {PIPE_FORMAT_B10G10R10X2_UNORM,      B10G10R10X2_UNORM},
 455
 456       /* r11g11b10 */
 457       {PIPE_FORMAT_R11G11B10_FLOAT,        R11G11B10_FLOAT},
 458
 459       /* 32 bits per component */
 460       {PIPE_FORMAT_R32_FLOAT,              R32_FLOAT},
 461       {PIPE_FORMAT_R32G32_FLOAT,           R32G32_FLOAT},
 462       {PIPE_FORMAT_R32G32B32_FLOAT,        R32G32B32_FLOAT},
 463       {PIPE_FORMAT_R32G32B32A32_FLOAT,     R32G32B32A32_FLOAT},
 464       {PIPE_FORMAT_R32G32B32X32_FLOAT,     R32G32B32X32_FLOAT},
 465
 466       {PIPE_FORMAT_R32_USCALED,            R32_USCALED},
 467       {PIPE_FORMAT_R32G32_USCALED,         R32G32_USCALED},
 468       {PIPE_FORMAT_R32G32B32_USCALED,      R32G32B32_USCALED},
 469       {PIPE_FORMAT_R32G32B32A32_USCALED,   R32G32B32A32_USCALED},
 470
 471       {PIPE_FORMAT_R32_SSCALED,            R32_SSCALED},
 472       {PIPE_FORMAT_R32G32_SSCALED,         R32G32_SSCALED},
 473       {PIPE_FORMAT_R32G32B32_SSCALED,      R32G32B32_SSCALED},
 474       {PIPE_FORMAT_R32G32B32A32_SSCALED,   R32G32B32A32_SSCALED},
 475
 476       {PIPE_FORMAT_R32_UINT,               R32_UINT},
 477       {PIPE_FORMAT_R32G32_UINT,            R32G32_UINT},
 478       {PIPE_FORMAT_R32G32B32_UINT,         R32G32B32_UINT},
 479       {PIPE_FORMAT_R32G32B32A32_UINT,      R32G32B32A32_UINT},
 480
 481       {PIPE_FORMAT_R32_SINT,               R32_SINT},
 482       {PIPE_FORMAT_R32G32_SINT,            R32G32_SINT},
 483       {PIPE_FORMAT_R32G32B32_SINT,         R32G32B32_SINT},
 484       {PIPE_FORMAT_R32G32B32A32_SINT,      R32G32B32A32_SINT},
 485
 486       /* 16 bits per component */
 487       {PIPE_FORMAT_R16_UNORM,              R16_UNORM},
 488       {PIPE_FORMAT_R16G16_UNORM,           R16G16_UNORM},
 489       {PIPE_FORMAT_R16G16B16_UNORM,        R16G16B16_UNORM},
 490       {PIPE_FORMAT_R16G16B16A16_UNORM,     R16G16B16A16_UNORM},
 491       {PIPE_FORMAT_R16G16B16X16_UNORM,     R16G16B16X16_UNORM},
 492
 493       {PIPE_FORMAT_R16_USCALED,            R16_USCALED},
 494       {PIPE_FORMAT_R16G16_USCALED,         R16G16_USCALED},
 495       {PIPE_FORMAT_R16G16B16_USCALED,      R16G16B16_USCALED},
 496       {PIPE_FORMAT_R16G16B16A16_USCALED,   R16G16B16A16_USCALED},
 497
 498       {PIPE_FORMAT_R16_SNORM,              R16_SNORM},
 499       {PIPE_FORMAT_R16G16_SNORM,           R16G16_SNORM},
 500       {PIPE_FORMAT_R16G16B16_SNORM,        R16G16B16_SNORM},
 501       {PIPE_FORMAT_R16G16B16A16_SNORM,     R16G16B16A16_SNORM},
 502
 503       {PIPE_FORMAT_R16_SSCALED,            R16_SSCALED},
 504       {PIPE_FORMAT_R16G16_SSCALED,         R16G16_SSCALED},
 505       {PIPE_FORMAT_R16G16B16_SSCALED,      R16G16B16_SSCALED},
 506       {PIPE_FORMAT_R16G16B16A16_SSCALED,   R16G16B16A16_SSCALED},
 507
 508       {PIPE_FORMAT_R16_UINT,               R16_UINT},
 509       {PIPE_FORMAT_R16G16_UINT,            R16G16_UINT},
 510       {PIPE_FORMAT_R16G16B16_UINT,         R16G16B16_UINT},
 511       {PIPE_FORMAT_R16G16B16A16_UINT,      R16G16B16A16_UINT},
 512
 513       {PIPE_FORMAT_R16_SINT,               R16_SINT},
 514       {PIPE_FORMAT_R16G16_SINT,            R16G16_SINT},
 515       {PIPE_FORMAT_R16G16B16_SINT,         R16G16B16_SINT},
 516       {PIPE_FORMAT_R16G16B16A16_SINT,      R16G16B16A16_SINT},
 517
 518       {PIPE_FORMAT_R16_FLOAT,              R16_FLOAT},
 519       {PIPE_FORMAT_R16G16_FLOAT,           R16G16_FLOAT},
 520       {PIPE_FORMAT_R16G16B16_FLOAT,        R16G16B16_FLOAT},
 521       {PIPE_FORMAT_R16G16B16A16_FLOAT,     R16G16B16A16_FLOAT},
 522       {PIPE_FORMAT_R16G16B16X16_FLOAT,     R16G16B16X16_FLOAT},
 523
 524       /* 8 bits per component */
 525       {PIPE_FORMAT_R8_UNORM,               R8_UNORM},
 526       {PIPE_FORMAT_R8G8_UNORM,             R8G8_UNORM},
 527       {PIPE_FORMAT_R8G8B8_UNORM,           R8G8B8_UNORM},
 528       {PIPE_FORMAT_R8G8B8_SRGB,            R8G8B8_UNORM_SRGB},
 529       {PIPE_FORMAT_R8G8B8A8_UNORM,         R8G8B8A8_UNORM},
 530       {PIPE_FORMAT_R8G8B8A8_SRGB,          R8G8B8A8_UNORM_SRGB},
 531       {PIPE_FORMAT_R8G8B8X8_UNORM,         R8G8B8X8_UNORM},
 532       {PIPE_FORMAT_R8G8B8X8_SRGB,          R8G8B8X8_UNORM_SRGB},
 533
 534       {PIPE_FORMAT_R8_USCALED,             R8_USCALED},
 535       {PIPE_FORMAT_R8G8_USCALED,           R8G8_USCALED},
 536       {PIPE_FORMAT_R8G8B8_USCALED,         R8G8B8_USCALED},
 537       {PIPE_FORMAT_R8G8B8A8_USCALED,       R8G8B8A8_USCALED},
 538
 539       {PIPE_FORMAT_R8_SNORM,               R8_SNORM},
 540       {PIPE_FORMAT_R8G8_SNORM,             R8G8_SNORM},
 541       {PIPE_FORMAT_R8G8B8_SNORM,           R8G8B8_SNORM},
 542       {PIPE_FORMAT_R8G8B8A8_SNORM,         R8G8B8A8_SNORM},
 543
 544       {PIPE_FORMAT_R8_SSCALED,             R8_SSCALED},
 545       {PIPE_FORMAT_R8G8_SSCALED,           R8G8_SSCALED},
 546       {PIPE_FORMAT_R8G8B8_SSCALED,         R8G8B8_SSCALED},
 547       {PIPE_FORMAT_R8G8B8A8_SSCALED,       R8G8B8A8_SSCALED},
 548
 549       {PIPE_FORMAT_R8_UINT,                R8_UINT},
 550       {PIPE_FORMAT_R8G8_UINT,              R8G8_UINT},
 551       {PIPE_FORMAT_R8G8B8_UINT,            R8G8B8_UINT},
 552       {PIPE_FORMAT_R8G8B8A8_UINT,          R8G8B8A8_UINT},
 553
 554       {PIPE_FORMAT_R8_SINT,                R8_SINT},
 555       {PIPE_FORMAT_R8G8_SINT,              R8G8_SINT},
 556       {PIPE_FORMAT_R8G8B8_SINT,            R8G8B8_SINT},
 557       {PIPE_FORMAT_R8G8B8A8_SINT,          R8G8B8A8_SINT},
 558
 559       /* These formats are valid for vertex data, but should not be used
 560        * for render targets.
 561        */
 562
 563       {PIPE_FORMAT_R32_FIXED,              R32_SFIXED},
 564       {PIPE_FORMAT_R32G32_FIXED,           R32G32_SFIXED},
 565       {PIPE_FORMAT_R32G32B32_FIXED,        R32G32B32_SFIXED},
 566       {PIPE_FORMAT_R32G32B32A32_FIXED,     R32G32B32A32_SFIXED},
 567
 568       {PIPE_FORMAT_R64_FLOAT,              R64_FLOAT},
 569       {PIPE_FORMAT_R64G64_FLOAT,           R64G64_FLOAT},
 570       {PIPE_FORMAT_R64G64B64_FLOAT,        R64G64B64_FLOAT},
 571       {PIPE_FORMAT_R64G64B64A64_FLOAT,     R64G64B64A64_FLOAT},
 572
 573       /* These formats have entries in SWR but don't have Load/StoreTile
 574        * implementations. That means these aren't renderable, and thus having
 575        * a mapping entry here is detrimental.
 576        */
 577       /*
 578
 579       {PIPE_FORMAT_L8_UNORM,               L8_UNORM},
 580       {PIPE_FORMAT_I8_UNORM,               I8_UNORM},
 581       {PIPE_FORMAT_L8A8_UNORM,             L8A8_UNORM},
 582       {PIPE_FORMAT_L16_UNORM,              L16_UNORM},
 583       {PIPE_FORMAT_UYVY,                   YCRCB_SWAPUVY},
 584
 585       {PIPE_FORMAT_L8_SRGB,                L8_UNORM_SRGB},
 586       {PIPE_FORMAT_L8A8_SRGB,              L8A8_UNORM_SRGB},
 587
 588       {PIPE_FORMAT_DXT1_RGBA,              BC1_UNORM},
 589       {PIPE_FORMAT_DXT3_RGBA,              BC2_UNORM},
 590       {PIPE_FORMAT_DXT5_RGBA,              BC3_UNORM},
 591
 592       {PIPE_FORMAT_DXT1_SRGBA,             BC1_UNORM_SRGB},
 593       {PIPE_FORMAT_DXT3_SRGBA,             BC2_UNORM_SRGB},
 594       {PIPE_FORMAT_DXT5_SRGBA,             BC3_UNORM_SRGB},
 595
 596       {PIPE_FORMAT_RGTC1_UNORM,            BC4_UNORM},
 597       {PIPE_FORMAT_RGTC1_SNORM,            BC4_SNORM},
 598       {PIPE_FORMAT_RGTC2_UNORM,            BC5_UNORM},
 599       {PIPE_FORMAT_RGTC2_SNORM,            BC5_SNORM},
 600
 601       {PIPE_FORMAT_L16A16_UNORM,           L16A16_UNORM},
 602       {PIPE_FORMAT_I16_UNORM,              I16_UNORM},
 603       {PIPE_FORMAT_L16_FLOAT,              L16_FLOAT},
 604       {PIPE_FORMAT_L16A16_FLOAT,           L16A16_FLOAT},
 605       {PIPE_FORMAT_I16_FLOAT,              I16_FLOAT},
 606       {PIPE_FORMAT_L32_FLOAT,              L32_FLOAT},
 607       {PIPE_FORMAT_L32A32_FLOAT,           L32A32_FLOAT},
 608       {PIPE_FORMAT_I32_FLOAT,              I32_FLOAT},
 609
 610       {PIPE_FORMAT_I8_UINT,                I8_UINT},
 611       {PIPE_FORMAT_L8_UINT,                L8_UINT},
 612       {PIPE_FORMAT_L8A8_UINT,              L8A8_UINT},
 613
 614       {PIPE_FORMAT_I8_SINT,                I8_SINT},
 615       {PIPE_FORMAT_L8_SINT,                L8_SINT},
 616       {PIPE_FORMAT_L8A8_SINT,              L8A8_SINT},
 617
 618       */
 619    };
 620
 621    auto it = mesa2swr.find(format);
 622    if (it == mesa2swr.end())
 623       return (SWR_FORMAT)-1;
 624    else
 625       return it->second;
 626 }
 627
 628 static boolean
 629 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
 630 {
 631    struct sw_winsys *winsys = screen->winsys;
 632    struct sw_displaytarget *dt;
 633
 634    const unsigned width = align(res->swr.width, res->swr.halign);
 635    const unsigned height = align(res->swr.height, res->swr.valign);
 636
 637    UINT stride;
 638    dt = winsys->displaytarget_create(winsys,
 639                                      res->base.bind,
 640                                      res->base.format,
 641                                      width, height,
 642                                      64, NULL,
 643                                      &stride);
 644
 645    if (dt == NULL)
 646       return FALSE;
 647
 648    void *map = winsys->displaytarget_map(winsys, dt, 0);
 649
 650    res->display_target = dt;
 651    res->swr.pBaseAddress = (uint8_t*) map;
 652
 653    /* Clear the display target surface */
 654    if (map)
 655       memset(map, 0, height * stride);
 656
 657    winsys->displaytarget_unmap(winsys, dt);
 658
 659    return TRUE;
 660 }
 661
 662 static bool
 663 swr_texture_layout(struct swr_screen *screen,
 664                    struct swr_resource *res,
 665                    boolean allocate)
 666 {
 667    struct pipe_resource *pt = &res->base;
 668
 669    pipe_format fmt = pt->format;
 670    const struct util_format_description *desc = util_format_description(fmt);
 671
 672    res->has_depth = util_format_has_depth(desc);
 673    res->has_stencil = util_format_has_stencil(desc);
 674
 675    if (res->has_stencil && !res->has_depth)
 676       fmt = PIPE_FORMAT_R8_UINT;
 677
 678    /* We always use the SWR layout. For 2D and 3D textures this looks like:
 679     *
 680     * |<------- pitch ------->|
 681     * +=======================+-------
 682     * |Array 0                |   ^
 683     * |                       |   |
 684     * |        Level 0        |   |
 685     * |                       |   |
 686     * |                       | qpitch
 687     * +-----------+-----------+   |
 688     * |           | L2L2L2L2  |   |
 689     * |  Level 1  | L3L3      |   |
 690     * |           | L4        |   v
 691     * +===========+===========+-------
 692     * |Array 1                |
 693     * |                       |
 694     * |        Level 0        |
 695     * |                       |
 696     * |                       |
 697     * +-----------+-----------+
 698     * |           | L2L2L2L2  |
 699     * |  Level 1  | L3L3      |
 700     * |           | L4        |
 701     * +===========+===========+
 702     *
 703     * The overall width in bytes is known as the pitch, while the overall
 704     * height in rows is the qpitch. Array slices are laid out logically below
 705     * one another, qpitch rows apart. For 3D surfaces, the "level" values are
 706     * just invalid for the higher array numbers (since depth is also
 707     * minified). 1D and 1D array surfaces are stored effectively the same way,
 708     * except that pitch never plays into it. All the levels are logically
 709     * adjacent to each other on the X axis. The qpitch becomes the number of
 710     * elements between array slices, while the pitch is unused.
 711     *
 712     * Each level's sizes are subject to the valign and halign settings of the
 713     * surface. For compressed formats that swr is unaware of, we will use an
 714     * appropriately-sized uncompressed format, and scale the widths/heights.
 715     *
 716     * This surface is stored inside res->swr. For depth/stencil textures,
 717     * res->secondary will have an identically-laid-out but R8_UINT-formatted
 718     * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
 719     * texels, to simplify map/unmap logic which copies the stencil values
 720     * in/out.
 721     */
 722
 723    res->swr.width = pt->width0;
 724    res->swr.height = pt->height0;
 725    res->swr.type = swr_convert_target_type(pt->target);
 726    res->swr.tileMode = SWR_TILE_NONE;
 727    res->swr.format = mesa_to_swr_format(fmt);
 728    res->swr.numSamples = std::max(1u, pt->nr_samples);
 729
 730    if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
 731       res->swr.halign = KNOB_MACROTILE_X_DIM;
 732       res->swr.valign = KNOB_MACROTILE_Y_DIM;
 733
 734       /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
 735        * surface sample count. */
 736       if (screen->msaa_force_enable) {
 737          res->swr.numSamples = screen->msaa_max_count;
 738          fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
 739                  res->swr.numSamples);
 740       }
 741    } else {
 742       res->swr.halign = 1;
 743       res->swr.valign = 1;
 744    }
 745
 746    unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
 747    unsigned width = align(pt->width0, halign);
 748    if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
 749       for (int level = 1; level <= pt->last_level; level++)
 750          width += align(u_minify(pt->width0, level), halign);
 751       res->swr.pitch = util_format_get_blocksize(fmt);
 752       res->swr.qpitch = util_format_get_nblocksx(fmt, width);
 753    } else {
 754       // The pitch is the overall width of the texture in bytes. Most of the
 755       // time this is the pitch of level 0 since all the other levels fit
 756       // underneath it. However in some degenerate situations, the width of
 757       // level1 + level2 may be larger. In that case, we use those
 758       // widths. This can happen if, e.g. halign is 32, and the width of level
 759       // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
 760       // be 32 each, adding up to 64.
 761       unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
 762       if (pt->last_level > 1) {
 763          width = std::max<uint32_t>(
 764                width,
 765                align(u_minify(pt->width0, 1), halign) +
 766                align(u_minify(pt->width0, 2), halign));
 767       }
 768       res->swr.pitch = util_format_get_stride(fmt, width);
 769
 770       // The qpitch is controlled by either the height of the second LOD, or
 771       // the combination of all the later LODs.
 772       unsigned height = align(pt->height0, valign);
 773       if (pt->last_level == 1) {
 774          height += align(u_minify(pt->height0, 1), valign);
 775       } else if (pt->last_level > 1) {
 776          unsigned level1 = align(u_minify(pt->height0, 1), valign);
 777          unsigned level2 = 0;
 778          for (int level = 2; level <= pt->last_level; level++) {
 779             level2 += align(u_minify(pt->height0, level), valign);
 780          }
 781          height += std::max(level1, level2);
 782       }
 783       res->swr.qpitch = util_format_get_nblocksy(fmt, height);
 784    }
 785
 786    if (pt->target == PIPE_TEXTURE_3D)
 787       res->swr.depth = pt->depth0;
 788    else
 789       res->swr.depth = pt->array_size;
 790
 791    // Fix up swr format if necessary so that LOD offset computation works
 792    if (res->swr.format == (SWR_FORMAT)-1) {
 793       switch (util_format_get_blocksize(fmt)) {
 794       default:
 795          unreachable("Unexpected format block size");
 796       case 1: res->swr.format = R8_UINT; break;
 797       case 2: res->swr.format = R16_UINT; break;
 798       case 4: res->swr.format = R32_UINT; break;
 799       case 8:
 800          if (util_format_is_compressed(fmt))
 801             res->swr.format = BC4_UNORM;
 802          else
 803             res->swr.format = R32G32_UINT;
 804          break;
 805       case 16:
 806          if (util_format_is_compressed(fmt))
 807             res->swr.format = BC5_UNORM;
 808          else
 809             res->swr.format = R32G32B32A32_UINT;
 810          break;
 811       }
 812    }
 813
 814    for (int level = 0; level <= pt->last_level; level++) {
 815       res->mip_offsets[level] =
 816          ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
 817    }
 818
 819    size_t total_size = res->swr.depth * res->swr.qpitch * res->swr.pitch *
 820                        res->swr.numSamples;
 821    if (total_size > SWR_MAX_TEXTURE_SIZE)
 822       return false;
 823
 824    if (allocate) {
 825       res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
 826
 827       if (res->has_depth && res->has_stencil) {
 828          res->secondary = res->swr;
 829          res->secondary.format = R8_UINT;
 830          res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
 831
 832          for (int level = 0; level <= pt->last_level; level++) {
 833             res->secondary_mip_offsets[level] =
 834                ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
 835          }
 836
 837          total_size = res->secondary.depth * res->secondary.qpitch *
 838                       res->secondary.pitch * res->secondary.numSamples;
 839
 840          res->secondary.pBaseAddress = (uint8_t *) AlignedMalloc(total_size,
 841                                                                  64);
 842       }
 843    }
 844
 845    return true;
 846 }
 847
 848 static boolean
 849 swr_can_create_resource(struct pipe_screen *screen,
 850                         const struct pipe_resource *templat)
 851 {
 852    struct swr_resource res;
 853    memset(&res, 0, sizeof(res));
 854    res.base = *templat;
 855    return swr_texture_layout(swr_screen(screen), &res, false);
 856 }
 857
 858 /* Helper function that conditionally creates a single-sample resolve resource
 859  * and attaches it to main multisample resource. */
 860 static boolean
 861 swr_create_resolve_resource(struct pipe_screen *_screen,
 862                             struct swr_resource *msaa_res)
 863 {
 864    struct swr_screen *screen = swr_screen(_screen);
 865
 866    /* If resource is multisample, create a single-sample resolve resource */
 867    if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
 868             !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
 869
 870       /* Create a single-sample copy of the resource.  Copy the original
 871        * resource parameters and set flag to prevent recursion when re-calling
 872        * resource_create */
 873       struct pipe_resource alt_template = msaa_res->base;
 874       alt_template.nr_samples = 0;
 875       alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
 876
 877       /* Note: Display_target is a special single-sample resource, only the
 878        * display_target has been created already. */
 879       if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 880                | PIPE_BIND_SHARED)) {
 881          /* Allocate the multisample buffers. */
 882          if (!swr_texture_layout(screen, msaa_res, true))
 883             return false;
 884
 885          /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
 886           * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
 887          alt_template.bind = PIPE_BIND_RENDER_TARGET;
 888       }
 889
 890       /* Allocate single-sample resolve surface */
 891       struct pipe_resource *alt;
 892       alt = _screen->resource_create(_screen, &alt_template);
 893       if (!alt)
 894          return false;
 895
 896       /* Attach it to the multisample resource */
 897       msaa_res->resolve_target = alt;
 898
 899       /* Hang resolve surface state off the multisample surface state to so
 900        * StoreTiles knows where to resolve the surface. */
 901       msaa_res->swr.pAuxBaseAddress =  (uint8_t *)&swr_resource(alt)->swr;
 902    }
 903
 904    return true; /* success */
 905 }
 906
 907 static struct pipe_resource *
 908 swr_resource_create(struct pipe_screen *_screen,
 909                     const struct pipe_resource *templat)
 910 {
 911    struct swr_screen *screen = swr_screen(_screen);
 912    struct swr_resource *res = CALLOC_STRUCT(swr_resource);
 913    if (!res)
 914       return NULL;
 915
 916    res->base = *templat;
 917    pipe_reference_init(&res->base.reference, 1);
 918    res->base.screen = &screen->base;
 919
 920    if (swr_resource_is_texture(&res->base)) {
 921       if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 922                             | PIPE_BIND_SHARED)) {
 923          /* displayable surface
 924           * first call swr_texture_layout without allocating to finish
 925           * filling out the SWR_SURFACE_STATE in res */
 926          swr_texture_layout(screen, res, false);
 927          if (!swr_displaytarget_layout(screen, res))
 928             goto fail;
 929       } else {
 930          /* texture map */
 931          if (!swr_texture_layout(screen, res, true))
 932             goto fail;
 933       }
 934
 935       /* If resource was multisample, create resolve resource and attach
 936        * it to multisample resource. */
 937       if (!swr_create_resolve_resource(_screen, res))
 938             goto fail;
 939
 940    } else {
 941       /* other data (vertex buffer, const buffer, etc) */
 942       assert(util_format_get_blocksize(templat->format) == 1);
 943       assert(templat->height0 == 1);
 944       assert(templat->depth0 == 1);
 945       assert(templat->last_level == 0);
 946
 947       /* Easiest to just call swr_texture_layout, as it sets up
 948        * SWR_SURFACE_STATE in res */
 949       if (!swr_texture_layout(screen, res, true))
 950          goto fail;
 951    }
 952
 953    return &res->base;
 954
 955 fail:
 956    FREE(res);
 957    return NULL;
 958 }
 959
 960 static void
 961 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
 962 {
 963    struct swr_screen *screen = swr_screen(p_screen);
 964    struct swr_resource *spr = swr_resource(pt);
 965
 966    if (spr->display_target) {
 967       /* If resource is display target, winsys manages the buffer and will
 968        * free it on displaytarget_destroy. */
 969       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 970
 971       struct sw_winsys *winsys = screen->winsys;
 972       winsys->displaytarget_destroy(winsys, spr->display_target);
 973
 974       if (spr->swr.numSamples > 1) {
 975          /* Free an attached resolve resource */
 976          struct swr_resource *alt = swr_resource(spr->resolve_target);
 977          swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true);
 978
 979          /* Free multisample buffer */
 980          swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
 981       }
 982    } else {
 983       /* For regular resources, defer deletion */
 984       swr_resource_unused(pt);
 985
 986       if (spr->swr.numSamples > 1) {
 987          /* Free an attached resolve resource */
 988          struct swr_resource *alt = swr_resource(spr->resolve_target);
 989          swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true);
 990       }
 991
 992       swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
 993       swr_fence_work_free(screen->flush_fence,
 994                           spr->secondary.pBaseAddress, true);
 995
 996       /* If work queue grows too large, submit a fence to force queue to
 997        * drain.  This is mainly to decrease the amount of memory used by the
 998        * piglit streaming-texture-leak test */
 999       if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1000          swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1001    }
1002
1003    FREE(spr);
1004 }
1005
1006
1007 static void
1008 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1009                       struct pipe_resource *resource,
1010                       unsigned level,
1011                       unsigned layer,
1012                       void *context_private,
1013                       struct pipe_box *sub_box)
1014 {
1015    struct swr_screen *screen = swr_screen(p_screen);
1016    struct sw_winsys *winsys = screen->winsys;
1017    struct swr_resource *spr = swr_resource(resource);
1018    struct pipe_context *pipe = screen->pipe;
1019
1020    if (pipe) {
1021       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1022       swr_resource_unused(resource);
1023       SwrEndFrame(swr_context(pipe)->swrContext);
1024    }
1025
1026    /* Multisample resolved into resolve_target at flush with store_resource */
1027    if (pipe && spr->swr.numSamples > 1) {
1028       struct pipe_resource *resolve_target = spr->resolve_target;
1029
1030       /* Once resolved, copy into display target */
1031       SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1032
1033       void *map = winsys->displaytarget_map(winsys, spr->display_target,
1034                                             PIPE_TRANSFER_WRITE);
1035       memcpy(map, resolve->pBaseAddress, resolve->pitch * resolve->height);
1036       winsys->displaytarget_unmap(winsys, spr->display_target);
1037    }
1038
1039    debug_assert(spr->display_target);
1040    if (spr->display_target)
1041       winsys->displaytarget_display(
1042          winsys, spr->display_target, context_private, sub_box);
1043 }
1044
1045
1046 static void
1047 swr_destroy_screen(struct pipe_screen *p_screen)
1048 {
1049    struct swr_screen *screen = swr_screen(p_screen);
1050    struct sw_winsys *winsys = screen->winsys;
1051
1052    fprintf(stderr, "SWR destroy screen!\n");
1053
1054    swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1055    swr_fence_reference(p_screen, &screen->flush_fence, NULL);
1056
1057    JitDestroyContext(screen->hJitMgr);
1058
1059    if (winsys->destroy)
1060       winsys->destroy(winsys);
1061
1062    FREE(screen);
1063 }
1064
1065 PUBLIC
1066 struct pipe_screen *
1067 swr_create_screen_internal(struct sw_winsys *winsys)
1068 {
1069    struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1070
1071    if (!screen)
1072       return NULL;
1073
1074    if (!lp_build_init()) {
1075       FREE(screen);
1076       return NULL;
1077    }
1078
1079    screen->winsys = winsys;
1080    screen->base.get_name = swr_get_name;
1081    screen->base.get_vendor = swr_get_vendor;
1082    screen->base.is_format_supported = swr_is_format_supported;
1083    screen->base.context_create = swr_create_context;
1084    screen->base.can_create_resource = swr_can_create_resource;
1085
1086    screen->base.destroy = swr_destroy_screen;
1087    screen->base.get_param = swr_get_param;
1088    screen->base.get_shader_param = swr_get_shader_param;
1089    screen->base.get_paramf = swr_get_paramf;
1090
1091    screen->base.resource_create = swr_resource_create;
1092    screen->base.resource_destroy = swr_resource_destroy;
1093
1094    screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1095
1096    screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
1097
1098    swr_fence_init(&screen->base);
1099
1100    util_format_s3tc_init();
1101
1102    /* XXX msaa under development, disable by default for now */
1103    screen->msaa_max_count = 0; /* was SWR_MAX_NUM_MULTISAMPLES; */
1104
1105    /* validate env override values, within range and power of 2 */
1106    int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 0);
1107    if (msaa_max_count) {
1108       if ((msaa_max_count < 0) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1109             || !util_is_power_of_two(msaa_max_count)) {
1110          fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1111          fprintf(stderr, "must be power of 2 between 1 and %d" \
1112                          " (or 0 to disable msaa)\n",
1113                SWR_MAX_NUM_MULTISAMPLES);
1114          msaa_max_count = 0;
1115       }
1116
1117       fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1118       if (!msaa_max_count)
1119          fprintf(stderr, "(msaa disabled)\n");
1120
1121       screen->msaa_max_count = msaa_max_count;
1122    }
1123
1124    screen->msaa_force_enable = debug_get_bool_option(
1125          "SWR_MSAA_FORCE_ENABLE", false);
1126    if (screen->msaa_force_enable)
1127       fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1128
1129    return &screen->base;
1130 }
1131