src/gallium/drivers/swr/swr_screen.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "swr_context.h"
  25 #include "swr_public.h"
  26 #include "swr_screen.h"
  27 #include "swr_resource.h"
  28 #include "swr_fence.h"
  29 #include "gen_knobs.h"
  30
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_defines.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_format.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_cpu_detect.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39
  40 #include "state_tracker/sw_winsys.h"
  41
  42 #include "jit_api.h"
  43
  44 #include "memory/TilingFunctions.h"
  45
  46 #include <stdio.h>
  47 #include <map>
  48
  49 /* MSVC case instensitive compare */
  50 #if defined(PIPE_CC_MSVC)
  51    #define strcasecmp lstrcmpiA
  52 #endif
  53
  54 /*
  55  * Max texture sizes
  56  * XXX Check max texture size values against core and sampler.
  57  */
  58 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
  59 #define SWR_MAX_TEXTURE_2D_LEVELS 14  /* 8K x 8K for now */
  60 #define SWR_MAX_TEXTURE_3D_LEVELS 12  /* 2K x 2K x 2K for now */
  61 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14  /* 8K x 8K for now */
  62 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
  63
  64 static const char *
  65 swr_get_name(struct pipe_screen *screen)
  66 {
  67    static char buf[100];
  68    util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
  69                  HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
  70                  lp_native_vector_width );
  71    return buf;
  72 }
  73
  74 static const char *
  75 swr_get_vendor(struct pipe_screen *screen)
  76 {
  77    return "Intel Corporation";
  78 }
  79
  80 static boolean
  81 swr_is_format_supported(struct pipe_screen *screen,
  82                         enum pipe_format format,
  83                         enum pipe_texture_target target,
  84                         unsigned sample_count,
  85                         unsigned bind)
  86 {
  87    struct sw_winsys *winsys = swr_screen(screen)->winsys;
  88    const struct util_format_description *format_desc;
  89
  90    assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
  91           || target == PIPE_TEXTURE_1D_ARRAY
  92           || target == PIPE_TEXTURE_2D
  93           || target == PIPE_TEXTURE_2D_ARRAY
  94           || target == PIPE_TEXTURE_RECT
  95           || target == PIPE_TEXTURE_3D
  96           || target == PIPE_TEXTURE_CUBE
  97           || target == PIPE_TEXTURE_CUBE_ARRAY);
  98
  99    format_desc = util_format_description(format);
 100    if (!format_desc)
 101       return FALSE;
 102
 103    if (sample_count > 1)
 104       return FALSE;
 105
 106    if (bind
 107        & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) {
 108       if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
 109          return FALSE;
 110    }
 111
 112    if (bind & PIPE_BIND_RENDER_TARGET) {
 113       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 114          return FALSE;
 115
 116       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 117          return FALSE;
 118
 119       /*
 120        * Although possible, it is unnatural to render into compressed or YUV
 121        * surfaces. So disable these here to avoid going into weird paths
 122        * inside the state trackers.
 123        */
 124       if (format_desc->block.width != 1 || format_desc->block.height != 1)
 125          return FALSE;
 126    }
 127
 128    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 129       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 130          return FALSE;
 131
 132       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 133          return FALSE;
 134    }
 135
 136    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
 137        format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
 138       return FALSE;
 139    }
 140
 141    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
 142        format != PIPE_FORMAT_ETC1_RGB8) {
 143       return FALSE;
 144    }
 145
 146    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 147       return util_format_s3tc_enabled;
 148    }
 149
 150    return TRUE;
 151 }
 152
 153 static int
 154 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
 155 {
 156    switch (param) {
 157       /* limits */
 158    case PIPE_CAP_MAX_RENDER_TARGETS:
 159       return PIPE_MAX_COLOR_BUFS;
 160    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 161       return SWR_MAX_TEXTURE_2D_LEVELS;
 162    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 163       return SWR_MAX_TEXTURE_3D_LEVELS;
 164    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 165       return SWR_MAX_TEXTURE_CUBE_LEVELS;
 166    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 167       return MAX_SO_STREAMS;
 168    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 169    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 170       return MAX_ATTRIBUTES * 4;
 171    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 172    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 173       return 1024;
 174    case PIPE_CAP_MAX_VERTEX_STREAMS:
 175       return 1;
 176    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 177       return 2048;
 178    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 179       return SWR_MAX_TEXTURE_ARRAY_LAYERS;
 180    case PIPE_CAP_MIN_TEXEL_OFFSET:
 181       return -8;
 182    case PIPE_CAP_MAX_TEXEL_OFFSET:
 183       return 7;
 184    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 185       return 330;
 186    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 187       return 16;
 188    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 189       return 64;
 190    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 191       return 65536;
 192    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 193       return 0;
 194    case PIPE_CAP_MAX_VIEWPORTS:
 195       return 1;
 196    case PIPE_CAP_ENDIANNESS:
 197       return PIPE_ENDIAN_NATIVE;
 198    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 199    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 200       return 0;
 201
 202       /* supported features */
 203    case PIPE_CAP_NPOT_TEXTURES:
 204    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 205    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 206    case PIPE_CAP_TWO_SIDED_STENCIL:
 207    case PIPE_CAP_SM3:
 208    case PIPE_CAP_POINT_SPRITE:
 209    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 210    case PIPE_CAP_OCCLUSION_QUERY:
 211    case PIPE_CAP_QUERY_TIME_ELAPSED:
 212    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 213    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 214    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 215    case PIPE_CAP_TEXTURE_SWIZZLE:
 216    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 217    case PIPE_CAP_INDEP_BLEND_ENABLE:
 218    case PIPE_CAP_INDEP_BLEND_FUNC:
 219    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 220    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 221    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 222    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 223    case PIPE_CAP_PRIMITIVE_RESTART:
 224    case PIPE_CAP_TGSI_INSTANCEID:
 225    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 226    case PIPE_CAP_START_INSTANCE:
 227    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 228    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 229    case PIPE_CAP_CONDITIONAL_RENDER:
 230    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 231    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 232    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 233    case PIPE_CAP_USER_VERTEX_BUFFERS:
 234    case PIPE_CAP_USER_INDEX_BUFFERS:
 235    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 236    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 237    case PIPE_CAP_QUERY_TIMESTAMP:
 238    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 239    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 240    case PIPE_CAP_FAKE_SW_MSAA:
 241    case PIPE_CAP_DRAW_INDIRECT:
 242    case PIPE_CAP_UMA:
 243    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 244    case PIPE_CAP_CLIP_HALFZ:
 245    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 246    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 247    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 248    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 249    case PIPE_CAP_CULL_DISTANCE:
 250    case PIPE_CAP_CUBE_MAP_ARRAY:
 251       return 1;
 252
 253       /* unsupported features */
 254    case PIPE_CAP_ANISOTROPIC_FILTER:
 255    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 256    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 257    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 258    case PIPE_CAP_TEXTURE_BARRIER:
 259    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 260    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 261    case PIPE_CAP_COMPUTE:
 262    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 263    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 264    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 265    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 266    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 267    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 268    case PIPE_CAP_TGSI_TEXCOORD:
 269    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 270    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 271    case PIPE_CAP_TEXTURE_GATHER_SM5:
 272    case PIPE_CAP_TEXTURE_QUERY_LOD:
 273    case PIPE_CAP_SAMPLE_SHADING:
 274    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 275    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 276    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 277    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 278    case PIPE_CAP_VERTEXID_NOBASE:
 279    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 280    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 281    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 282    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 283    case PIPE_CAP_TGSI_TXQS:
 284    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 285    case PIPE_CAP_SHAREABLE_SHADERS:
 286    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 287    case PIPE_CAP_CLEAR_TEXTURE:
 288    case PIPE_CAP_DRAW_PARAMETERS:
 289    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 290    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 291    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 292    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 293    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 294    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 295    case PIPE_CAP_INVALIDATE_BUFFER:
 296    case PIPE_CAP_GENERATE_MIPMAP:
 297    case PIPE_CAP_STRING_MARKER:
 298    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 299    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 300    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 301    case PIPE_CAP_QUERY_MEMORY_INFO:
 302    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 303    case PIPE_CAP_PCI_GROUP:
 304    case PIPE_CAP_PCI_BUS:
 305    case PIPE_CAP_PCI_DEVICE:
 306    case PIPE_CAP_PCI_FUNCTION:
 307    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 308    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 309    case PIPE_CAP_TGSI_VOTE:
 310    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 311    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 312    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 313    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 314    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 315    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 316    case PIPE_CAP_NATIVE_FENCE_FD:
 317    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 318       return 0;
 319
 320    case PIPE_CAP_VENDOR_ID:
 321       return 0xFFFFFFFF;
 322    case PIPE_CAP_DEVICE_ID:
 323       return 0xFFFFFFFF;
 324    case PIPE_CAP_ACCELERATED:
 325       return 0;
 326    case PIPE_CAP_VIDEO_MEMORY: {
 327       /* XXX: Do we want to return the full amount of system memory ? */
 328       uint64_t system_memory;
 329
 330       if (!os_get_total_physical_memory(&system_memory))
 331          return 0;
 332
 333       return (int)(system_memory >> 20);
 334    }
 335    }
 336
 337    /* should only get here on unhandled cases */
 338    debug_printf("Unexpected PIPE_CAP %d query\n", param);
 339    return 0;
 340 }
 341
 342 static int
 343 swr_get_shader_param(struct pipe_screen *screen,
 344                      unsigned shader,
 345                      enum pipe_shader_cap param)
 346 {
 347    if (shader == PIPE_SHADER_VERTEX || shader == PIPE_SHADER_FRAGMENT)
 348       return gallivm_get_shader_param(param);
 349
 350    // Todo: geometry, tesselation, compute
 351    return 0;
 352 }
 353
 354
 355 static float
 356 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 357 {
 358    switch (param) {
 359    case PIPE_CAPF_MAX_LINE_WIDTH:
 360    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 361    case PIPE_CAPF_MAX_POINT_WIDTH:
 362       return 255.0; /* arbitrary */
 363    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 364       return 0.0;
 365    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 366       return 0.0;
 367    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 368       return 16.0; /* arbitrary */
 369    case PIPE_CAPF_GUARD_BAND_LEFT:
 370    case PIPE_CAPF_GUARD_BAND_TOP:
 371    case PIPE_CAPF_GUARD_BAND_RIGHT:
 372    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 373       return 0.0;
 374    }
 375    /* should only get here on unhandled cases */
 376    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 377    return 0.0;
 378 }
 379
 380 SWR_FORMAT
 381 mesa_to_swr_format(enum pipe_format format)
 382 {
 383    static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
 384       /* depth / stencil */
 385       {PIPE_FORMAT_Z16_UNORM,              R16_UNORM}, // z
 386       {PIPE_FORMAT_Z32_FLOAT,              R32_FLOAT}, // z
 387       {PIPE_FORMAT_Z24_UNORM_S8_UINT,      R24_UNORM_X8_TYPELESS}, // z
 388       {PIPE_FORMAT_Z24X8_UNORM,            R24_UNORM_X8_TYPELESS}, // z
 389       {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,   R32_FLOAT_X8X24_TYPELESS}, // z
 390
 391       /* alpha */
 392       {PIPE_FORMAT_A8_UNORM,               A8_UNORM},
 393       {PIPE_FORMAT_A16_UNORM,              A16_UNORM},
 394       {PIPE_FORMAT_A16_FLOAT,              A16_FLOAT},
 395       {PIPE_FORMAT_A32_FLOAT,              A32_FLOAT},
 396
 397       /* odd sizes, bgr */
 398       {PIPE_FORMAT_B5G6R5_UNORM,           B5G6R5_UNORM},
 399       {PIPE_FORMAT_B5G6R5_SRGB,            B5G6R5_UNORM_SRGB},
 400       {PIPE_FORMAT_B5G5R5A1_UNORM,         B5G5R5A1_UNORM},
 401       {PIPE_FORMAT_B5G5R5X1_UNORM,         B5G5R5X1_UNORM},
 402       {PIPE_FORMAT_B4G4R4A4_UNORM,         B4G4R4A4_UNORM},
 403       {PIPE_FORMAT_B8G8R8A8_UNORM,         B8G8R8A8_UNORM},
 404       {PIPE_FORMAT_B8G8R8A8_SRGB,          B8G8R8A8_UNORM_SRGB},
 405       {PIPE_FORMAT_B8G8R8X8_UNORM,         B8G8R8X8_UNORM},
 406       {PIPE_FORMAT_B8G8R8X8_SRGB,          B8G8R8X8_UNORM_SRGB},
 407
 408       /* rgb10a2 */
 409       {PIPE_FORMAT_R10G10B10A2_UNORM,      R10G10B10A2_UNORM},
 410       {PIPE_FORMAT_R10G10B10A2_SNORM,      R10G10B10A2_SNORM},
 411       {PIPE_FORMAT_R10G10B10A2_USCALED,    R10G10B10A2_USCALED},
 412       {PIPE_FORMAT_R10G10B10A2_SSCALED,    R10G10B10A2_SSCALED},
 413       {PIPE_FORMAT_R10G10B10A2_UINT,       R10G10B10A2_UINT},
 414
 415       /* rgb10x2 */
 416       {PIPE_FORMAT_R10G10B10X2_USCALED,    R10G10B10X2_USCALED},
 417
 418       /* bgr10a2 */
 419       {PIPE_FORMAT_B10G10R10A2_UNORM,      B10G10R10A2_UNORM},
 420       {PIPE_FORMAT_B10G10R10A2_SNORM,      B10G10R10A2_SNORM},
 421       {PIPE_FORMAT_B10G10R10A2_USCALED,    B10G10R10A2_USCALED},
 422       {PIPE_FORMAT_B10G10R10A2_SSCALED,    B10G10R10A2_SSCALED},
 423       {PIPE_FORMAT_B10G10R10A2_UINT,       B10G10R10A2_UINT},
 424
 425       /* bgr10x2 */
 426       {PIPE_FORMAT_B10G10R10X2_UNORM,      B10G10R10X2_UNORM},
 427
 428       /* r11g11b10 */
 429       {PIPE_FORMAT_R11G11B10_FLOAT,        R11G11B10_FLOAT},
 430
 431       /* 32 bits per component */
 432       {PIPE_FORMAT_R32_FLOAT,              R32_FLOAT},
 433       {PIPE_FORMAT_R32G32_FLOAT,           R32G32_FLOAT},
 434       {PIPE_FORMAT_R32G32B32_FLOAT,        R32G32B32_FLOAT},
 435       {PIPE_FORMAT_R32G32B32A32_FLOAT,     R32G32B32A32_FLOAT},
 436       {PIPE_FORMAT_R32G32B32X32_FLOAT,     R32G32B32X32_FLOAT},
 437
 438       {PIPE_FORMAT_R32_USCALED,            R32_USCALED},
 439       {PIPE_FORMAT_R32G32_USCALED,         R32G32_USCALED},
 440       {PIPE_FORMAT_R32G32B32_USCALED,      R32G32B32_USCALED},
 441       {PIPE_FORMAT_R32G32B32A32_USCALED,   R32G32B32A32_USCALED},
 442
 443       {PIPE_FORMAT_R32_SSCALED,            R32_SSCALED},
 444       {PIPE_FORMAT_R32G32_SSCALED,         R32G32_SSCALED},
 445       {PIPE_FORMAT_R32G32B32_SSCALED,      R32G32B32_SSCALED},
 446       {PIPE_FORMAT_R32G32B32A32_SSCALED,   R32G32B32A32_SSCALED},
 447
 448       {PIPE_FORMAT_R32_UINT,               R32_UINT},
 449       {PIPE_FORMAT_R32G32_UINT,            R32G32_UINT},
 450       {PIPE_FORMAT_R32G32B32_UINT,         R32G32B32_UINT},
 451       {PIPE_FORMAT_R32G32B32A32_UINT,      R32G32B32A32_UINT},
 452
 453       {PIPE_FORMAT_R32_SINT,               R32_SINT},
 454       {PIPE_FORMAT_R32G32_SINT,            R32G32_SINT},
 455       {PIPE_FORMAT_R32G32B32_SINT,         R32G32B32_SINT},
 456       {PIPE_FORMAT_R32G32B32A32_SINT,      R32G32B32A32_SINT},
 457
 458       /* 16 bits per component */
 459       {PIPE_FORMAT_R16_UNORM,              R16_UNORM},
 460       {PIPE_FORMAT_R16G16_UNORM,           R16G16_UNORM},
 461       {PIPE_FORMAT_R16G16B16_UNORM,        R16G16B16_UNORM},
 462       {PIPE_FORMAT_R16G16B16A16_UNORM,     R16G16B16A16_UNORM},
 463       {PIPE_FORMAT_R16G16B16X16_UNORM,     R16G16B16X16_UNORM},
 464
 465       {PIPE_FORMAT_R16_USCALED,            R16_USCALED},
 466       {PIPE_FORMAT_R16G16_USCALED,         R16G16_USCALED},
 467       {PIPE_FORMAT_R16G16B16_USCALED,      R16G16B16_USCALED},
 468       {PIPE_FORMAT_R16G16B16A16_USCALED,   R16G16B16A16_USCALED},
 469
 470       {PIPE_FORMAT_R16_SNORM,              R16_SNORM},
 471       {PIPE_FORMAT_R16G16_SNORM,           R16G16_SNORM},
 472       {PIPE_FORMAT_R16G16B16_SNORM,        R16G16B16_SNORM},
 473       {PIPE_FORMAT_R16G16B16A16_SNORM,     R16G16B16A16_SNORM},
 474
 475       {PIPE_FORMAT_R16_SSCALED,            R16_SSCALED},
 476       {PIPE_FORMAT_R16G16_SSCALED,         R16G16_SSCALED},
 477       {PIPE_FORMAT_R16G16B16_SSCALED,      R16G16B16_SSCALED},
 478       {PIPE_FORMAT_R16G16B16A16_SSCALED,   R16G16B16A16_SSCALED},
 479
 480       {PIPE_FORMAT_R16_UINT,               R16_UINT},
 481       {PIPE_FORMAT_R16G16_UINT,            R16G16_UINT},
 482       {PIPE_FORMAT_R16G16B16_UINT,         R16G16B16_UINT},
 483       {PIPE_FORMAT_R16G16B16A16_UINT,      R16G16B16A16_UINT},
 484
 485       {PIPE_FORMAT_R16_SINT,               R16_SINT},
 486       {PIPE_FORMAT_R16G16_SINT,            R16G16_SINT},
 487       {PIPE_FORMAT_R16G16B16_SINT,         R16G16B16_SINT},
 488       {PIPE_FORMAT_R16G16B16A16_SINT,      R16G16B16A16_SINT},
 489
 490       {PIPE_FORMAT_R16_FLOAT,              R16_FLOAT},
 491       {PIPE_FORMAT_R16G16_FLOAT,           R16G16_FLOAT},
 492       {PIPE_FORMAT_R16G16B16_FLOAT,        R16G16B16_FLOAT},
 493       {PIPE_FORMAT_R16G16B16A16_FLOAT,     R16G16B16A16_FLOAT},
 494       {PIPE_FORMAT_R16G16B16X16_FLOAT,     R16G16B16X16_FLOAT},
 495
 496       /* 8 bits per component */
 497       {PIPE_FORMAT_R8_UNORM,               R8_UNORM},
 498       {PIPE_FORMAT_R8G8_UNORM,             R8G8_UNORM},
 499       {PIPE_FORMAT_R8G8B8_UNORM,           R8G8B8_UNORM},
 500       {PIPE_FORMAT_R8G8B8_SRGB,            R8G8B8_UNORM_SRGB},
 501       {PIPE_FORMAT_R8G8B8A8_UNORM,         R8G8B8A8_UNORM},
 502       {PIPE_FORMAT_R8G8B8A8_SRGB,          R8G8B8A8_UNORM_SRGB},
 503       {PIPE_FORMAT_R8G8B8X8_UNORM,         R8G8B8X8_UNORM},
 504       {PIPE_FORMAT_R8G8B8X8_SRGB,          R8G8B8X8_UNORM_SRGB},
 505
 506       {PIPE_FORMAT_R8_USCALED,             R8_USCALED},
 507       {PIPE_FORMAT_R8G8_USCALED,           R8G8_USCALED},
 508       {PIPE_FORMAT_R8G8B8_USCALED,         R8G8B8_USCALED},
 509       {PIPE_FORMAT_R8G8B8A8_USCALED,       R8G8B8A8_USCALED},
 510
 511       {PIPE_FORMAT_R8_SNORM,               R8_SNORM},
 512       {PIPE_FORMAT_R8G8_SNORM,             R8G8_SNORM},
 513       {PIPE_FORMAT_R8G8B8_SNORM,           R8G8B8_SNORM},
 514       {PIPE_FORMAT_R8G8B8A8_SNORM,         R8G8B8A8_SNORM},
 515
 516       {PIPE_FORMAT_R8_SSCALED,             R8_SSCALED},
 517       {PIPE_FORMAT_R8G8_SSCALED,           R8G8_SSCALED},
 518       {PIPE_FORMAT_R8G8B8_SSCALED,         R8G8B8_SSCALED},
 519       {PIPE_FORMAT_R8G8B8A8_SSCALED,       R8G8B8A8_SSCALED},
 520
 521       {PIPE_FORMAT_R8_UINT,                R8_UINT},
 522       {PIPE_FORMAT_R8G8_UINT,              R8G8_UINT},
 523       {PIPE_FORMAT_R8G8B8_UINT,            R8G8B8_UINT},
 524       {PIPE_FORMAT_R8G8B8A8_UINT,          R8G8B8A8_UINT},
 525
 526       {PIPE_FORMAT_R8_SINT,                R8_SINT},
 527       {PIPE_FORMAT_R8G8_SINT,              R8G8_SINT},
 528       {PIPE_FORMAT_R8G8B8_SINT,            R8G8B8_SINT},
 529       {PIPE_FORMAT_R8G8B8A8_SINT,          R8G8B8A8_SINT},
 530
 531       /* These formats are valid for vertex data, but should not be used
 532        * for render targets.
 533        */
 534
 535       {PIPE_FORMAT_R32_FIXED,              R32_SFIXED},
 536       {PIPE_FORMAT_R32G32_FIXED,           R32G32_SFIXED},
 537       {PIPE_FORMAT_R32G32B32_FIXED,        R32G32B32_SFIXED},
 538       {PIPE_FORMAT_R32G32B32A32_FIXED,     R32G32B32A32_SFIXED},
 539
 540       {PIPE_FORMAT_R64_FLOAT,              R64_FLOAT},
 541       {PIPE_FORMAT_R64G64_FLOAT,           R64G64_FLOAT},
 542       {PIPE_FORMAT_R64G64B64_FLOAT,        R64G64B64_FLOAT},
 543       {PIPE_FORMAT_R64G64B64A64_FLOAT,     R64G64B64A64_FLOAT},
 544
 545       /* These formats have entries in SWR but don't have Load/StoreTile
 546        * implementations. That means these aren't renderable, and thus having
 547        * a mapping entry here is detrimental.
 548        */
 549       /*
 550
 551       {PIPE_FORMAT_L8_UNORM,               L8_UNORM},
 552       {PIPE_FORMAT_I8_UNORM,               I8_UNORM},
 553       {PIPE_FORMAT_L8A8_UNORM,             L8A8_UNORM},
 554       {PIPE_FORMAT_L16_UNORM,              L16_UNORM},
 555       {PIPE_FORMAT_UYVY,                   YCRCB_SWAPUVY},
 556
 557       {PIPE_FORMAT_L8_SRGB,                L8_UNORM_SRGB},
 558       {PIPE_FORMAT_L8A8_SRGB,              L8A8_UNORM_SRGB},
 559
 560       {PIPE_FORMAT_DXT1_RGBA,              BC1_UNORM},
 561       {PIPE_FORMAT_DXT3_RGBA,              BC2_UNORM},
 562       {PIPE_FORMAT_DXT5_RGBA,              BC3_UNORM},
 563
 564       {PIPE_FORMAT_DXT1_SRGBA,             BC1_UNORM_SRGB},
 565       {PIPE_FORMAT_DXT3_SRGBA,             BC2_UNORM_SRGB},
 566       {PIPE_FORMAT_DXT5_SRGBA,             BC3_UNORM_SRGB},
 567
 568       {PIPE_FORMAT_RGTC1_UNORM,            BC4_UNORM},
 569       {PIPE_FORMAT_RGTC1_SNORM,            BC4_SNORM},
 570       {PIPE_FORMAT_RGTC2_UNORM,            BC5_UNORM},
 571       {PIPE_FORMAT_RGTC2_SNORM,            BC5_SNORM},
 572
 573       {PIPE_FORMAT_L16A16_UNORM,           L16A16_UNORM},
 574       {PIPE_FORMAT_I16_UNORM,              I16_UNORM},
 575       {PIPE_FORMAT_L16_FLOAT,              L16_FLOAT},
 576       {PIPE_FORMAT_L16A16_FLOAT,           L16A16_FLOAT},
 577       {PIPE_FORMAT_I16_FLOAT,              I16_FLOAT},
 578       {PIPE_FORMAT_L32_FLOAT,              L32_FLOAT},
 579       {PIPE_FORMAT_L32A32_FLOAT,           L32A32_FLOAT},
 580       {PIPE_FORMAT_I32_FLOAT,              I32_FLOAT},
 581
 582       {PIPE_FORMAT_I8_UINT,                I8_UINT},
 583       {PIPE_FORMAT_L8_UINT,                L8_UINT},
 584       {PIPE_FORMAT_L8A8_UINT,              L8A8_UINT},
 585
 586       {PIPE_FORMAT_I8_SINT,                I8_SINT},
 587       {PIPE_FORMAT_L8_SINT,                L8_SINT},
 588       {PIPE_FORMAT_L8A8_SINT,              L8A8_SINT},
 589
 590       */
 591    };
 592
 593    auto it = mesa2swr.find(format);
 594    if (it == mesa2swr.end())
 595       return (SWR_FORMAT)-1;
 596    else
 597       return it->second;
 598 }
 599
 600 static boolean
 601 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
 602 {
 603    struct sw_winsys *winsys = screen->winsys;
 604    struct sw_displaytarget *dt;
 605
 606    const unsigned width = align(res->swr.width, res->swr.halign);
 607    const unsigned height = align(res->swr.height, res->swr.valign);
 608
 609    UINT stride;
 610    dt = winsys->displaytarget_create(winsys,
 611                                      res->base.bind,
 612                                      res->base.format,
 613                                      width, height,
 614                                      64, NULL,
 615                                      &stride);
 616
 617    if (dt == NULL)
 618       return FALSE;
 619
 620    void *map = winsys->displaytarget_map(winsys, dt, 0);
 621
 622    res->display_target = dt;
 623    res->swr.pBaseAddress = (uint8_t*) map;
 624
 625    /* Clear the display target surface */
 626    if (map)
 627       memset(map, 0, height * stride);
 628
 629    winsys->displaytarget_unmap(winsys, dt);
 630
 631    return TRUE;
 632 }
 633
 634 static bool
 635 swr_texture_layout(struct swr_screen *screen,
 636                    struct swr_resource *res,
 637                    boolean allocate)
 638 {
 639    struct pipe_resource *pt = &res->base;
 640
 641    pipe_format fmt = pt->format;
 642    const struct util_format_description *desc = util_format_description(fmt);
 643
 644    res->has_depth = util_format_has_depth(desc);
 645    res->has_stencil = util_format_has_stencil(desc);
 646
 647    if (res->has_stencil && !res->has_depth)
 648       fmt = PIPE_FORMAT_R8_UINT;
 649
 650    /* We always use the SWR layout. For 2D and 3D textures this looks like:
 651     *
 652     * |<------- pitch ------->|
 653     * +=======================+-------
 654     * |Array 0                |   ^
 655     * |                       |   |
 656     * |        Level 0        |   |
 657     * |                       |   |
 658     * |                       | qpitch
 659     * +-----------+-----------+   |
 660     * |           | L2L2L2L2  |   |
 661     * |  Level 1  | L3L3      |   |
 662     * |           | L4        |   v
 663     * +===========+===========+-------
 664     * |Array 1                |
 665     * |                       |
 666     * |        Level 0        |
 667     * |                       |
 668     * |                       |
 669     * +-----------+-----------+
 670     * |           | L2L2L2L2  |
 671     * |  Level 1  | L3L3      |
 672     * |           | L4        |
 673     * +===========+===========+
 674     *
 675     * The overall width in bytes is known as the pitch, while the overall
 676     * height in rows is the qpitch. Array slices are laid out logically below
 677     * one another, qpitch rows apart. For 3D surfaces, the "level" values are
 678     * just invalid for the higher array numbers (since depth is also
 679     * minified). 1D and 1D array surfaces are stored effectively the same way,
 680     * except that pitch never plays into it. All the levels are logically
 681     * adjacent to each other on the X axis. The qpitch becomes the number of
 682     * elements between array slices, while the pitch is unused.
 683     *
 684     * Each level's sizes are subject to the valign and halign settings of the
 685     * surface. For compressed formats that swr is unaware of, we will use an
 686     * appropriately-sized uncompressed format, and scale the widths/heights.
 687     *
 688     * This surface is stored inside res->swr. For depth/stencil textures,
 689     * res->secondary will have an identically-laid-out but R8_UINT-formatted
 690     * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
 691     * texels, to simplify map/unmap logic which copies the stencil values
 692     * in/out.
 693     */
 694
 695    res->swr.width = pt->width0;
 696    res->swr.height = pt->height0;
 697    res->swr.type = swr_convert_target_type(pt->target);
 698    res->swr.tileMode = SWR_TILE_NONE;
 699    res->swr.format = mesa_to_swr_format(fmt);
 700    res->swr.numSamples = std::max(1u, pt->nr_samples);
 701
 702    if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
 703       res->swr.halign = KNOB_MACROTILE_X_DIM;
 704       res->swr.valign = KNOB_MACROTILE_Y_DIM;
 705    } else {
 706       res->swr.halign = 1;
 707       res->swr.valign = 1;
 708    }
 709
 710    unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
 711    unsigned width = align(pt->width0, halign);
 712    if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
 713       for (int level = 1; level <= pt->last_level; level++)
 714          width += align(u_minify(pt->width0, level), halign);
 715       res->swr.pitch = util_format_get_blocksize(fmt);
 716       res->swr.qpitch = util_format_get_nblocksx(fmt, width);
 717    } else {
 718       // The pitch is the overall width of the texture in bytes. Most of the
 719       // time this is the pitch of level 0 since all the other levels fit
 720       // underneath it. However in some degenerate situations, the width of
 721       // level1 + level2 may be larger. In that case, we use those
 722       // widths. This can happen if, e.g. halign is 32, and the width of level
 723       // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
 724       // be 32 each, adding up to 64.
 725       unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
 726       if (pt->last_level > 1) {
 727          width = std::max<uint32_t>(
 728                width,
 729                align(u_minify(pt->width0, 1), halign) +
 730                align(u_minify(pt->width0, 2), halign));
 731       }
 732       res->swr.pitch = util_format_get_stride(fmt, width);
 733
 734       // The qpitch is controlled by either the height of the second LOD, or
 735       // the combination of all the later LODs.
 736       unsigned height = align(pt->height0, valign);
 737       if (pt->last_level == 1) {
 738          height += align(u_minify(pt->height0, 1), valign);
 739       } else if (pt->last_level > 1) {
 740          unsigned level1 = align(u_minify(pt->height0, 1), valign);
 741          unsigned level2 = 0;
 742          for (int level = 2; level <= pt->last_level; level++) {
 743             level2 += align(u_minify(pt->height0, level), valign);
 744          }
 745          height += std::max(level1, level2);
 746       }
 747       res->swr.qpitch = util_format_get_nblocksy(fmt, height);
 748    }
 749
 750    if (pt->target == PIPE_TEXTURE_3D)
 751       res->swr.depth = pt->depth0;
 752    else
 753       res->swr.depth = pt->array_size;
 754
 755    // Fix up swr format if necessary so that LOD offset computation works
 756    if (res->swr.format == (SWR_FORMAT)-1) {
 757       switch (util_format_get_blocksize(fmt)) {
 758       default:
 759          unreachable("Unexpected format block size");
 760       case 1: res->swr.format = R8_UINT; break;
 761       case 2: res->swr.format = R16_UINT; break;
 762       case 4: res->swr.format = R32_UINT; break;
 763       case 8:
 764          if (util_format_is_compressed(fmt))
 765             res->swr.format = BC4_UNORM;
 766          else
 767             res->swr.format = R32G32_UINT;
 768          break;
 769       case 16:
 770          if (util_format_is_compressed(fmt))
 771             res->swr.format = BC5_UNORM;
 772          else
 773             res->swr.format = R32G32B32A32_UINT;
 774          break;
 775       }
 776    }
 777
 778    for (int level = 0; level <= pt->last_level; level++) {
 779       res->mip_offsets[level] =
 780          ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
 781    }
 782
 783    size_t total_size =
 784       (size_t)res->swr.depth * res->swr.qpitch * res->swr.pitch;
 785    if (total_size > SWR_MAX_TEXTURE_SIZE)
 786       return false;
 787
 788    if (allocate) {
 789       res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
 790
 791       if (res->has_depth && res->has_stencil) {
 792          res->secondary = res->swr;
 793          res->secondary.format = R8_UINT;
 794          res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
 795
 796          for (int level = 0; level <= pt->last_level; level++) {
 797             res->secondary_mip_offsets[level] =
 798                ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
 799          }
 800
 801          res->secondary.pBaseAddress = (uint8_t *)AlignedMalloc(
 802             res->secondary.depth * res->secondary.qpitch *
 803             res->secondary.pitch, 64);
 804       }
 805    }
 806
 807    return true;
 808 }
 809
 810 static boolean
 811 swr_can_create_resource(struct pipe_screen *screen,
 812                         const struct pipe_resource *templat)
 813 {
 814    struct swr_resource res;
 815    memset(&res, 0, sizeof(res));
 816    res.base = *templat;
 817    return swr_texture_layout(swr_screen(screen), &res, false);
 818 }
 819
 820 static struct pipe_resource *
 821 swr_resource_create(struct pipe_screen *_screen,
 822                     const struct pipe_resource *templat)
 823 {
 824    struct swr_screen *screen = swr_screen(_screen);
 825    struct swr_resource *res = CALLOC_STRUCT(swr_resource);
 826    if (!res)
 827       return NULL;
 828
 829    res->base = *templat;
 830    pipe_reference_init(&res->base.reference, 1);
 831    res->base.screen = &screen->base;
 832
 833    if (swr_resource_is_texture(&res->base)) {
 834       if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 835                             | PIPE_BIND_SHARED)) {
 836          /* displayable surface
 837           * first call swr_texture_layout without allocating to finish
 838           * filling out the SWR_SURFAE_STATE in res */
 839          swr_texture_layout(screen, res, false);
 840          if (!swr_displaytarget_layout(screen, res))
 841             goto fail;
 842       } else {
 843          /* texture map */
 844          if (!swr_texture_layout(screen, res, true))
 845             goto fail;
 846       }
 847    } else {
 848       /* other data (vertex buffer, const buffer, etc) */
 849       assert(util_format_get_blocksize(templat->format) == 1);
 850       assert(templat->height0 == 1);
 851       assert(templat->depth0 == 1);
 852       assert(templat->last_level == 0);
 853
 854       /* Easiest to just call swr_texture_layout, as it sets up
 855        * SWR_SURFAE_STATE in res */
 856       if (!swr_texture_layout(screen, res, true))
 857          goto fail;
 858    }
 859
 860    return &res->base;
 861
 862 fail:
 863    FREE(res);
 864    return NULL;
 865 }
 866
 867 static void
 868 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
 869 {
 870    struct swr_screen *screen = swr_screen(p_screen);
 871    struct swr_resource *spr = swr_resource(pt);
 872    struct pipe_context *pipe = screen->pipe;
 873
 874    if (spr->display_target) {
 875       /* If resource is display target, winsys manages the buffer and will
 876        * free it on displaytarget_destroy. */
 877       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 878
 879       struct sw_winsys *winsys = screen->winsys;
 880       winsys->displaytarget_destroy(winsys, spr->display_target);
 881
 882    } else {
 883       /* For regular resources, if the resource is being used, defer deletion
 884        * (use aligned-free) */
 885       if (pipe && spr->status) {
 886          swr_resource_unused(pt);
 887          swr_fence_work_free(screen->flush_fence,
 888                              spr->swr.pBaseAddress, true);
 889          swr_fence_work_free(screen->flush_fence,
 890                              spr->secondary.pBaseAddress, true);
 891       } else {
 892          AlignedFree(spr->swr.pBaseAddress);
 893          AlignedFree(spr->secondary.pBaseAddress);
 894       }
 895    }
 896
 897    FREE(spr);
 898 }
 899
 900
 901 static void
 902 swr_flush_frontbuffer(struct pipe_screen *p_screen,
 903                       struct pipe_resource *resource,
 904                       unsigned level,
 905                       unsigned layer,
 906                       void *context_private,
 907                       struct pipe_box *sub_box)
 908 {
 909    struct swr_screen *screen = swr_screen(p_screen);
 910    struct sw_winsys *winsys = screen->winsys;
 911    struct swr_resource *spr = swr_resource(resource);
 912    struct pipe_context *pipe = screen->pipe;
 913
 914    if (pipe) {
 915       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 916       swr_resource_unused(resource);
 917       SwrEndFrame(swr_context(pipe)->swrContext);
 918    }
 919
 920    debug_assert(spr->display_target);
 921    if (spr->display_target)
 922       winsys->displaytarget_display(
 923          winsys, spr->display_target, context_private, sub_box);
 924 }
 925
 926
 927 static void
 928 swr_destroy_screen(struct pipe_screen *p_screen)
 929 {
 930    struct swr_screen *screen = swr_screen(p_screen);
 931    struct sw_winsys *winsys = screen->winsys;
 932
 933    fprintf(stderr, "SWR destroy screen!\n");
 934
 935    swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 936    swr_fence_reference(p_screen, &screen->flush_fence, NULL);
 937
 938    JitDestroyContext(screen->hJitMgr);
 939
 940    if (winsys->destroy)
 941       winsys->destroy(winsys);
 942
 943    FREE(screen);
 944 }
 945
 946 PUBLIC
 947 struct pipe_screen *
 948 swr_create_screen_internal(struct sw_winsys *winsys)
 949 {
 950    struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
 951
 952    if (!screen)
 953       return NULL;
 954
 955    if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
 956       g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152);
 957    }
 958
 959    if (!lp_build_init()) {
 960       FREE(screen);
 961       return NULL;
 962    }
 963
 964    screen->winsys = winsys;
 965    screen->base.get_name = swr_get_name;
 966    screen->base.get_vendor = swr_get_vendor;
 967    screen->base.is_format_supported = swr_is_format_supported;
 968    screen->base.context_create = swr_create_context;
 969    screen->base.can_create_resource = swr_can_create_resource;
 970
 971    screen->base.destroy = swr_destroy_screen;
 972    screen->base.get_param = swr_get_param;
 973    screen->base.get_shader_param = swr_get_shader_param;
 974    screen->base.get_paramf = swr_get_paramf;
 975
 976    screen->base.resource_create = swr_resource_create;
 977    screen->base.resource_destroy = swr_resource_destroy;
 978
 979    screen->base.flush_frontbuffer = swr_flush_frontbuffer;
 980
 981    screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
 982
 983    swr_fence_init(&screen->base);
 984
 985    util_format_s3tc_init();
 986
 987    return &screen->base;
 988 }
 989