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gallium: remove PIPE_CAP_TWO_SIDED_STENCIL
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned bind)
89 {
90 struct swr_screen *screen = swr_screen(_screen);
91 struct sw_winsys *winsys = screen->winsys;
92 const struct util_format_description *format_desc;
93
94 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
95 || target == PIPE_TEXTURE_1D_ARRAY
96 || target == PIPE_TEXTURE_2D
97 || target == PIPE_TEXTURE_2D_ARRAY
98 || target == PIPE_TEXTURE_RECT
99 || target == PIPE_TEXTURE_3D
100 || target == PIPE_TEXTURE_CUBE
101 || target == PIPE_TEXTURE_CUBE_ARRAY);
102
103 format_desc = util_format_description(format);
104 if (!format_desc)
105 return FALSE;
106
107 if ((sample_count > screen->msaa_max_count)
108 || !util_is_power_of_two(sample_count))
109 return FALSE;
110
111 if (bind & PIPE_BIND_DISPLAY_TARGET) {
112 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
113 return FALSE;
114 }
115
116 if (bind & PIPE_BIND_RENDER_TARGET) {
117 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
118 return FALSE;
119
120 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
121 return FALSE;
122
123 /*
124 * Although possible, it is unnatural to render into compressed or YUV
125 * surfaces. So disable these here to avoid going into weird paths
126 * inside the state trackers.
127 */
128 if (format_desc->block.width != 1 || format_desc->block.height != 1)
129 return FALSE;
130 }
131
132 if (bind & PIPE_BIND_DEPTH_STENCIL) {
133 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
134 return FALSE;
135
136 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
137 return FALSE;
138 }
139
140 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
141 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
142 return FALSE;
143 }
144
145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
146 format != PIPE_FORMAT_ETC1_RGB8) {
147 return FALSE;
148 }
149
150 return TRUE;
151 }
152
153 static int
154 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
155 {
156 switch (param) {
157 /* limits */
158 case PIPE_CAP_MAX_RENDER_TARGETS:
159 return PIPE_MAX_COLOR_BUFS;
160 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
161 return SWR_MAX_TEXTURE_2D_LEVELS;
162 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
163 return SWR_MAX_TEXTURE_3D_LEVELS;
164 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
165 return SWR_MAX_TEXTURE_CUBE_LEVELS;
166 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
167 return MAX_SO_STREAMS;
168 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
169 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
170 return MAX_ATTRIBUTES * 4;
171 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
172 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
173 return 1024;
174 case PIPE_CAP_MAX_VERTEX_STREAMS:
175 return 1;
176 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
177 return 2048;
178 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
179 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
180 case PIPE_CAP_MIN_TEXEL_OFFSET:
181 return -8;
182 case PIPE_CAP_MAX_TEXEL_OFFSET:
183 return 7;
184 case PIPE_CAP_GLSL_FEATURE_LEVEL:
185 return 330;
186 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
187 return 16;
188 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
189 return 64;
190 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
191 return 65536;
192 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
193 return 0;
194 case PIPE_CAP_MAX_VIEWPORTS:
195 return 1;
196 case PIPE_CAP_ENDIANNESS:
197 return PIPE_ENDIAN_NATIVE;
198 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
199 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
200 return 0;
201
202 /* supported features */
203 case PIPE_CAP_NPOT_TEXTURES:
204 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
205 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
206 case PIPE_CAP_SM3:
207 case PIPE_CAP_POINT_SPRITE:
208 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
209 case PIPE_CAP_OCCLUSION_QUERY:
210 case PIPE_CAP_QUERY_TIME_ELAPSED:
211 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
212 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
213 case PIPE_CAP_TEXTURE_SHADOW_MAP:
214 case PIPE_CAP_TEXTURE_SWIZZLE:
215 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
216 case PIPE_CAP_INDEP_BLEND_ENABLE:
217 case PIPE_CAP_INDEP_BLEND_FUNC:
218 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
219 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
220 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
221 case PIPE_CAP_DEPTH_CLIP_DISABLE:
222 case PIPE_CAP_PRIMITIVE_RESTART:
223 case PIPE_CAP_TGSI_INSTANCEID:
224 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
225 case PIPE_CAP_START_INSTANCE:
226 case PIPE_CAP_SEAMLESS_CUBE_MAP:
227 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
228 case PIPE_CAP_CONDITIONAL_RENDER:
229 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
230 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
231 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
232 case PIPE_CAP_USER_VERTEX_BUFFERS:
233 case PIPE_CAP_USER_CONSTANT_BUFFERS:
234 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
235 case PIPE_CAP_QUERY_TIMESTAMP:
236 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
237 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
238 case PIPE_CAP_DRAW_INDIRECT:
239 case PIPE_CAP_UMA:
240 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
241 case PIPE_CAP_CLIP_HALFZ:
242 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
243 case PIPE_CAP_DEPTH_BOUNDS_TEST:
244 case PIPE_CAP_CLEAR_TEXTURE:
245 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
246 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
247 case PIPE_CAP_CULL_DISTANCE:
248 case PIPE_CAP_CUBE_MAP_ARRAY:
249 case PIPE_CAP_DOUBLES:
250 return 1;
251
252 /* MSAA support
253 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
254 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
255 case PIPE_CAP_TEXTURE_MULTISAMPLE:
256 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
257 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
258 case PIPE_CAP_FAKE_SW_MSAA:
259 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
260
261 /* fetch jit change for 2-4GB buffers requires alignment */
262 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
263 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
264 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
265 return 1;
266
267 /* unsupported features */
268 case PIPE_CAP_ANISOTROPIC_FILTER:
269 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
270 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
271 case PIPE_CAP_SHADER_STENCIL_EXPORT:
272 case PIPE_CAP_TEXTURE_BARRIER:
273 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
274 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
275 case PIPE_CAP_COMPUTE:
276 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
277 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
278 case PIPE_CAP_TGSI_TEXCOORD:
279 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
280 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
281 case PIPE_CAP_TEXTURE_GATHER_SM5:
282 case PIPE_CAP_TEXTURE_QUERY_LOD:
283 case PIPE_CAP_SAMPLE_SHADING:
284 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
285 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
286 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
287 case PIPE_CAP_SAMPLER_VIEW_TARGET:
288 case PIPE_CAP_VERTEXID_NOBASE:
289 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
290 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
291 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
292 case PIPE_CAP_TGSI_TXQS:
293 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
294 case PIPE_CAP_SHAREABLE_SHADERS:
295 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
296 case PIPE_CAP_DRAW_PARAMETERS:
297 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
298 case PIPE_CAP_MULTI_DRAW_INDIRECT:
299 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
300 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
301 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
302 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
303 case PIPE_CAP_INVALIDATE_BUFFER:
304 case PIPE_CAP_GENERATE_MIPMAP:
305 case PIPE_CAP_STRING_MARKER:
306 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
307 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
308 case PIPE_CAP_QUERY_BUFFER_OBJECT:
309 case PIPE_CAP_QUERY_MEMORY_INFO:
310 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
311 case PIPE_CAP_PCI_GROUP:
312 case PIPE_CAP_PCI_BUS:
313 case PIPE_CAP_PCI_DEVICE:
314 case PIPE_CAP_PCI_FUNCTION:
315 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
316 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
317 case PIPE_CAP_TGSI_VOTE:
318 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
319 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
320 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
321 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
322 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
323 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
324 case PIPE_CAP_NATIVE_FENCE_FD:
325 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
326 case PIPE_CAP_TGSI_FS_FBFETCH:
327 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
328 case PIPE_CAP_INT64:
329 case PIPE_CAP_INT64_DIVMOD:
330 case PIPE_CAP_TGSI_TEX_TXF_LZ:
331 case PIPE_CAP_TGSI_CLOCK:
332 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
333 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
334 case PIPE_CAP_TGSI_BALLOT:
335 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
336 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
337 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
338 case PIPE_CAP_POST_DEPTH_COVERAGE:
339 case PIPE_CAP_BINDLESS_TEXTURE:
340 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
341 case PIPE_CAP_QUERY_SO_OVERFLOW:
342 case PIPE_CAP_MEMOBJ:
343 case PIPE_CAP_LOAD_CONSTBUF:
344 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
345 case PIPE_CAP_TILE_RASTER_ORDER:
346 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
347 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
348 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
349 return 0;
350
351 case PIPE_CAP_VENDOR_ID:
352 return 0xFFFFFFFF;
353 case PIPE_CAP_DEVICE_ID:
354 return 0xFFFFFFFF;
355 case PIPE_CAP_ACCELERATED:
356 return 0;
357 case PIPE_CAP_VIDEO_MEMORY: {
358 /* XXX: Do we want to return the full amount of system memory ? */
359 uint64_t system_memory;
360
361 if (!os_get_total_physical_memory(&system_memory))
362 return 0;
363
364 return (int)(system_memory >> 20);
365 }
366 }
367
368 /* should only get here on unhandled cases */
369 debug_printf("Unexpected PIPE_CAP %d query\n", param);
370 return 0;
371 }
372
373 static int
374 swr_get_shader_param(struct pipe_screen *screen,
375 enum pipe_shader_type shader,
376 enum pipe_shader_cap param)
377 {
378 if (shader == PIPE_SHADER_VERTEX ||
379 shader == PIPE_SHADER_FRAGMENT ||
380 shader == PIPE_SHADER_GEOMETRY)
381 return gallivm_get_shader_param(param);
382
383 // Todo: tesselation, compute
384 return 0;
385 }
386
387
388 static float
389 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
390 {
391 switch (param) {
392 case PIPE_CAPF_MAX_LINE_WIDTH:
393 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
394 case PIPE_CAPF_MAX_POINT_WIDTH:
395 return 255.0; /* arbitrary */
396 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
397 return 0.0;
398 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
399 return 0.0;
400 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
401 return 16.0; /* arbitrary */
402 case PIPE_CAPF_GUARD_BAND_LEFT:
403 case PIPE_CAPF_GUARD_BAND_TOP:
404 case PIPE_CAPF_GUARD_BAND_RIGHT:
405 case PIPE_CAPF_GUARD_BAND_BOTTOM:
406 return 0.0;
407 }
408 /* should only get here on unhandled cases */
409 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
410 return 0.0;
411 }
412
413 SWR_FORMAT
414 mesa_to_swr_format(enum pipe_format format)
415 {
416 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
417 /* depth / stencil */
418 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
419 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
420 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
421 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
422 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
423
424 /* alpha */
425 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
426 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
427 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
428 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
429
430 /* odd sizes, bgr */
431 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
432 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
433 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
434 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
435 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
436 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
437 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
438 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
439 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
440
441 /* rgb10a2 */
442 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
443 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
444 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
445 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
446 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
447
448 /* rgb10x2 */
449 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
450
451 /* bgr10a2 */
452 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
453 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
454 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
455 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
456 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
457
458 /* bgr10x2 */
459 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
460
461 /* r11g11b10 */
462 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
463
464 /* 32 bits per component */
465 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
466 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
467 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
468 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
469 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
470
471 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
472 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
473 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
474 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
475
476 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
477 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
478 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
479 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
480
481 {PIPE_FORMAT_R32_UINT, R32_UINT},
482 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
483 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
484 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
485
486 {PIPE_FORMAT_R32_SINT, R32_SINT},
487 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
488 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
489 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
490
491 /* 16 bits per component */
492 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
493 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
494 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
495 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
496 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
497
498 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
499 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
500 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
501 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
502
503 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
504 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
505 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
506 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
507
508 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
509 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
510 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
511 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
512
513 {PIPE_FORMAT_R16_UINT, R16_UINT},
514 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
515 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
516 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
517
518 {PIPE_FORMAT_R16_SINT, R16_SINT},
519 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
520 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
521 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
522
523 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
524 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
525 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
526 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
527 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
528
529 /* 8 bits per component */
530 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
531 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
532 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
533 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
534 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
535 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
536 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
537 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
538
539 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
540 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
541 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
542 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
543
544 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
545 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
546 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
547 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
548
549 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
550 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
551 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
552 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
553
554 {PIPE_FORMAT_R8_UINT, R8_UINT},
555 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
556 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
557 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
558
559 {PIPE_FORMAT_R8_SINT, R8_SINT},
560 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
561 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
562 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
563
564 /* These formats are valid for vertex data, but should not be used
565 * for render targets.
566 */
567
568 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
569 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
570 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
571 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
572
573 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
574 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
575 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
576 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
577
578 /* These formats have entries in SWR but don't have Load/StoreTile
579 * implementations. That means these aren't renderable, and thus having
580 * a mapping entry here is detrimental.
581 */
582 /*
583
584 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
585 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
586 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
587 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
588 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
589
590 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
591 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
592
593 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
594 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
595 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
596
597 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
598 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
599 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
600
601 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
602 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
603 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
604 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
605
606 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
607 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
608 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
609 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
610 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
611 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
612 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
613 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
614
615 {PIPE_FORMAT_I8_UINT, I8_UINT},
616 {PIPE_FORMAT_L8_UINT, L8_UINT},
617 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
618
619 {PIPE_FORMAT_I8_SINT, I8_SINT},
620 {PIPE_FORMAT_L8_SINT, L8_SINT},
621 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
622
623 */
624 };
625
626 auto it = mesa2swr.find(format);
627 if (it == mesa2swr.end())
628 return (SWR_FORMAT)-1;
629 else
630 return it->second;
631 }
632
633 static boolean
634 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
635 {
636 struct sw_winsys *winsys = screen->winsys;
637 struct sw_displaytarget *dt;
638
639 const unsigned width = align(res->swr.width, res->swr.halign);
640 const unsigned height = align(res->swr.height, res->swr.valign);
641
642 UINT stride;
643 dt = winsys->displaytarget_create(winsys,
644 res->base.bind,
645 res->base.format,
646 width, height,
647 64, NULL,
648 &stride);
649
650 if (dt == NULL)
651 return FALSE;
652
653 void *map = winsys->displaytarget_map(winsys, dt, 0);
654
655 res->display_target = dt;
656 res->swr.xpBaseAddress = (gfxptr_t)map;
657
658 /* Clear the display target surface */
659 if (map)
660 memset(map, 0, height * stride);
661
662 winsys->displaytarget_unmap(winsys, dt);
663
664 return TRUE;
665 }
666
667 static bool
668 swr_texture_layout(struct swr_screen *screen,
669 struct swr_resource *res,
670 boolean allocate)
671 {
672 struct pipe_resource *pt = &res->base;
673
674 pipe_format fmt = pt->format;
675 const struct util_format_description *desc = util_format_description(fmt);
676
677 res->has_depth = util_format_has_depth(desc);
678 res->has_stencil = util_format_has_stencil(desc);
679
680 if (res->has_stencil && !res->has_depth)
681 fmt = PIPE_FORMAT_R8_UINT;
682
683 /* We always use the SWR layout. For 2D and 3D textures this looks like:
684 *
685 * |<------- pitch ------->|
686 * +=======================+-------
687 * |Array 0 | ^
688 * | | |
689 * | Level 0 | |
690 * | | |
691 * | | qpitch
692 * +-----------+-----------+ |
693 * | | L2L2L2L2 | |
694 * | Level 1 | L3L3 | |
695 * | | L4 | v
696 * +===========+===========+-------
697 * |Array 1 |
698 * | |
699 * | Level 0 |
700 * | |
701 * | |
702 * +-----------+-----------+
703 * | | L2L2L2L2 |
704 * | Level 1 | L3L3 |
705 * | | L4 |
706 * +===========+===========+
707 *
708 * The overall width in bytes is known as the pitch, while the overall
709 * height in rows is the qpitch. Array slices are laid out logically below
710 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
711 * just invalid for the higher array numbers (since depth is also
712 * minified). 1D and 1D array surfaces are stored effectively the same way,
713 * except that pitch never plays into it. All the levels are logically
714 * adjacent to each other on the X axis. The qpitch becomes the number of
715 * elements between array slices, while the pitch is unused.
716 *
717 * Each level's sizes are subject to the valign and halign settings of the
718 * surface. For compressed formats that swr is unaware of, we will use an
719 * appropriately-sized uncompressed format, and scale the widths/heights.
720 *
721 * This surface is stored inside res->swr. For depth/stencil textures,
722 * res->secondary will have an identically-laid-out but R8_UINT-formatted
723 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
724 * texels, to simplify map/unmap logic which copies the stencil values
725 * in/out.
726 */
727
728 res->swr.width = pt->width0;
729 res->swr.height = pt->height0;
730 res->swr.type = swr_convert_target_type(pt->target);
731 res->swr.tileMode = SWR_TILE_NONE;
732 res->swr.format = mesa_to_swr_format(fmt);
733 res->swr.numSamples = std::max(1u, pt->nr_samples);
734
735 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
736 res->swr.halign = KNOB_MACROTILE_X_DIM;
737 res->swr.valign = KNOB_MACROTILE_Y_DIM;
738
739 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
740 * surface sample count. */
741 if (screen->msaa_force_enable) {
742 res->swr.numSamples = screen->msaa_max_count;
743 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
744 res->swr.numSamples);
745 }
746 } else {
747 res->swr.halign = 1;
748 res->swr.valign = 1;
749 }
750
751 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
752 unsigned width = align(pt->width0, halign);
753 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
754 for (int level = 1; level <= pt->last_level; level++)
755 width += align(u_minify(pt->width0, level), halign);
756 res->swr.pitch = util_format_get_blocksize(fmt);
757 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
758 } else {
759 // The pitch is the overall width of the texture in bytes. Most of the
760 // time this is the pitch of level 0 since all the other levels fit
761 // underneath it. However in some degenerate situations, the width of
762 // level1 + level2 may be larger. In that case, we use those
763 // widths. This can happen if, e.g. halign is 32, and the width of level
764 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
765 // be 32 each, adding up to 64.
766 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
767 if (pt->last_level > 1) {
768 width = std::max<uint32_t>(
769 width,
770 align(u_minify(pt->width0, 1), halign) +
771 align(u_minify(pt->width0, 2), halign));
772 }
773 res->swr.pitch = util_format_get_stride(fmt, width);
774
775 // The qpitch is controlled by either the height of the second LOD, or
776 // the combination of all the later LODs.
777 unsigned height = align(pt->height0, valign);
778 if (pt->last_level == 1) {
779 height += align(u_minify(pt->height0, 1), valign);
780 } else if (pt->last_level > 1) {
781 unsigned level1 = align(u_minify(pt->height0, 1), valign);
782 unsigned level2 = 0;
783 for (int level = 2; level <= pt->last_level; level++) {
784 level2 += align(u_minify(pt->height0, level), valign);
785 }
786 height += std::max(level1, level2);
787 }
788 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
789 }
790
791 if (pt->target == PIPE_TEXTURE_3D)
792 res->swr.depth = pt->depth0;
793 else
794 res->swr.depth = pt->array_size;
795
796 // Fix up swr format if necessary so that LOD offset computation works
797 if (res->swr.format == (SWR_FORMAT)-1) {
798 switch (util_format_get_blocksize(fmt)) {
799 default:
800 unreachable("Unexpected format block size");
801 case 1: res->swr.format = R8_UINT; break;
802 case 2: res->swr.format = R16_UINT; break;
803 case 4: res->swr.format = R32_UINT; break;
804 case 8:
805 if (util_format_is_compressed(fmt))
806 res->swr.format = BC4_UNORM;
807 else
808 res->swr.format = R32G32_UINT;
809 break;
810 case 16:
811 if (util_format_is_compressed(fmt))
812 res->swr.format = BC5_UNORM;
813 else
814 res->swr.format = R32G32B32A32_UINT;
815 break;
816 }
817 }
818
819 for (int level = 0; level <= pt->last_level; level++) {
820 res->mip_offsets[level] =
821 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
822 }
823
824 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
825 res->swr.pitch * res->swr.numSamples;
826 if (total_size > SWR_MAX_TEXTURE_SIZE)
827 return false;
828
829 if (allocate) {
830 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
831 if (!res->swr.xpBaseAddress)
832 return false;
833
834 if (res->has_depth && res->has_stencil) {
835 res->secondary = res->swr;
836 res->secondary.format = R8_UINT;
837 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
838
839 for (int level = 0; level <= pt->last_level; level++) {
840 res->secondary_mip_offsets[level] =
841 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
842 }
843
844 total_size = res->secondary.depth * res->secondary.qpitch *
845 res->secondary.pitch * res->secondary.numSamples;
846
847 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
848 if (!res->secondary.xpBaseAddress) {
849 AlignedFree((void *)res->swr.xpBaseAddress);
850 return false;
851 }
852 }
853 }
854
855 return true;
856 }
857
858 static boolean
859 swr_can_create_resource(struct pipe_screen *screen,
860 const struct pipe_resource *templat)
861 {
862 struct swr_resource res;
863 memset(&res, 0, sizeof(res));
864 res.base = *templat;
865 return swr_texture_layout(swr_screen(screen), &res, false);
866 }
867
868 /* Helper function that conditionally creates a single-sample resolve resource
869 * and attaches it to main multisample resource. */
870 static boolean
871 swr_create_resolve_resource(struct pipe_screen *_screen,
872 struct swr_resource *msaa_res)
873 {
874 struct swr_screen *screen = swr_screen(_screen);
875
876 /* If resource is multisample, create a single-sample resolve resource */
877 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
878 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
879
880 /* Create a single-sample copy of the resource. Copy the original
881 * resource parameters and set flag to prevent recursion when re-calling
882 * resource_create */
883 struct pipe_resource alt_template = msaa_res->base;
884 alt_template.nr_samples = 0;
885 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
886
887 /* Note: Display_target is a special single-sample resource, only the
888 * display_target has been created already. */
889 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
890 | PIPE_BIND_SHARED)) {
891 /* Allocate the multisample buffers. */
892 if (!swr_texture_layout(screen, msaa_res, true))
893 return false;
894
895 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
896 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
897 alt_template.bind = PIPE_BIND_RENDER_TARGET;
898 }
899
900 /* Allocate single-sample resolve surface */
901 struct pipe_resource *alt;
902 alt = _screen->resource_create(_screen, &alt_template);
903 if (!alt)
904 return false;
905
906 /* Attach it to the multisample resource */
907 msaa_res->resolve_target = alt;
908
909 /* Hang resolve surface state off the multisample surface state to so
910 * StoreTiles knows where to resolve the surface. */
911 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
912 }
913
914 return true; /* success */
915 }
916
917 static struct pipe_resource *
918 swr_resource_create(struct pipe_screen *_screen,
919 const struct pipe_resource *templat)
920 {
921 struct swr_screen *screen = swr_screen(_screen);
922 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
923 if (!res)
924 return NULL;
925
926 res->base = *templat;
927 pipe_reference_init(&res->base.reference, 1);
928 res->base.screen = &screen->base;
929
930 if (swr_resource_is_texture(&res->base)) {
931 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
932 | PIPE_BIND_SHARED)) {
933 /* displayable surface
934 * first call swr_texture_layout without allocating to finish
935 * filling out the SWR_SURFACE_STATE in res */
936 swr_texture_layout(screen, res, false);
937 if (!swr_displaytarget_layout(screen, res))
938 goto fail;
939 } else {
940 /* texture map */
941 if (!swr_texture_layout(screen, res, true))
942 goto fail;
943 }
944
945 /* If resource was multisample, create resolve resource and attach
946 * it to multisample resource. */
947 if (!swr_create_resolve_resource(_screen, res))
948 goto fail;
949
950 } else {
951 /* other data (vertex buffer, const buffer, etc) */
952 assert(util_format_get_blocksize(templat->format) == 1);
953 assert(templat->height0 == 1);
954 assert(templat->depth0 == 1);
955 assert(templat->last_level == 0);
956
957 /* Easiest to just call swr_texture_layout, as it sets up
958 * SWR_SURFACE_STATE in res */
959 if (!swr_texture_layout(screen, res, true))
960 goto fail;
961 }
962
963 return &res->base;
964
965 fail:
966 FREE(res);
967 return NULL;
968 }
969
970 static void
971 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
972 {
973 struct swr_screen *screen = swr_screen(p_screen);
974 struct swr_resource *spr = swr_resource(pt);
975
976 if (spr->display_target) {
977 /* If resource is display target, winsys manages the buffer and will
978 * free it on displaytarget_destroy. */
979 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
980
981 struct sw_winsys *winsys = screen->winsys;
982 winsys->displaytarget_destroy(winsys, spr->display_target);
983
984 if (spr->swr.numSamples > 1) {
985 /* Free an attached resolve resource */
986 struct swr_resource *alt = swr_resource(spr->resolve_target);
987 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
988
989 /* Free multisample buffer */
990 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
991 }
992 } else {
993 /* For regular resources, defer deletion */
994 swr_resource_unused(pt);
995
996 if (spr->swr.numSamples > 1) {
997 /* Free an attached resolve resource */
998 struct swr_resource *alt = swr_resource(spr->resolve_target);
999 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1000 }
1001
1002 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1003 swr_fence_work_free(screen->flush_fence,
1004 (void*)(spr->secondary.xpBaseAddress), true);
1005
1006 /* If work queue grows too large, submit a fence to force queue to
1007 * drain. This is mainly to decrease the amount of memory used by the
1008 * piglit streaming-texture-leak test */
1009 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1010 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1011 }
1012
1013 FREE(spr);
1014 }
1015
1016
1017 static void
1018 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1019 struct pipe_resource *resource,
1020 unsigned level,
1021 unsigned layer,
1022 void *context_private,
1023 struct pipe_box *sub_box)
1024 {
1025 struct swr_screen *screen = swr_screen(p_screen);
1026 struct sw_winsys *winsys = screen->winsys;
1027 struct swr_resource *spr = swr_resource(resource);
1028 struct pipe_context *pipe = screen->pipe;
1029 struct swr_context *ctx = swr_context(pipe);
1030
1031 if (pipe) {
1032 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1033 swr_resource_unused(resource);
1034 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1035 }
1036
1037 /* Multisample resolved into resolve_target at flush with store_resource */
1038 if (pipe && spr->swr.numSamples > 1) {
1039 struct pipe_resource *resolve_target = spr->resolve_target;
1040
1041 /* Once resolved, copy into display target */
1042 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1043
1044 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1045 PIPE_TRANSFER_WRITE);
1046 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1047 winsys->displaytarget_unmap(winsys, spr->display_target);
1048 }
1049
1050 debug_assert(spr->display_target);
1051 if (spr->display_target)
1052 winsys->displaytarget_display(
1053 winsys, spr->display_target, context_private, sub_box);
1054 }
1055
1056
1057 static void
1058 swr_destroy_screen(struct pipe_screen *p_screen)
1059 {
1060 struct swr_screen *screen = swr_screen(p_screen);
1061 struct sw_winsys *winsys = screen->winsys;
1062
1063 fprintf(stderr, "SWR destroy screen!\n");
1064
1065 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1066 swr_fence_reference(p_screen, &screen->flush_fence, NULL);
1067
1068 JitDestroyContext(screen->hJitMgr);
1069 #if USE_SIMD16_SHADERS
1070 JitDestroyContext(screen->hJitMgr16);
1071 #endif
1072
1073 if (winsys->destroy)
1074 winsys->destroy(winsys);
1075
1076 FREE(screen);
1077 }
1078
1079
1080 static void
1081 swr_validate_env_options(struct swr_screen *screen)
1082 {
1083 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1084 * copied to scratch space on a draw. Past this, the draw will access
1085 * user-buffer directly and then block. This is faster than queuing many
1086 * large client draws. */
1087 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1088 int client_copy_limit =
1089 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1090 if (client_copy_limit > 0)
1091 screen->client_copy_limit = client_copy_limit;
1092
1093 /* XXX msaa under development, disable by default for now */
1094 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1095
1096 /* validate env override values, within range and power of 2 */
1097 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1098 if (msaa_max_count != 1) {
1099 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1100 || !util_is_power_of_two(msaa_max_count)) {
1101 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1102 fprintf(stderr, "must be power of 2 between 1 and %d" \
1103 " (or 1 to disable msaa)\n",
1104 SWR_MAX_NUM_MULTISAMPLES);
1105 msaa_max_count = 1;
1106 }
1107
1108 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1109 if (msaa_max_count == 1)
1110 fprintf(stderr, "(msaa disabled)\n");
1111
1112 screen->msaa_max_count = msaa_max_count;
1113 }
1114
1115 screen->msaa_force_enable = debug_get_bool_option(
1116 "SWR_MSAA_FORCE_ENABLE", false);
1117 if (screen->msaa_force_enable)
1118 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1119 }
1120
1121
1122 PUBLIC
1123 struct pipe_screen *
1124 swr_create_screen_internal(struct sw_winsys *winsys)
1125 {
1126 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1127
1128 if (!screen)
1129 return NULL;
1130
1131 if (!lp_build_init()) {
1132 FREE(screen);
1133 return NULL;
1134 }
1135
1136 screen->winsys = winsys;
1137 screen->base.get_name = swr_get_name;
1138 screen->base.get_vendor = swr_get_vendor;
1139 screen->base.is_format_supported = swr_is_format_supported;
1140 screen->base.context_create = swr_create_context;
1141 screen->base.can_create_resource = swr_can_create_resource;
1142
1143 screen->base.destroy = swr_destroy_screen;
1144 screen->base.get_param = swr_get_param;
1145 screen->base.get_shader_param = swr_get_shader_param;
1146 screen->base.get_paramf = swr_get_paramf;
1147
1148 screen->base.resource_create = swr_resource_create;
1149 screen->base.resource_destroy = swr_resource_destroy;
1150
1151 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1152
1153 // Pass in "" for architecture for run-time determination
1154 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1155 #if USE_SIMD16_SHADERS
1156 screen->hJitMgr16 = JitCreateContext(16, "", "swr");
1157 #endif
1158
1159 swr_fence_init(&screen->base);
1160
1161 swr_validate_env_options(screen);
1162
1163 return &screen->base;
1164 }
1165