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gallium: add PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /* MSVC case instensitive compare */
50 #if defined(PIPE_CC_MSVC)
51 #define strcasecmp lstrcmpiA
52 #endif
53
54 /*
55 * Max texture sizes
56 * XXX Check max texture size values against core and sampler.
57 */
58 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
59 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
60 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
61 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
62 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
63
64 /* Flag indicates creation of alternate surface, to prevent recursive loop
65 * in resource creation when msaa_force_enable is set. */
66 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
67
68
69 static const char *
70 swr_get_name(struct pipe_screen *screen)
71 {
72 static char buf[100];
73 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
74 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
75 lp_native_vector_width );
76 return buf;
77 }
78
79 static const char *
80 swr_get_vendor(struct pipe_screen *screen)
81 {
82 return "Intel Corporation";
83 }
84
85 static boolean
86 swr_is_format_supported(struct pipe_screen *_screen,
87 enum pipe_format format,
88 enum pipe_texture_target target,
89 unsigned sample_count,
90 unsigned bind)
91 {
92 struct swr_screen *screen = swr_screen(_screen);
93 struct sw_winsys *winsys = screen->winsys;
94 const struct util_format_description *format_desc;
95
96 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
97 || target == PIPE_TEXTURE_1D_ARRAY
98 || target == PIPE_TEXTURE_2D
99 || target == PIPE_TEXTURE_2D_ARRAY
100 || target == PIPE_TEXTURE_RECT
101 || target == PIPE_TEXTURE_3D
102 || target == PIPE_TEXTURE_CUBE
103 || target == PIPE_TEXTURE_CUBE_ARRAY);
104
105 format_desc = util_format_description(format);
106 if (!format_desc)
107 return FALSE;
108
109 if ((sample_count > screen->msaa_max_count)
110 || !util_is_power_of_two(sample_count))
111 return FALSE;
112
113 if (bind & PIPE_BIND_DISPLAY_TARGET) {
114 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
115 return FALSE;
116 }
117
118 if (bind & PIPE_BIND_RENDER_TARGET) {
119 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
120 return FALSE;
121
122 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
123 return FALSE;
124
125 /*
126 * Although possible, it is unnatural to render into compressed or YUV
127 * surfaces. So disable these here to avoid going into weird paths
128 * inside the state trackers.
129 */
130 if (format_desc->block.width != 1 || format_desc->block.height != 1)
131 return FALSE;
132 }
133
134 if (bind & PIPE_BIND_DEPTH_STENCIL) {
135 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
136 return FALSE;
137
138 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
139 return FALSE;
140 }
141
142 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
143 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
144 return FALSE;
145 }
146
147 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
148 format != PIPE_FORMAT_ETC1_RGB8) {
149 return FALSE;
150 }
151
152 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
153 return util_format_s3tc_enabled;
154 }
155
156 return TRUE;
157 }
158
159 static int
160 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
161 {
162 switch (param) {
163 /* limits */
164 case PIPE_CAP_MAX_RENDER_TARGETS:
165 return PIPE_MAX_COLOR_BUFS;
166 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
167 return SWR_MAX_TEXTURE_2D_LEVELS;
168 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
169 return SWR_MAX_TEXTURE_3D_LEVELS;
170 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
171 return SWR_MAX_TEXTURE_CUBE_LEVELS;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
173 return MAX_SO_STREAMS;
174 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
175 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
176 return MAX_ATTRIBUTES * 4;
177 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
178 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
179 return 1024;
180 case PIPE_CAP_MAX_VERTEX_STREAMS:
181 return 1;
182 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
183 return 2048;
184 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
185 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
186 case PIPE_CAP_MIN_TEXEL_OFFSET:
187 return -8;
188 case PIPE_CAP_MAX_TEXEL_OFFSET:
189 return 7;
190 case PIPE_CAP_GLSL_FEATURE_LEVEL:
191 return 330;
192 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
193 return 16;
194 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
195 return 64;
196 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
197 return 65536;
198 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
199 return 0;
200 case PIPE_CAP_MAX_VIEWPORTS:
201 return 1;
202 case PIPE_CAP_ENDIANNESS:
203 return PIPE_ENDIAN_NATIVE;
204 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
205 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
206 return 0;
207
208 /* supported features */
209 case PIPE_CAP_NPOT_TEXTURES:
210 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
211 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
212 case PIPE_CAP_TWO_SIDED_STENCIL:
213 case PIPE_CAP_SM3:
214 case PIPE_CAP_POINT_SPRITE:
215 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
216 case PIPE_CAP_OCCLUSION_QUERY:
217 case PIPE_CAP_QUERY_TIME_ELAPSED:
218 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
219 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
220 case PIPE_CAP_TEXTURE_SHADOW_MAP:
221 case PIPE_CAP_TEXTURE_SWIZZLE:
222 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
223 case PIPE_CAP_INDEP_BLEND_ENABLE:
224 case PIPE_CAP_INDEP_BLEND_FUNC:
225 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
226 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
227 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
228 case PIPE_CAP_DEPTH_CLIP_DISABLE:
229 case PIPE_CAP_PRIMITIVE_RESTART:
230 case PIPE_CAP_TGSI_INSTANCEID:
231 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
232 case PIPE_CAP_START_INSTANCE:
233 case PIPE_CAP_SEAMLESS_CUBE_MAP:
234 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
235 case PIPE_CAP_CONDITIONAL_RENDER:
236 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
237 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
238 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
239 case PIPE_CAP_USER_VERTEX_BUFFERS:
240 case PIPE_CAP_USER_CONSTANT_BUFFERS:
241 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
242 case PIPE_CAP_QUERY_TIMESTAMP:
243 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
244 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
245 case PIPE_CAP_DRAW_INDIRECT:
246 case PIPE_CAP_UMA:
247 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
248 case PIPE_CAP_CLIP_HALFZ:
249 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
250 case PIPE_CAP_DEPTH_BOUNDS_TEST:
251 case PIPE_CAP_CLEAR_TEXTURE:
252 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
253 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
254 case PIPE_CAP_CULL_DISTANCE:
255 case PIPE_CAP_CUBE_MAP_ARRAY:
256 case PIPE_CAP_DOUBLES:
257 return 1;
258
259 /* MSAA support
260 * If user has explicitly set max_sample_count = 0 (via SWR_MSAA_MAX_COUNT)
261 * then disable all MSAA support and go back to old caps. */
262 case PIPE_CAP_TEXTURE_MULTISAMPLE:
263 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
264 return swr_screen(screen)->msaa_max_count ? 1 : 0;
265 case PIPE_CAP_FAKE_SW_MSAA:
266 return swr_screen(screen)->msaa_max_count ? 0 : 1;
267
268 /* unsupported features */
269 case PIPE_CAP_ANISOTROPIC_FILTER:
270 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
271 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
272 case PIPE_CAP_SHADER_STENCIL_EXPORT:
273 case PIPE_CAP_TEXTURE_BARRIER:
274 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
275 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
276 case PIPE_CAP_COMPUTE:
277 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
278 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
279 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
280 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
281 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
282 case PIPE_CAP_TGSI_TEXCOORD:
283 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
284 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
285 case PIPE_CAP_TEXTURE_GATHER_SM5:
286 case PIPE_CAP_TEXTURE_QUERY_LOD:
287 case PIPE_CAP_SAMPLE_SHADING:
288 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
289 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
290 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
291 case PIPE_CAP_SAMPLER_VIEW_TARGET:
292 case PIPE_CAP_VERTEXID_NOBASE:
293 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
294 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
295 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
296 case PIPE_CAP_TGSI_TXQS:
297 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
298 case PIPE_CAP_SHAREABLE_SHADERS:
299 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
300 case PIPE_CAP_DRAW_PARAMETERS:
301 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
302 case PIPE_CAP_MULTI_DRAW_INDIRECT:
303 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
304 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
305 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
306 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
307 case PIPE_CAP_INVALIDATE_BUFFER:
308 case PIPE_CAP_GENERATE_MIPMAP:
309 case PIPE_CAP_STRING_MARKER:
310 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
311 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
312 case PIPE_CAP_QUERY_BUFFER_OBJECT:
313 case PIPE_CAP_QUERY_MEMORY_INFO:
314 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
315 case PIPE_CAP_PCI_GROUP:
316 case PIPE_CAP_PCI_BUS:
317 case PIPE_CAP_PCI_DEVICE:
318 case PIPE_CAP_PCI_FUNCTION:
319 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
320 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
321 case PIPE_CAP_TGSI_VOTE:
322 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
323 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
324 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
325 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
326 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
327 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
328 case PIPE_CAP_NATIVE_FENCE_FD:
329 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
330 case PIPE_CAP_TGSI_FS_FBFETCH:
331 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
332 case PIPE_CAP_INT64:
333 case PIPE_CAP_INT64_DIVMOD:
334 case PIPE_CAP_TGSI_TEX_TXF_LZ:
335 case PIPE_CAP_TGSI_CLOCK:
336 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
337 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
338 case PIPE_CAP_TGSI_BALLOT:
339 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
340 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
341 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
342 return 0;
343
344 case PIPE_CAP_VENDOR_ID:
345 return 0xFFFFFFFF;
346 case PIPE_CAP_DEVICE_ID:
347 return 0xFFFFFFFF;
348 case PIPE_CAP_ACCELERATED:
349 return 0;
350 case PIPE_CAP_VIDEO_MEMORY: {
351 /* XXX: Do we want to return the full amount of system memory ? */
352 uint64_t system_memory;
353
354 if (!os_get_total_physical_memory(&system_memory))
355 return 0;
356
357 return (int)(system_memory >> 20);
358 }
359 }
360
361 /* should only get here on unhandled cases */
362 debug_printf("Unexpected PIPE_CAP %d query\n", param);
363 return 0;
364 }
365
366 static int
367 swr_get_shader_param(struct pipe_screen *screen,
368 enum pipe_shader_type shader,
369 enum pipe_shader_cap param)
370 {
371 if (shader == PIPE_SHADER_VERTEX ||
372 shader == PIPE_SHADER_FRAGMENT ||
373 shader == PIPE_SHADER_GEOMETRY)
374 return gallivm_get_shader_param(param);
375
376 // Todo: tesselation, compute
377 return 0;
378 }
379
380
381 static float
382 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
383 {
384 switch (param) {
385 case PIPE_CAPF_MAX_LINE_WIDTH:
386 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
387 case PIPE_CAPF_MAX_POINT_WIDTH:
388 return 255.0; /* arbitrary */
389 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
390 return 0.0;
391 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
392 return 0.0;
393 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
394 return 16.0; /* arbitrary */
395 case PIPE_CAPF_GUARD_BAND_LEFT:
396 case PIPE_CAPF_GUARD_BAND_TOP:
397 case PIPE_CAPF_GUARD_BAND_RIGHT:
398 case PIPE_CAPF_GUARD_BAND_BOTTOM:
399 return 0.0;
400 }
401 /* should only get here on unhandled cases */
402 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
403 return 0.0;
404 }
405
406 SWR_FORMAT
407 mesa_to_swr_format(enum pipe_format format)
408 {
409 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
410 /* depth / stencil */
411 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
412 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
413 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
414 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
415 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
416
417 /* alpha */
418 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
419 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
420 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
421 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
422
423 /* odd sizes, bgr */
424 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
425 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
426 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
427 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
428 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
429 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
430 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
431 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
432 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
433
434 /* rgb10a2 */
435 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
436 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
437 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
438 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
439 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
440
441 /* rgb10x2 */
442 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
443
444 /* bgr10a2 */
445 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
446 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
447 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
448 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
449 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
450
451 /* bgr10x2 */
452 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
453
454 /* r11g11b10 */
455 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
456
457 /* 32 bits per component */
458 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
459 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
460 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
461 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
462 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
463
464 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
465 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
466 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
467 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
468
469 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
470 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
471 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
472 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
473
474 {PIPE_FORMAT_R32_UINT, R32_UINT},
475 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
476 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
477 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
478
479 {PIPE_FORMAT_R32_SINT, R32_SINT},
480 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
481 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
482 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
483
484 /* 16 bits per component */
485 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
486 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
487 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
488 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
489 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
490
491 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
492 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
493 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
494 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
495
496 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
497 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
498 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
499 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
500
501 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
502 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
503 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
504 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
505
506 {PIPE_FORMAT_R16_UINT, R16_UINT},
507 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
508 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
509 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
510
511 {PIPE_FORMAT_R16_SINT, R16_SINT},
512 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
513 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
514 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
515
516 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
517 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
518 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
519 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
520 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
521
522 /* 8 bits per component */
523 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
524 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
525 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
526 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
527 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
528 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
529 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
530 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
531
532 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
533 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
534 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
535 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
536
537 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
538 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
539 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
540 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
541
542 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
543 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
544 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
545 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
546
547 {PIPE_FORMAT_R8_UINT, R8_UINT},
548 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
549 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
550 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
551
552 {PIPE_FORMAT_R8_SINT, R8_SINT},
553 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
554 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
555 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
556
557 /* These formats are valid for vertex data, but should not be used
558 * for render targets.
559 */
560
561 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
562 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
563 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
564 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
565
566 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
567 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
568 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
569 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
570
571 /* These formats have entries in SWR but don't have Load/StoreTile
572 * implementations. That means these aren't renderable, and thus having
573 * a mapping entry here is detrimental.
574 */
575 /*
576
577 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
578 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
579 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
580 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
581 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
582
583 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
584 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
585
586 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
587 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
588 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
589
590 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
591 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
592 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
593
594 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
595 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
596 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
597 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
598
599 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
600 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
601 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
602 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
603 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
604 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
605 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
606 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
607
608 {PIPE_FORMAT_I8_UINT, I8_UINT},
609 {PIPE_FORMAT_L8_UINT, L8_UINT},
610 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
611
612 {PIPE_FORMAT_I8_SINT, I8_SINT},
613 {PIPE_FORMAT_L8_SINT, L8_SINT},
614 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
615
616 */
617 };
618
619 auto it = mesa2swr.find(format);
620 if (it == mesa2swr.end())
621 return (SWR_FORMAT)-1;
622 else
623 return it->second;
624 }
625
626 static boolean
627 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
628 {
629 struct sw_winsys *winsys = screen->winsys;
630 struct sw_displaytarget *dt;
631
632 const unsigned width = align(res->swr.width, res->swr.halign);
633 const unsigned height = align(res->swr.height, res->swr.valign);
634
635 UINT stride;
636 dt = winsys->displaytarget_create(winsys,
637 res->base.bind,
638 res->base.format,
639 width, height,
640 64, NULL,
641 &stride);
642
643 if (dt == NULL)
644 return FALSE;
645
646 void *map = winsys->displaytarget_map(winsys, dt, 0);
647
648 res->display_target = dt;
649 res->swr.pBaseAddress = (uint8_t*) map;
650
651 /* Clear the display target surface */
652 if (map)
653 memset(map, 0, height * stride);
654
655 winsys->displaytarget_unmap(winsys, dt);
656
657 return TRUE;
658 }
659
660 static bool
661 swr_texture_layout(struct swr_screen *screen,
662 struct swr_resource *res,
663 boolean allocate)
664 {
665 struct pipe_resource *pt = &res->base;
666
667 pipe_format fmt = pt->format;
668 const struct util_format_description *desc = util_format_description(fmt);
669
670 res->has_depth = util_format_has_depth(desc);
671 res->has_stencil = util_format_has_stencil(desc);
672
673 if (res->has_stencil && !res->has_depth)
674 fmt = PIPE_FORMAT_R8_UINT;
675
676 /* We always use the SWR layout. For 2D and 3D textures this looks like:
677 *
678 * |<------- pitch ------->|
679 * +=======================+-------
680 * |Array 0 | ^
681 * | | |
682 * | Level 0 | |
683 * | | |
684 * | | qpitch
685 * +-----------+-----------+ |
686 * | | L2L2L2L2 | |
687 * | Level 1 | L3L3 | |
688 * | | L4 | v
689 * +===========+===========+-------
690 * |Array 1 |
691 * | |
692 * | Level 0 |
693 * | |
694 * | |
695 * +-----------+-----------+
696 * | | L2L2L2L2 |
697 * | Level 1 | L3L3 |
698 * | | L4 |
699 * +===========+===========+
700 *
701 * The overall width in bytes is known as the pitch, while the overall
702 * height in rows is the qpitch. Array slices are laid out logically below
703 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
704 * just invalid for the higher array numbers (since depth is also
705 * minified). 1D and 1D array surfaces are stored effectively the same way,
706 * except that pitch never plays into it. All the levels are logically
707 * adjacent to each other on the X axis. The qpitch becomes the number of
708 * elements between array slices, while the pitch is unused.
709 *
710 * Each level's sizes are subject to the valign and halign settings of the
711 * surface. For compressed formats that swr is unaware of, we will use an
712 * appropriately-sized uncompressed format, and scale the widths/heights.
713 *
714 * This surface is stored inside res->swr. For depth/stencil textures,
715 * res->secondary will have an identically-laid-out but R8_UINT-formatted
716 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
717 * texels, to simplify map/unmap logic which copies the stencil values
718 * in/out.
719 */
720
721 res->swr.width = pt->width0;
722 res->swr.height = pt->height0;
723 res->swr.type = swr_convert_target_type(pt->target);
724 res->swr.tileMode = SWR_TILE_NONE;
725 res->swr.format = mesa_to_swr_format(fmt);
726 res->swr.numSamples = std::max(1u, pt->nr_samples);
727
728 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
729 res->swr.halign = KNOB_MACROTILE_X_DIM;
730 res->swr.valign = KNOB_MACROTILE_Y_DIM;
731
732 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
733 * surface sample count. */
734 if (screen->msaa_force_enable) {
735 res->swr.numSamples = screen->msaa_max_count;
736 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
737 res->swr.numSamples);
738 }
739 } else {
740 res->swr.halign = 1;
741 res->swr.valign = 1;
742 }
743
744 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
745 unsigned width = align(pt->width0, halign);
746 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
747 for (int level = 1; level <= pt->last_level; level++)
748 width += align(u_minify(pt->width0, level), halign);
749 res->swr.pitch = util_format_get_blocksize(fmt);
750 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
751 } else {
752 // The pitch is the overall width of the texture in bytes. Most of the
753 // time this is the pitch of level 0 since all the other levels fit
754 // underneath it. However in some degenerate situations, the width of
755 // level1 + level2 may be larger. In that case, we use those
756 // widths. This can happen if, e.g. halign is 32, and the width of level
757 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
758 // be 32 each, adding up to 64.
759 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
760 if (pt->last_level > 1) {
761 width = std::max<uint32_t>(
762 width,
763 align(u_minify(pt->width0, 1), halign) +
764 align(u_minify(pt->width0, 2), halign));
765 }
766 res->swr.pitch = util_format_get_stride(fmt, width);
767
768 // The qpitch is controlled by either the height of the second LOD, or
769 // the combination of all the later LODs.
770 unsigned height = align(pt->height0, valign);
771 if (pt->last_level == 1) {
772 height += align(u_minify(pt->height0, 1), valign);
773 } else if (pt->last_level > 1) {
774 unsigned level1 = align(u_minify(pt->height0, 1), valign);
775 unsigned level2 = 0;
776 for (int level = 2; level <= pt->last_level; level++) {
777 level2 += align(u_minify(pt->height0, level), valign);
778 }
779 height += std::max(level1, level2);
780 }
781 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
782 }
783
784 if (pt->target == PIPE_TEXTURE_3D)
785 res->swr.depth = pt->depth0;
786 else
787 res->swr.depth = pt->array_size;
788
789 // Fix up swr format if necessary so that LOD offset computation works
790 if (res->swr.format == (SWR_FORMAT)-1) {
791 switch (util_format_get_blocksize(fmt)) {
792 default:
793 unreachable("Unexpected format block size");
794 case 1: res->swr.format = R8_UINT; break;
795 case 2: res->swr.format = R16_UINT; break;
796 case 4: res->swr.format = R32_UINT; break;
797 case 8:
798 if (util_format_is_compressed(fmt))
799 res->swr.format = BC4_UNORM;
800 else
801 res->swr.format = R32G32_UINT;
802 break;
803 case 16:
804 if (util_format_is_compressed(fmt))
805 res->swr.format = BC5_UNORM;
806 else
807 res->swr.format = R32G32B32A32_UINT;
808 break;
809 }
810 }
811
812 for (int level = 0; level <= pt->last_level; level++) {
813 res->mip_offsets[level] =
814 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
815 }
816
817 size_t total_size = res->swr.depth * res->swr.qpitch * res->swr.pitch *
818 res->swr.numSamples;
819 if (total_size > SWR_MAX_TEXTURE_SIZE)
820 return false;
821
822 if (allocate) {
823 res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
824
825 if (res->has_depth && res->has_stencil) {
826 res->secondary = res->swr;
827 res->secondary.format = R8_UINT;
828 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
829
830 for (int level = 0; level <= pt->last_level; level++) {
831 res->secondary_mip_offsets[level] =
832 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
833 }
834
835 total_size = res->secondary.depth * res->secondary.qpitch *
836 res->secondary.pitch * res->secondary.numSamples;
837
838 res->secondary.pBaseAddress = (uint8_t *) AlignedMalloc(total_size,
839 64);
840 }
841 }
842
843 return true;
844 }
845
846 static boolean
847 swr_can_create_resource(struct pipe_screen *screen,
848 const struct pipe_resource *templat)
849 {
850 struct swr_resource res;
851 memset(&res, 0, sizeof(res));
852 res.base = *templat;
853 return swr_texture_layout(swr_screen(screen), &res, false);
854 }
855
856 /* Helper function that conditionally creates a single-sample resolve resource
857 * and attaches it to main multisample resource. */
858 static boolean
859 swr_create_resolve_resource(struct pipe_screen *_screen,
860 struct swr_resource *msaa_res)
861 {
862 struct swr_screen *screen = swr_screen(_screen);
863
864 /* If resource is multisample, create a single-sample resolve resource */
865 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
866 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
867
868 /* Create a single-sample copy of the resource. Copy the original
869 * resource parameters and set flag to prevent recursion when re-calling
870 * resource_create */
871 struct pipe_resource alt_template = msaa_res->base;
872 alt_template.nr_samples = 0;
873 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
874
875 /* Note: Display_target is a special single-sample resource, only the
876 * display_target has been created already. */
877 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
878 | PIPE_BIND_SHARED)) {
879 /* Allocate the multisample buffers. */
880 if (!swr_texture_layout(screen, msaa_res, true))
881 return false;
882
883 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
884 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
885 alt_template.bind = PIPE_BIND_RENDER_TARGET;
886 }
887
888 /* Allocate single-sample resolve surface */
889 struct pipe_resource *alt;
890 alt = _screen->resource_create(_screen, &alt_template);
891 if (!alt)
892 return false;
893
894 /* Attach it to the multisample resource */
895 msaa_res->resolve_target = alt;
896
897 /* Hang resolve surface state off the multisample surface state to so
898 * StoreTiles knows where to resolve the surface. */
899 msaa_res->swr.pAuxBaseAddress = (uint8_t *)&swr_resource(alt)->swr;
900 }
901
902 return true; /* success */
903 }
904
905 static struct pipe_resource *
906 swr_resource_create(struct pipe_screen *_screen,
907 const struct pipe_resource *templat)
908 {
909 struct swr_screen *screen = swr_screen(_screen);
910 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
911 if (!res)
912 return NULL;
913
914 res->base = *templat;
915 pipe_reference_init(&res->base.reference, 1);
916 res->base.screen = &screen->base;
917
918 if (swr_resource_is_texture(&res->base)) {
919 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
920 | PIPE_BIND_SHARED)) {
921 /* displayable surface
922 * first call swr_texture_layout without allocating to finish
923 * filling out the SWR_SURFACE_STATE in res */
924 swr_texture_layout(screen, res, false);
925 if (!swr_displaytarget_layout(screen, res))
926 goto fail;
927 } else {
928 /* texture map */
929 if (!swr_texture_layout(screen, res, true))
930 goto fail;
931 }
932
933 /* If resource was multisample, create resolve resource and attach
934 * it to multisample resource. */
935 if (!swr_create_resolve_resource(_screen, res))
936 goto fail;
937
938 } else {
939 /* other data (vertex buffer, const buffer, etc) */
940 assert(util_format_get_blocksize(templat->format) == 1);
941 assert(templat->height0 == 1);
942 assert(templat->depth0 == 1);
943 assert(templat->last_level == 0);
944
945 /* Easiest to just call swr_texture_layout, as it sets up
946 * SWR_SURFACE_STATE in res */
947 if (!swr_texture_layout(screen, res, true))
948 goto fail;
949 }
950
951 return &res->base;
952
953 fail:
954 FREE(res);
955 return NULL;
956 }
957
958 static void
959 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
960 {
961 struct swr_screen *screen = swr_screen(p_screen);
962 struct swr_resource *spr = swr_resource(pt);
963
964 if (spr->display_target) {
965 /* If resource is display target, winsys manages the buffer and will
966 * free it on displaytarget_destroy. */
967 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
968
969 struct sw_winsys *winsys = screen->winsys;
970 winsys->displaytarget_destroy(winsys, spr->display_target);
971
972 if (spr->swr.numSamples > 1) {
973 /* Free an attached resolve resource */
974 struct swr_resource *alt = swr_resource(spr->resolve_target);
975 swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true);
976
977 /* Free multisample buffer */
978 swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
979 }
980 } else {
981 /* For regular resources, defer deletion */
982 swr_resource_unused(pt);
983
984 if (spr->swr.numSamples > 1) {
985 /* Free an attached resolve resource */
986 struct swr_resource *alt = swr_resource(spr->resolve_target);
987 swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true);
988 }
989
990 swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
991 swr_fence_work_free(screen->flush_fence,
992 spr->secondary.pBaseAddress, true);
993 }
994
995 FREE(spr);
996 }
997
998
999 static void
1000 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1001 struct pipe_resource *resource,
1002 unsigned level,
1003 unsigned layer,
1004 void *context_private,
1005 struct pipe_box *sub_box)
1006 {
1007 struct swr_screen *screen = swr_screen(p_screen);
1008 struct sw_winsys *winsys = screen->winsys;
1009 struct swr_resource *spr = swr_resource(resource);
1010 struct pipe_context *pipe = screen->pipe;
1011
1012 if (pipe) {
1013 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1014 swr_resource_unused(resource);
1015 SwrEndFrame(swr_context(pipe)->swrContext);
1016 }
1017
1018 /* Multisample resolved into resolve_target at flush with store_resource */
1019 if (pipe && spr->swr.numSamples > 1) {
1020 struct pipe_resource *resolve_target = spr->resolve_target;
1021
1022 /* Once resolved, copy into display target */
1023 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1024
1025 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1026 PIPE_TRANSFER_WRITE);
1027 memcpy(map, resolve->pBaseAddress, resolve->pitch * resolve->height);
1028 winsys->displaytarget_unmap(winsys, spr->display_target);
1029 }
1030
1031 debug_assert(spr->display_target);
1032 if (spr->display_target)
1033 winsys->displaytarget_display(
1034 winsys, spr->display_target, context_private, sub_box);
1035 }
1036
1037
1038 static void
1039 swr_destroy_screen(struct pipe_screen *p_screen)
1040 {
1041 struct swr_screen *screen = swr_screen(p_screen);
1042 struct sw_winsys *winsys = screen->winsys;
1043
1044 fprintf(stderr, "SWR destroy screen!\n");
1045
1046 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1047 swr_fence_reference(p_screen, &screen->flush_fence, NULL);
1048
1049 JitDestroyContext(screen->hJitMgr);
1050
1051 if (winsys->destroy)
1052 winsys->destroy(winsys);
1053
1054 FREE(screen);
1055 }
1056
1057 PUBLIC
1058 struct pipe_screen *
1059 swr_create_screen_internal(struct sw_winsys *winsys)
1060 {
1061 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1062
1063 if (!screen)
1064 return NULL;
1065
1066 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
1067 g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152);
1068 }
1069
1070 if (!lp_build_init()) {
1071 FREE(screen);
1072 return NULL;
1073 }
1074
1075 screen->winsys = winsys;
1076 screen->base.get_name = swr_get_name;
1077 screen->base.get_vendor = swr_get_vendor;
1078 screen->base.is_format_supported = swr_is_format_supported;
1079 screen->base.context_create = swr_create_context;
1080 screen->base.can_create_resource = swr_can_create_resource;
1081
1082 screen->base.destroy = swr_destroy_screen;
1083 screen->base.get_param = swr_get_param;
1084 screen->base.get_shader_param = swr_get_shader_param;
1085 screen->base.get_paramf = swr_get_paramf;
1086
1087 screen->base.resource_create = swr_resource_create;
1088 screen->base.resource_destroy = swr_resource_destroy;
1089
1090 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1091
1092 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
1093
1094 swr_fence_init(&screen->base);
1095
1096 util_format_s3tc_init();
1097
1098 /* XXX msaa under development, disable by default for now */
1099 screen->msaa_max_count = 0; /* was SWR_MAX_NUM_MULTISAMPLES; */
1100
1101 /* validate env override values, within range and power of 2 */
1102 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 0);
1103 if (msaa_max_count) {
1104 if ((msaa_max_count < 0) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1105 || !util_is_power_of_two(msaa_max_count)) {
1106 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1107 fprintf(stderr, "must be power of 2 between 1 and %d" \
1108 " (or 0 to disable msaa)\n",
1109 SWR_MAX_NUM_MULTISAMPLES);
1110 msaa_max_count = 0;
1111 }
1112
1113 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1114 if (!msaa_max_count)
1115 fprintf(stderr, "(msaa disabled)\n");
1116
1117 screen->msaa_max_count = msaa_max_count;
1118 }
1119
1120 screen->msaa_force_enable = debug_get_bool_option(
1121 "SWR_MSAA_FORCE_ENABLE", false);
1122 if (screen->msaa_force_enable)
1123 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1124
1125 return &screen->base;
1126 }
1127