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gallium: add support for programmable sample locations
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned bind)
89 {
90 struct swr_screen *screen = swr_screen(_screen);
91 struct sw_winsys *winsys = screen->winsys;
92 const struct util_format_description *format_desc;
93
94 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
95 || target == PIPE_TEXTURE_1D_ARRAY
96 || target == PIPE_TEXTURE_2D
97 || target == PIPE_TEXTURE_2D_ARRAY
98 || target == PIPE_TEXTURE_RECT
99 || target == PIPE_TEXTURE_3D
100 || target == PIPE_TEXTURE_CUBE
101 || target == PIPE_TEXTURE_CUBE_ARRAY);
102
103 format_desc = util_format_description(format);
104 if (!format_desc)
105 return FALSE;
106
107 if ((sample_count > screen->msaa_max_count)
108 || !util_is_power_of_two_or_zero(sample_count))
109 return FALSE;
110
111 if (bind & PIPE_BIND_DISPLAY_TARGET) {
112 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
113 return FALSE;
114 }
115
116 if (bind & PIPE_BIND_RENDER_TARGET) {
117 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
118 return FALSE;
119
120 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
121 return FALSE;
122
123 /*
124 * Although possible, it is unnatural to render into compressed or YUV
125 * surfaces. So disable these here to avoid going into weird paths
126 * inside the state trackers.
127 */
128 if (format_desc->block.width != 1 || format_desc->block.height != 1)
129 return FALSE;
130 }
131
132 if (bind & PIPE_BIND_DEPTH_STENCIL) {
133 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
134 return FALSE;
135
136 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
137 return FALSE;
138 }
139
140 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
141 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
142 return FALSE;
143 }
144
145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
146 format != PIPE_FORMAT_ETC1_RGB8) {
147 return FALSE;
148 }
149
150 return TRUE;
151 }
152
153 static int
154 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
155 {
156 switch (param) {
157 /* limits */
158 case PIPE_CAP_MAX_RENDER_TARGETS:
159 return PIPE_MAX_COLOR_BUFS;
160 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
161 return SWR_MAX_TEXTURE_2D_LEVELS;
162 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
163 return SWR_MAX_TEXTURE_3D_LEVELS;
164 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
165 return SWR_MAX_TEXTURE_CUBE_LEVELS;
166 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
167 return MAX_SO_STREAMS;
168 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
169 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
170 return MAX_ATTRIBUTES * 4;
171 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
172 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
173 return 1024;
174 case PIPE_CAP_MAX_VERTEX_STREAMS:
175 return 1;
176 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
177 return 2048;
178 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
179 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
180 case PIPE_CAP_MIN_TEXEL_OFFSET:
181 return -8;
182 case PIPE_CAP_MAX_TEXEL_OFFSET:
183 return 7;
184 case PIPE_CAP_GLSL_FEATURE_LEVEL:
185 return 330;
186 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
187 return 140;
188 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
189 return 16;
190 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
191 return 64;
192 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
193 return 65536;
194 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
195 return 0;
196 case PIPE_CAP_MAX_VIEWPORTS:
197 return 1;
198 case PIPE_CAP_ENDIANNESS:
199 return PIPE_ENDIAN_NATIVE;
200 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
201 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
202 return 0;
203
204 /* supported features */
205 case PIPE_CAP_NPOT_TEXTURES:
206 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
207 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
208 case PIPE_CAP_SM3:
209 case PIPE_CAP_POINT_SPRITE:
210 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
211 case PIPE_CAP_OCCLUSION_QUERY:
212 case PIPE_CAP_QUERY_TIME_ELAPSED:
213 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
214 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
215 case PIPE_CAP_TEXTURE_SWIZZLE:
216 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
217 case PIPE_CAP_INDEP_BLEND_ENABLE:
218 case PIPE_CAP_INDEP_BLEND_FUNC:
219 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
220 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
221 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
222 case PIPE_CAP_DEPTH_CLIP_DISABLE:
223 case PIPE_CAP_PRIMITIVE_RESTART:
224 case PIPE_CAP_TGSI_INSTANCEID:
225 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
226 case PIPE_CAP_START_INSTANCE:
227 case PIPE_CAP_SEAMLESS_CUBE_MAP:
228 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
229 case PIPE_CAP_CONDITIONAL_RENDER:
230 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
231 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
232 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
233 case PIPE_CAP_USER_VERTEX_BUFFERS:
234 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
235 case PIPE_CAP_QUERY_TIMESTAMP:
236 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
237 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
238 case PIPE_CAP_DRAW_INDIRECT:
239 case PIPE_CAP_UMA:
240 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
241 case PIPE_CAP_CLIP_HALFZ:
242 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
243 case PIPE_CAP_DEPTH_BOUNDS_TEST:
244 case PIPE_CAP_CLEAR_TEXTURE:
245 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
246 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
247 case PIPE_CAP_CULL_DISTANCE:
248 case PIPE_CAP_CUBE_MAP_ARRAY:
249 case PIPE_CAP_DOUBLES:
250 return 1;
251
252 /* MSAA support
253 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
254 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
255 case PIPE_CAP_TEXTURE_MULTISAMPLE:
256 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
257 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
258 case PIPE_CAP_FAKE_SW_MSAA:
259 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
260
261 /* fetch jit change for 2-4GB buffers requires alignment */
262 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
263 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
264 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
265 return 1;
266
267 /* unsupported features */
268 case PIPE_CAP_ANISOTROPIC_FILTER:
269 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
270 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
271 case PIPE_CAP_SHADER_STENCIL_EXPORT:
272 case PIPE_CAP_TEXTURE_BARRIER:
273 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
274 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
275 case PIPE_CAP_COMPUTE:
276 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
277 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
278 case PIPE_CAP_TGSI_TEXCOORD:
279 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
280 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
281 case PIPE_CAP_TEXTURE_GATHER_SM5:
282 case PIPE_CAP_TEXTURE_QUERY_LOD:
283 case PIPE_CAP_SAMPLE_SHADING:
284 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
285 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
286 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
287 case PIPE_CAP_SAMPLER_VIEW_TARGET:
288 case PIPE_CAP_VERTEXID_NOBASE:
289 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
290 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
291 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
292 case PIPE_CAP_TGSI_TXQS:
293 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
294 case PIPE_CAP_SHAREABLE_SHADERS:
295 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
296 case PIPE_CAP_DRAW_PARAMETERS:
297 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
298 case PIPE_CAP_MULTI_DRAW_INDIRECT:
299 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
300 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
301 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
302 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
303 case PIPE_CAP_INVALIDATE_BUFFER:
304 case PIPE_CAP_GENERATE_MIPMAP:
305 case PIPE_CAP_STRING_MARKER:
306 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
307 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
308 case PIPE_CAP_QUERY_BUFFER_OBJECT:
309 case PIPE_CAP_QUERY_MEMORY_INFO:
310 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
311 case PIPE_CAP_PCI_GROUP:
312 case PIPE_CAP_PCI_BUS:
313 case PIPE_CAP_PCI_DEVICE:
314 case PIPE_CAP_PCI_FUNCTION:
315 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
316 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
317 case PIPE_CAP_TGSI_VOTE:
318 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
319 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
320 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
321 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
322 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
323 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
324 case PIPE_CAP_NATIVE_FENCE_FD:
325 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
326 case PIPE_CAP_TGSI_FS_FBFETCH:
327 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
328 case PIPE_CAP_INT64:
329 case PIPE_CAP_INT64_DIVMOD:
330 case PIPE_CAP_TGSI_TEX_TXF_LZ:
331 case PIPE_CAP_TGSI_CLOCK:
332 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
333 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
334 case PIPE_CAP_TGSI_BALLOT:
335 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
336 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
337 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
338 case PIPE_CAP_POST_DEPTH_COVERAGE:
339 case PIPE_CAP_BINDLESS_TEXTURE:
340 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
341 case PIPE_CAP_QUERY_SO_OVERFLOW:
342 case PIPE_CAP_MEMOBJ:
343 case PIPE_CAP_LOAD_CONSTBUF:
344 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
345 case PIPE_CAP_TILE_RASTER_ORDER:
346 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
347 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
348 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
349 case PIPE_CAP_FENCE_SIGNAL:
350 case PIPE_CAP_CONSTBUF0_FLAGS:
351 case PIPE_CAP_PACKED_UNIFORMS:
352 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
353 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
354 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
355 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
356 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
357 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
358 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
359 return 0;
360
361 case PIPE_CAP_VENDOR_ID:
362 return 0xFFFFFFFF;
363 case PIPE_CAP_DEVICE_ID:
364 return 0xFFFFFFFF;
365 case PIPE_CAP_ACCELERATED:
366 return 0;
367 case PIPE_CAP_VIDEO_MEMORY: {
368 /* XXX: Do we want to return the full amount of system memory ? */
369 uint64_t system_memory;
370
371 if (!os_get_total_physical_memory(&system_memory))
372 return 0;
373
374 return (int)(system_memory >> 20);
375 }
376 }
377
378 /* should only get here on unhandled cases */
379 debug_printf("Unexpected PIPE_CAP %d query\n", param);
380 return 0;
381 }
382
383 static int
384 swr_get_shader_param(struct pipe_screen *screen,
385 enum pipe_shader_type shader,
386 enum pipe_shader_cap param)
387 {
388 if (shader == PIPE_SHADER_VERTEX ||
389 shader == PIPE_SHADER_FRAGMENT ||
390 shader == PIPE_SHADER_GEOMETRY)
391 return gallivm_get_shader_param(param);
392
393 // Todo: tesselation, compute
394 return 0;
395 }
396
397
398 static float
399 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
400 {
401 switch (param) {
402 case PIPE_CAPF_MAX_LINE_WIDTH:
403 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
404 case PIPE_CAPF_MAX_POINT_WIDTH:
405 return 255.0; /* arbitrary */
406 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
407 return 0.0;
408 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
409 return 0.0;
410 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
411 return 16.0; /* arbitrary */
412 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
413 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
414 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
415 return 0.0f;
416 }
417 /* should only get here on unhandled cases */
418 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
419 return 0.0;
420 }
421
422 SWR_FORMAT
423 mesa_to_swr_format(enum pipe_format format)
424 {
425 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
426 /* depth / stencil */
427 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
428 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
429 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
430 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
431 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
432
433 /* alpha */
434 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
435 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
436 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
437 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
438
439 /* odd sizes, bgr */
440 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
441 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
442 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
443 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
444 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
445 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
446 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
447 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
448 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
449
450 /* rgb10a2 */
451 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
452 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
453 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
454 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
455 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
456
457 /* rgb10x2 */
458 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
459
460 /* bgr10a2 */
461 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
462 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
463 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
464 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
465 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
466
467 /* bgr10x2 */
468 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
469
470 /* r11g11b10 */
471 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
472
473 /* 32 bits per component */
474 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
475 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
476 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
477 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
478 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
479
480 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
481 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
482 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
483 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
484
485 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
486 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
487 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
488 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
489
490 {PIPE_FORMAT_R32_UINT, R32_UINT},
491 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
492 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
493 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
494
495 {PIPE_FORMAT_R32_SINT, R32_SINT},
496 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
497 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
498 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
499
500 /* 16 bits per component */
501 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
502 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
503 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
504 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
505 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
506
507 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
508 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
509 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
510 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
511
512 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
513 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
514 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
515 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
516
517 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
518 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
519 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
520 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
521
522 {PIPE_FORMAT_R16_UINT, R16_UINT},
523 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
524 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
525 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
526
527 {PIPE_FORMAT_R16_SINT, R16_SINT},
528 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
529 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
530 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
531
532 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
533 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
534 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
535 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
536 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
537
538 /* 8 bits per component */
539 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
540 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
541 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
542 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
543 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
544 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
545 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
546 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
547
548 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
549 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
550 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
551 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
552
553 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
554 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
555 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
556 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
557
558 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
559 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
560 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
561 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
562
563 {PIPE_FORMAT_R8_UINT, R8_UINT},
564 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
565 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
566 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
567
568 {PIPE_FORMAT_R8_SINT, R8_SINT},
569 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
570 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
571 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
572
573 /* These formats are valid for vertex data, but should not be used
574 * for render targets.
575 */
576
577 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
578 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
579 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
580 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
581
582 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
583 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
584 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
585 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
586
587 /* These formats have entries in SWR but don't have Load/StoreTile
588 * implementations. That means these aren't renderable, and thus having
589 * a mapping entry here is detrimental.
590 */
591 /*
592
593 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
594 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
595 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
596 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
597 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
598
599 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
600 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
601
602 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
603 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
604 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
605
606 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
607 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
608 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
609
610 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
611 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
612 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
613 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
614
615 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
616 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
617 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
618 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
619 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
620 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
621 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
622 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
623
624 {PIPE_FORMAT_I8_UINT, I8_UINT},
625 {PIPE_FORMAT_L8_UINT, L8_UINT},
626 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
627
628 {PIPE_FORMAT_I8_SINT, I8_SINT},
629 {PIPE_FORMAT_L8_SINT, L8_SINT},
630 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
631
632 */
633 };
634
635 auto it = mesa2swr.find(format);
636 if (it == mesa2swr.end())
637 return (SWR_FORMAT)-1;
638 else
639 return it->second;
640 }
641
642 static boolean
643 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
644 {
645 struct sw_winsys *winsys = screen->winsys;
646 struct sw_displaytarget *dt;
647
648 const unsigned width = align(res->swr.width, res->swr.halign);
649 const unsigned height = align(res->swr.height, res->swr.valign);
650
651 UINT stride;
652 dt = winsys->displaytarget_create(winsys,
653 res->base.bind,
654 res->base.format,
655 width, height,
656 64, NULL,
657 &stride);
658
659 if (dt == NULL)
660 return FALSE;
661
662 void *map = winsys->displaytarget_map(winsys, dt, 0);
663
664 res->display_target = dt;
665 res->swr.xpBaseAddress = (gfxptr_t)map;
666
667 /* Clear the display target surface */
668 if (map)
669 memset(map, 0, height * stride);
670
671 winsys->displaytarget_unmap(winsys, dt);
672
673 return TRUE;
674 }
675
676 static bool
677 swr_texture_layout(struct swr_screen *screen,
678 struct swr_resource *res,
679 boolean allocate)
680 {
681 struct pipe_resource *pt = &res->base;
682
683 pipe_format fmt = pt->format;
684 const struct util_format_description *desc = util_format_description(fmt);
685
686 res->has_depth = util_format_has_depth(desc);
687 res->has_stencil = util_format_has_stencil(desc);
688
689 if (res->has_stencil && !res->has_depth)
690 fmt = PIPE_FORMAT_R8_UINT;
691
692 /* We always use the SWR layout. For 2D and 3D textures this looks like:
693 *
694 * |<------- pitch ------->|
695 * +=======================+-------
696 * |Array 0 | ^
697 * | | |
698 * | Level 0 | |
699 * | | |
700 * | | qpitch
701 * +-----------+-----------+ |
702 * | | L2L2L2L2 | |
703 * | Level 1 | L3L3 | |
704 * | | L4 | v
705 * +===========+===========+-------
706 * |Array 1 |
707 * | |
708 * | Level 0 |
709 * | |
710 * | |
711 * +-----------+-----------+
712 * | | L2L2L2L2 |
713 * | Level 1 | L3L3 |
714 * | | L4 |
715 * +===========+===========+
716 *
717 * The overall width in bytes is known as the pitch, while the overall
718 * height in rows is the qpitch. Array slices are laid out logically below
719 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
720 * just invalid for the higher array numbers (since depth is also
721 * minified). 1D and 1D array surfaces are stored effectively the same way,
722 * except that pitch never plays into it. All the levels are logically
723 * adjacent to each other on the X axis. The qpitch becomes the number of
724 * elements between array slices, while the pitch is unused.
725 *
726 * Each level's sizes are subject to the valign and halign settings of the
727 * surface. For compressed formats that swr is unaware of, we will use an
728 * appropriately-sized uncompressed format, and scale the widths/heights.
729 *
730 * This surface is stored inside res->swr. For depth/stencil textures,
731 * res->secondary will have an identically-laid-out but R8_UINT-formatted
732 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
733 * texels, to simplify map/unmap logic which copies the stencil values
734 * in/out.
735 */
736
737 res->swr.width = pt->width0;
738 res->swr.height = pt->height0;
739 res->swr.type = swr_convert_target_type(pt->target);
740 res->swr.tileMode = SWR_TILE_NONE;
741 res->swr.format = mesa_to_swr_format(fmt);
742 res->swr.numSamples = std::max(1u, pt->nr_samples);
743
744 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
745 res->swr.halign = KNOB_MACROTILE_X_DIM;
746 res->swr.valign = KNOB_MACROTILE_Y_DIM;
747
748 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
749 * surface sample count. */
750 if (screen->msaa_force_enable) {
751 res->swr.numSamples = screen->msaa_max_count;
752 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
753 res->swr.numSamples);
754 }
755 } else {
756 res->swr.halign = 1;
757 res->swr.valign = 1;
758 }
759
760 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
761 unsigned width = align(pt->width0, halign);
762 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
763 for (int level = 1; level <= pt->last_level; level++)
764 width += align(u_minify(pt->width0, level), halign);
765 res->swr.pitch = util_format_get_blocksize(fmt);
766 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
767 } else {
768 // The pitch is the overall width of the texture in bytes. Most of the
769 // time this is the pitch of level 0 since all the other levels fit
770 // underneath it. However in some degenerate situations, the width of
771 // level1 + level2 may be larger. In that case, we use those
772 // widths. This can happen if, e.g. halign is 32, and the width of level
773 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
774 // be 32 each, adding up to 64.
775 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
776 if (pt->last_level > 1) {
777 width = std::max<uint32_t>(
778 width,
779 align(u_minify(pt->width0, 1), halign) +
780 align(u_minify(pt->width0, 2), halign));
781 }
782 res->swr.pitch = util_format_get_stride(fmt, width);
783
784 // The qpitch is controlled by either the height of the second LOD, or
785 // the combination of all the later LODs.
786 unsigned height = align(pt->height0, valign);
787 if (pt->last_level == 1) {
788 height += align(u_minify(pt->height0, 1), valign);
789 } else if (pt->last_level > 1) {
790 unsigned level1 = align(u_minify(pt->height0, 1), valign);
791 unsigned level2 = 0;
792 for (int level = 2; level <= pt->last_level; level++) {
793 level2 += align(u_minify(pt->height0, level), valign);
794 }
795 height += std::max(level1, level2);
796 }
797 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
798 }
799
800 if (pt->target == PIPE_TEXTURE_3D)
801 res->swr.depth = pt->depth0;
802 else
803 res->swr.depth = pt->array_size;
804
805 // Fix up swr format if necessary so that LOD offset computation works
806 if (res->swr.format == (SWR_FORMAT)-1) {
807 switch (util_format_get_blocksize(fmt)) {
808 default:
809 unreachable("Unexpected format block size");
810 case 1: res->swr.format = R8_UINT; break;
811 case 2: res->swr.format = R16_UINT; break;
812 case 4: res->swr.format = R32_UINT; break;
813 case 8:
814 if (util_format_is_compressed(fmt))
815 res->swr.format = BC4_UNORM;
816 else
817 res->swr.format = R32G32_UINT;
818 break;
819 case 16:
820 if (util_format_is_compressed(fmt))
821 res->swr.format = BC5_UNORM;
822 else
823 res->swr.format = R32G32B32A32_UINT;
824 break;
825 }
826 }
827
828 for (int level = 0; level <= pt->last_level; level++) {
829 res->mip_offsets[level] =
830 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
831 }
832
833 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
834 res->swr.pitch * res->swr.numSamples;
835 if (total_size > SWR_MAX_TEXTURE_SIZE)
836 return false;
837
838 if (allocate) {
839 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
840 if (!res->swr.xpBaseAddress)
841 return false;
842
843 if (res->has_depth && res->has_stencil) {
844 res->secondary = res->swr;
845 res->secondary.format = R8_UINT;
846 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
847
848 for (int level = 0; level <= pt->last_level; level++) {
849 res->secondary_mip_offsets[level] =
850 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
851 }
852
853 total_size = res->secondary.depth * res->secondary.qpitch *
854 res->secondary.pitch * res->secondary.numSamples;
855
856 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
857 if (!res->secondary.xpBaseAddress) {
858 AlignedFree((void *)res->swr.xpBaseAddress);
859 return false;
860 }
861 }
862 }
863
864 return true;
865 }
866
867 static boolean
868 swr_can_create_resource(struct pipe_screen *screen,
869 const struct pipe_resource *templat)
870 {
871 struct swr_resource res;
872 memset(&res, 0, sizeof(res));
873 res.base = *templat;
874 return swr_texture_layout(swr_screen(screen), &res, false);
875 }
876
877 /* Helper function that conditionally creates a single-sample resolve resource
878 * and attaches it to main multisample resource. */
879 static boolean
880 swr_create_resolve_resource(struct pipe_screen *_screen,
881 struct swr_resource *msaa_res)
882 {
883 struct swr_screen *screen = swr_screen(_screen);
884
885 /* If resource is multisample, create a single-sample resolve resource */
886 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
887 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
888
889 /* Create a single-sample copy of the resource. Copy the original
890 * resource parameters and set flag to prevent recursion when re-calling
891 * resource_create */
892 struct pipe_resource alt_template = msaa_res->base;
893 alt_template.nr_samples = 0;
894 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
895
896 /* Note: Display_target is a special single-sample resource, only the
897 * display_target has been created already. */
898 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
899 | PIPE_BIND_SHARED)) {
900 /* Allocate the multisample buffers. */
901 if (!swr_texture_layout(screen, msaa_res, true))
902 return false;
903
904 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
905 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
906 alt_template.bind = PIPE_BIND_RENDER_TARGET;
907 }
908
909 /* Allocate single-sample resolve surface */
910 struct pipe_resource *alt;
911 alt = _screen->resource_create(_screen, &alt_template);
912 if (!alt)
913 return false;
914
915 /* Attach it to the multisample resource */
916 msaa_res->resolve_target = alt;
917
918 /* Hang resolve surface state off the multisample surface state to so
919 * StoreTiles knows where to resolve the surface. */
920 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
921 }
922
923 return true; /* success */
924 }
925
926 static struct pipe_resource *
927 swr_resource_create(struct pipe_screen *_screen,
928 const struct pipe_resource *templat)
929 {
930 struct swr_screen *screen = swr_screen(_screen);
931 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
932 if (!res)
933 return NULL;
934
935 res->base = *templat;
936 pipe_reference_init(&res->base.reference, 1);
937 res->base.screen = &screen->base;
938
939 if (swr_resource_is_texture(&res->base)) {
940 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
941 | PIPE_BIND_SHARED)) {
942 /* displayable surface
943 * first call swr_texture_layout without allocating to finish
944 * filling out the SWR_SURFACE_STATE in res */
945 swr_texture_layout(screen, res, false);
946 if (!swr_displaytarget_layout(screen, res))
947 goto fail;
948 } else {
949 /* texture map */
950 if (!swr_texture_layout(screen, res, true))
951 goto fail;
952 }
953
954 /* If resource was multisample, create resolve resource and attach
955 * it to multisample resource. */
956 if (!swr_create_resolve_resource(_screen, res))
957 goto fail;
958
959 } else {
960 /* other data (vertex buffer, const buffer, etc) */
961 assert(util_format_get_blocksize(templat->format) == 1);
962 assert(templat->height0 == 1);
963 assert(templat->depth0 == 1);
964 assert(templat->last_level == 0);
965
966 /* Easiest to just call swr_texture_layout, as it sets up
967 * SWR_SURFACE_STATE in res */
968 if (!swr_texture_layout(screen, res, true))
969 goto fail;
970 }
971
972 return &res->base;
973
974 fail:
975 FREE(res);
976 return NULL;
977 }
978
979 static void
980 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
981 {
982 struct swr_screen *screen = swr_screen(p_screen);
983 struct swr_resource *spr = swr_resource(pt);
984
985 if (spr->display_target) {
986 /* If resource is display target, winsys manages the buffer and will
987 * free it on displaytarget_destroy. */
988 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
989
990 struct sw_winsys *winsys = screen->winsys;
991 winsys->displaytarget_destroy(winsys, spr->display_target);
992
993 if (spr->swr.numSamples > 1) {
994 /* Free an attached resolve resource */
995 struct swr_resource *alt = swr_resource(spr->resolve_target);
996 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
997
998 /* Free multisample buffer */
999 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1000 }
1001 } else {
1002 /* For regular resources, defer deletion */
1003 swr_resource_unused(pt);
1004
1005 if (spr->swr.numSamples > 1) {
1006 /* Free an attached resolve resource */
1007 struct swr_resource *alt = swr_resource(spr->resolve_target);
1008 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1009 }
1010
1011 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1012 swr_fence_work_free(screen->flush_fence,
1013 (void*)(spr->secondary.xpBaseAddress), true);
1014
1015 /* If work queue grows too large, submit a fence to force queue to
1016 * drain. This is mainly to decrease the amount of memory used by the
1017 * piglit streaming-texture-leak test */
1018 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1019 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1020 }
1021
1022 FREE(spr);
1023 }
1024
1025
1026 static void
1027 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1028 struct pipe_resource *resource,
1029 unsigned level,
1030 unsigned layer,
1031 void *context_private,
1032 struct pipe_box *sub_box)
1033 {
1034 struct swr_screen *screen = swr_screen(p_screen);
1035 struct sw_winsys *winsys = screen->winsys;
1036 struct swr_resource *spr = swr_resource(resource);
1037 struct pipe_context *pipe = screen->pipe;
1038 struct swr_context *ctx = swr_context(pipe);
1039
1040 if (pipe) {
1041 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1042 swr_resource_unused(resource);
1043 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1044 }
1045
1046 /* Multisample resolved into resolve_target at flush with store_resource */
1047 if (pipe && spr->swr.numSamples > 1) {
1048 struct pipe_resource *resolve_target = spr->resolve_target;
1049
1050 /* Once resolved, copy into display target */
1051 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1052
1053 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1054 PIPE_TRANSFER_WRITE);
1055 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1056 winsys->displaytarget_unmap(winsys, spr->display_target);
1057 }
1058
1059 debug_assert(spr->display_target);
1060 if (spr->display_target)
1061 winsys->displaytarget_display(
1062 winsys, spr->display_target, context_private, sub_box);
1063 }
1064
1065
1066 void
1067 swr_destroy_screen_internal(struct swr_screen **screen)
1068 {
1069 struct pipe_screen *p_screen = &(*screen)->base;
1070
1071 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1072 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1073
1074 JitDestroyContext((*screen)->hJitMgr);
1075
1076 if ((*screen)->pLibrary)
1077 util_dl_close((*screen)->pLibrary);
1078
1079 FREE(*screen);
1080 *screen = NULL;
1081 }
1082
1083
1084 static void
1085 swr_destroy_screen(struct pipe_screen *p_screen)
1086 {
1087 struct swr_screen *screen = swr_screen(p_screen);
1088 struct sw_winsys *winsys = screen->winsys;
1089
1090 fprintf(stderr, "SWR destroy screen!\n");
1091
1092 if (winsys->destroy)
1093 winsys->destroy(winsys);
1094
1095 swr_destroy_screen_internal(&screen);
1096 }
1097
1098
1099 static void
1100 swr_validate_env_options(struct swr_screen *screen)
1101 {
1102 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1103 * copied to scratch space on a draw. Past this, the draw will access
1104 * user-buffer directly and then block. This is faster than queuing many
1105 * large client draws. */
1106 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1107 int client_copy_limit =
1108 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1109 if (client_copy_limit > 0)
1110 screen->client_copy_limit = client_copy_limit;
1111
1112 /* XXX msaa under development, disable by default for now */
1113 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1114
1115 /* validate env override values, within range and power of 2 */
1116 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1117 if (msaa_max_count != 1) {
1118 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1119 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1120 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1121 fprintf(stderr, "must be power of 2 between 1 and %d" \
1122 " (or 1 to disable msaa)\n",
1123 SWR_MAX_NUM_MULTISAMPLES);
1124 msaa_max_count = 1;
1125 }
1126
1127 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1128 if (msaa_max_count == 1)
1129 fprintf(stderr, "(msaa disabled)\n");
1130
1131 screen->msaa_max_count = msaa_max_count;
1132 }
1133
1134 screen->msaa_force_enable = debug_get_bool_option(
1135 "SWR_MSAA_FORCE_ENABLE", false);
1136 if (screen->msaa_force_enable)
1137 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1138 }
1139
1140
1141 PUBLIC
1142 struct pipe_screen *
1143 swr_create_screen_internal(struct sw_winsys *winsys)
1144 {
1145 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1146 memset(screen, 0, sizeof(struct swr_screen));
1147
1148 if (!screen)
1149 return NULL;
1150
1151 if (!lp_build_init()) {
1152 FREE(screen);
1153 return NULL;
1154 }
1155
1156 screen->winsys = winsys;
1157 screen->base.get_name = swr_get_name;
1158 screen->base.get_vendor = swr_get_vendor;
1159 screen->base.is_format_supported = swr_is_format_supported;
1160 screen->base.context_create = swr_create_context;
1161 screen->base.can_create_resource = swr_can_create_resource;
1162
1163 screen->base.destroy = swr_destroy_screen;
1164 screen->base.get_param = swr_get_param;
1165 screen->base.get_shader_param = swr_get_shader_param;
1166 screen->base.get_paramf = swr_get_paramf;
1167
1168 screen->base.resource_create = swr_resource_create;
1169 screen->base.resource_destroy = swr_resource_destroy;
1170
1171 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1172
1173 // Pass in "" for architecture for run-time determination
1174 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1175
1176 swr_fence_init(&screen->base);
1177
1178 swr_validate_env_options(screen);
1179
1180 return &screen->base;
1181 }
1182