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swr/rast: Migrate memory pointers to gfxptr_t type
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 32768
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned bind)
89 {
90 struct swr_screen *screen = swr_screen(_screen);
91 struct sw_winsys *winsys = screen->winsys;
92 const struct util_format_description *format_desc;
93
94 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
95 || target == PIPE_TEXTURE_1D_ARRAY
96 || target == PIPE_TEXTURE_2D
97 || target == PIPE_TEXTURE_2D_ARRAY
98 || target == PIPE_TEXTURE_RECT
99 || target == PIPE_TEXTURE_3D
100 || target == PIPE_TEXTURE_CUBE
101 || target == PIPE_TEXTURE_CUBE_ARRAY);
102
103 format_desc = util_format_description(format);
104 if (!format_desc)
105 return FALSE;
106
107 if ((sample_count > screen->msaa_max_count)
108 || !util_is_power_of_two(sample_count))
109 return FALSE;
110
111 if (bind & PIPE_BIND_DISPLAY_TARGET) {
112 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
113 return FALSE;
114 }
115
116 if (bind & PIPE_BIND_RENDER_TARGET) {
117 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
118 return FALSE;
119
120 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
121 return FALSE;
122
123 /*
124 * Although possible, it is unnatural to render into compressed or YUV
125 * surfaces. So disable these here to avoid going into weird paths
126 * inside the state trackers.
127 */
128 if (format_desc->block.width != 1 || format_desc->block.height != 1)
129 return FALSE;
130 }
131
132 if (bind & PIPE_BIND_DEPTH_STENCIL) {
133 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
134 return FALSE;
135
136 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
137 return FALSE;
138 }
139
140 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
141 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
142 return FALSE;
143 }
144
145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
146 format != PIPE_FORMAT_ETC1_RGB8) {
147 return FALSE;
148 }
149
150 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
151 return util_format_s3tc_enabled;
152 }
153
154 return TRUE;
155 }
156
157 static int
158 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
159 {
160 switch (param) {
161 /* limits */
162 case PIPE_CAP_MAX_RENDER_TARGETS:
163 return PIPE_MAX_COLOR_BUFS;
164 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
165 return SWR_MAX_TEXTURE_2D_LEVELS;
166 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
167 return SWR_MAX_TEXTURE_3D_LEVELS;
168 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
169 return SWR_MAX_TEXTURE_CUBE_LEVELS;
170 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
171 return MAX_SO_STREAMS;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
173 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
174 return MAX_ATTRIBUTES * 4;
175 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
176 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
177 return 1024;
178 case PIPE_CAP_MAX_VERTEX_STREAMS:
179 return 1;
180 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
181 return 2048;
182 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
183 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
184 case PIPE_CAP_MIN_TEXEL_OFFSET:
185 return -8;
186 case PIPE_CAP_MAX_TEXEL_OFFSET:
187 return 7;
188 case PIPE_CAP_GLSL_FEATURE_LEVEL:
189 return 330;
190 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
191 return 16;
192 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
193 return 64;
194 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
195 return 65536;
196 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
197 return 0;
198 case PIPE_CAP_MAX_VIEWPORTS:
199 return 1;
200 case PIPE_CAP_ENDIANNESS:
201 return PIPE_ENDIAN_NATIVE;
202 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
203 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
204 return 0;
205
206 /* supported features */
207 case PIPE_CAP_NPOT_TEXTURES:
208 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
209 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
210 case PIPE_CAP_TWO_SIDED_STENCIL:
211 case PIPE_CAP_SM3:
212 case PIPE_CAP_POINT_SPRITE:
213 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
214 case PIPE_CAP_OCCLUSION_QUERY:
215 case PIPE_CAP_QUERY_TIME_ELAPSED:
216 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
217 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
218 case PIPE_CAP_TEXTURE_SHADOW_MAP:
219 case PIPE_CAP_TEXTURE_SWIZZLE:
220 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
221 case PIPE_CAP_INDEP_BLEND_ENABLE:
222 case PIPE_CAP_INDEP_BLEND_FUNC:
223 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
224 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
225 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
226 case PIPE_CAP_DEPTH_CLIP_DISABLE:
227 case PIPE_CAP_PRIMITIVE_RESTART:
228 case PIPE_CAP_TGSI_INSTANCEID:
229 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
230 case PIPE_CAP_START_INSTANCE:
231 case PIPE_CAP_SEAMLESS_CUBE_MAP:
232 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
233 case PIPE_CAP_CONDITIONAL_RENDER:
234 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
235 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
236 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
237 case PIPE_CAP_USER_VERTEX_BUFFERS:
238 case PIPE_CAP_USER_CONSTANT_BUFFERS:
239 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
240 case PIPE_CAP_QUERY_TIMESTAMP:
241 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
242 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
243 case PIPE_CAP_DRAW_INDIRECT:
244 case PIPE_CAP_UMA:
245 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
246 case PIPE_CAP_CLIP_HALFZ:
247 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
248 case PIPE_CAP_DEPTH_BOUNDS_TEST:
249 case PIPE_CAP_CLEAR_TEXTURE:
250 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
251 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
252 case PIPE_CAP_CULL_DISTANCE:
253 case PIPE_CAP_CUBE_MAP_ARRAY:
254 case PIPE_CAP_DOUBLES:
255 return 1;
256
257 /* MSAA support
258 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
259 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
260 case PIPE_CAP_TEXTURE_MULTISAMPLE:
261 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
262 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
263 case PIPE_CAP_FAKE_SW_MSAA:
264 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
265
266 /* fetch jit change for 2-4GB buffers requires alignment */
267 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
268 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
269 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
270 return 1;
271
272 /* unsupported features */
273 case PIPE_CAP_ANISOTROPIC_FILTER:
274 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
275 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
276 case PIPE_CAP_SHADER_STENCIL_EXPORT:
277 case PIPE_CAP_TEXTURE_BARRIER:
278 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
279 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
280 case PIPE_CAP_COMPUTE:
281 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
282 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
283 case PIPE_CAP_TGSI_TEXCOORD:
284 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
285 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
286 case PIPE_CAP_TEXTURE_GATHER_SM5:
287 case PIPE_CAP_TEXTURE_QUERY_LOD:
288 case PIPE_CAP_SAMPLE_SHADING:
289 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
290 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
291 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
292 case PIPE_CAP_SAMPLER_VIEW_TARGET:
293 case PIPE_CAP_VERTEXID_NOBASE:
294 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
295 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
296 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
297 case PIPE_CAP_TGSI_TXQS:
298 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
299 case PIPE_CAP_SHAREABLE_SHADERS:
300 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
301 case PIPE_CAP_DRAW_PARAMETERS:
302 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
303 case PIPE_CAP_MULTI_DRAW_INDIRECT:
304 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
305 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
306 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
307 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
308 case PIPE_CAP_INVALIDATE_BUFFER:
309 case PIPE_CAP_GENERATE_MIPMAP:
310 case PIPE_CAP_STRING_MARKER:
311 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
312 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
313 case PIPE_CAP_QUERY_BUFFER_OBJECT:
314 case PIPE_CAP_QUERY_MEMORY_INFO:
315 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
316 case PIPE_CAP_PCI_GROUP:
317 case PIPE_CAP_PCI_BUS:
318 case PIPE_CAP_PCI_DEVICE:
319 case PIPE_CAP_PCI_FUNCTION:
320 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
321 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
322 case PIPE_CAP_TGSI_VOTE:
323 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
324 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
325 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
326 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
327 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
328 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
329 case PIPE_CAP_NATIVE_FENCE_FD:
330 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
331 case PIPE_CAP_TGSI_FS_FBFETCH:
332 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
333 case PIPE_CAP_INT64:
334 case PIPE_CAP_INT64_DIVMOD:
335 case PIPE_CAP_TGSI_TEX_TXF_LZ:
336 case PIPE_CAP_TGSI_CLOCK:
337 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
338 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
339 case PIPE_CAP_TGSI_BALLOT:
340 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
341 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
342 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
343 case PIPE_CAP_POST_DEPTH_COVERAGE:
344 case PIPE_CAP_BINDLESS_TEXTURE:
345 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
346 case PIPE_CAP_QUERY_SO_OVERFLOW:
347 case PIPE_CAP_MEMOBJ:
348 return 0;
349
350 case PIPE_CAP_VENDOR_ID:
351 return 0xFFFFFFFF;
352 case PIPE_CAP_DEVICE_ID:
353 return 0xFFFFFFFF;
354 case PIPE_CAP_ACCELERATED:
355 return 0;
356 case PIPE_CAP_VIDEO_MEMORY: {
357 /* XXX: Do we want to return the full amount of system memory ? */
358 uint64_t system_memory;
359
360 if (!os_get_total_physical_memory(&system_memory))
361 return 0;
362
363 return (int)(system_memory >> 20);
364 }
365 }
366
367 /* should only get here on unhandled cases */
368 debug_printf("Unexpected PIPE_CAP %d query\n", param);
369 return 0;
370 }
371
372 static int
373 swr_get_shader_param(struct pipe_screen *screen,
374 enum pipe_shader_type shader,
375 enum pipe_shader_cap param)
376 {
377 if (shader == PIPE_SHADER_VERTEX ||
378 shader == PIPE_SHADER_FRAGMENT ||
379 shader == PIPE_SHADER_GEOMETRY)
380 return gallivm_get_shader_param(param);
381
382 // Todo: tesselation, compute
383 return 0;
384 }
385
386
387 static float
388 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
389 {
390 switch (param) {
391 case PIPE_CAPF_MAX_LINE_WIDTH:
392 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
393 case PIPE_CAPF_MAX_POINT_WIDTH:
394 return 255.0; /* arbitrary */
395 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
396 return 0.0;
397 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
398 return 0.0;
399 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
400 return 16.0; /* arbitrary */
401 case PIPE_CAPF_GUARD_BAND_LEFT:
402 case PIPE_CAPF_GUARD_BAND_TOP:
403 case PIPE_CAPF_GUARD_BAND_RIGHT:
404 case PIPE_CAPF_GUARD_BAND_BOTTOM:
405 return 0.0;
406 }
407 /* should only get here on unhandled cases */
408 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
409 return 0.0;
410 }
411
412 SWR_FORMAT
413 mesa_to_swr_format(enum pipe_format format)
414 {
415 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
416 /* depth / stencil */
417 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
418 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
419 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
420 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
421 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
422
423 /* alpha */
424 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
425 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
426 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
427 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
428
429 /* odd sizes, bgr */
430 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
431 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
432 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
433 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
434 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
435 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
436 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
437 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
438 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
439
440 /* rgb10a2 */
441 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
442 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
443 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
444 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
445 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
446
447 /* rgb10x2 */
448 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
449
450 /* bgr10a2 */
451 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
452 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
453 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
454 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
455 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
456
457 /* bgr10x2 */
458 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
459
460 /* r11g11b10 */
461 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
462
463 /* 32 bits per component */
464 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
465 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
466 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
467 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
468 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
469
470 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
471 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
472 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
473 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
474
475 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
476 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
477 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
478 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
479
480 {PIPE_FORMAT_R32_UINT, R32_UINT},
481 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
482 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
483 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
484
485 {PIPE_FORMAT_R32_SINT, R32_SINT},
486 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
487 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
488 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
489
490 /* 16 bits per component */
491 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
492 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
493 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
494 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
495 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
496
497 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
498 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
499 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
500 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
501
502 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
503 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
504 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
505 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
506
507 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
508 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
509 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
510 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
511
512 {PIPE_FORMAT_R16_UINT, R16_UINT},
513 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
514 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
515 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
516
517 {PIPE_FORMAT_R16_SINT, R16_SINT},
518 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
519 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
520 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
521
522 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
523 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
524 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
525 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
526 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
527
528 /* 8 bits per component */
529 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
530 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
531 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
532 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
533 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
534 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
535 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
536 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
537
538 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
539 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
540 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
541 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
542
543 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
544 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
545 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
546 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
547
548 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
549 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
550 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
551 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
552
553 {PIPE_FORMAT_R8_UINT, R8_UINT},
554 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
555 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
556 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
557
558 {PIPE_FORMAT_R8_SINT, R8_SINT},
559 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
560 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
561 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
562
563 /* These formats are valid for vertex data, but should not be used
564 * for render targets.
565 */
566
567 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
568 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
569 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
570 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
571
572 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
573 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
574 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
575 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
576
577 /* These formats have entries in SWR but don't have Load/StoreTile
578 * implementations. That means these aren't renderable, and thus having
579 * a mapping entry here is detrimental.
580 */
581 /*
582
583 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
584 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
585 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
586 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
587 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
588
589 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
590 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
591
592 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
593 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
594 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
595
596 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
597 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
598 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
599
600 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
601 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
602 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
603 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
604
605 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
606 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
607 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
608 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
609 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
610 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
611 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
612 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
613
614 {PIPE_FORMAT_I8_UINT, I8_UINT},
615 {PIPE_FORMAT_L8_UINT, L8_UINT},
616 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
617
618 {PIPE_FORMAT_I8_SINT, I8_SINT},
619 {PIPE_FORMAT_L8_SINT, L8_SINT},
620 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
621
622 */
623 };
624
625 auto it = mesa2swr.find(format);
626 if (it == mesa2swr.end())
627 return (SWR_FORMAT)-1;
628 else
629 return it->second;
630 }
631
632 static boolean
633 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
634 {
635 struct sw_winsys *winsys = screen->winsys;
636 struct sw_displaytarget *dt;
637
638 const unsigned width = align(res->swr.width, res->swr.halign);
639 const unsigned height = align(res->swr.height, res->swr.valign);
640
641 UINT stride;
642 dt = winsys->displaytarget_create(winsys,
643 res->base.bind,
644 res->base.format,
645 width, height,
646 64, NULL,
647 &stride);
648
649 if (dt == NULL)
650 return FALSE;
651
652 void *map = winsys->displaytarget_map(winsys, dt, 0);
653
654 res->display_target = dt;
655 res->swr.xpBaseAddress = (gfxptr_t)map;
656
657 /* Clear the display target surface */
658 if (map)
659 memset(map, 0, height * stride);
660
661 winsys->displaytarget_unmap(winsys, dt);
662
663 return TRUE;
664 }
665
666 static bool
667 swr_texture_layout(struct swr_screen *screen,
668 struct swr_resource *res,
669 boolean allocate)
670 {
671 struct pipe_resource *pt = &res->base;
672
673 pipe_format fmt = pt->format;
674 const struct util_format_description *desc = util_format_description(fmt);
675
676 res->has_depth = util_format_has_depth(desc);
677 res->has_stencil = util_format_has_stencil(desc);
678
679 if (res->has_stencil && !res->has_depth)
680 fmt = PIPE_FORMAT_R8_UINT;
681
682 /* We always use the SWR layout. For 2D and 3D textures this looks like:
683 *
684 * |<------- pitch ------->|
685 * +=======================+-------
686 * |Array 0 | ^
687 * | | |
688 * | Level 0 | |
689 * | | |
690 * | | qpitch
691 * +-----------+-----------+ |
692 * | | L2L2L2L2 | |
693 * | Level 1 | L3L3 | |
694 * | | L4 | v
695 * +===========+===========+-------
696 * |Array 1 |
697 * | |
698 * | Level 0 |
699 * | |
700 * | |
701 * +-----------+-----------+
702 * | | L2L2L2L2 |
703 * | Level 1 | L3L3 |
704 * | | L4 |
705 * +===========+===========+
706 *
707 * The overall width in bytes is known as the pitch, while the overall
708 * height in rows is the qpitch. Array slices are laid out logically below
709 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
710 * just invalid for the higher array numbers (since depth is also
711 * minified). 1D and 1D array surfaces are stored effectively the same way,
712 * except that pitch never plays into it. All the levels are logically
713 * adjacent to each other on the X axis. The qpitch becomes the number of
714 * elements between array slices, while the pitch is unused.
715 *
716 * Each level's sizes are subject to the valign and halign settings of the
717 * surface. For compressed formats that swr is unaware of, we will use an
718 * appropriately-sized uncompressed format, and scale the widths/heights.
719 *
720 * This surface is stored inside res->swr. For depth/stencil textures,
721 * res->secondary will have an identically-laid-out but R8_UINT-formatted
722 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
723 * texels, to simplify map/unmap logic which copies the stencil values
724 * in/out.
725 */
726
727 res->swr.width = pt->width0;
728 res->swr.height = pt->height0;
729 res->swr.type = swr_convert_target_type(pt->target);
730 res->swr.tileMode = SWR_TILE_NONE;
731 res->swr.format = mesa_to_swr_format(fmt);
732 res->swr.numSamples = std::max(1u, pt->nr_samples);
733
734 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
735 res->swr.halign = KNOB_MACROTILE_X_DIM;
736 res->swr.valign = KNOB_MACROTILE_Y_DIM;
737
738 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
739 * surface sample count. */
740 if (screen->msaa_force_enable) {
741 res->swr.numSamples = screen->msaa_max_count;
742 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
743 res->swr.numSamples);
744 }
745 } else {
746 res->swr.halign = 1;
747 res->swr.valign = 1;
748 }
749
750 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
751 unsigned width = align(pt->width0, halign);
752 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
753 for (int level = 1; level <= pt->last_level; level++)
754 width += align(u_minify(pt->width0, level), halign);
755 res->swr.pitch = util_format_get_blocksize(fmt);
756 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
757 } else {
758 // The pitch is the overall width of the texture in bytes. Most of the
759 // time this is the pitch of level 0 since all the other levels fit
760 // underneath it. However in some degenerate situations, the width of
761 // level1 + level2 may be larger. In that case, we use those
762 // widths. This can happen if, e.g. halign is 32, and the width of level
763 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
764 // be 32 each, adding up to 64.
765 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
766 if (pt->last_level > 1) {
767 width = std::max<uint32_t>(
768 width,
769 align(u_minify(pt->width0, 1), halign) +
770 align(u_minify(pt->width0, 2), halign));
771 }
772 res->swr.pitch = util_format_get_stride(fmt, width);
773
774 // The qpitch is controlled by either the height of the second LOD, or
775 // the combination of all the later LODs.
776 unsigned height = align(pt->height0, valign);
777 if (pt->last_level == 1) {
778 height += align(u_minify(pt->height0, 1), valign);
779 } else if (pt->last_level > 1) {
780 unsigned level1 = align(u_minify(pt->height0, 1), valign);
781 unsigned level2 = 0;
782 for (int level = 2; level <= pt->last_level; level++) {
783 level2 += align(u_minify(pt->height0, level), valign);
784 }
785 height += std::max(level1, level2);
786 }
787 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
788 }
789
790 if (pt->target == PIPE_TEXTURE_3D)
791 res->swr.depth = pt->depth0;
792 else
793 res->swr.depth = pt->array_size;
794
795 // Fix up swr format if necessary so that LOD offset computation works
796 if (res->swr.format == (SWR_FORMAT)-1) {
797 switch (util_format_get_blocksize(fmt)) {
798 default:
799 unreachable("Unexpected format block size");
800 case 1: res->swr.format = R8_UINT; break;
801 case 2: res->swr.format = R16_UINT; break;
802 case 4: res->swr.format = R32_UINT; break;
803 case 8:
804 if (util_format_is_compressed(fmt))
805 res->swr.format = BC4_UNORM;
806 else
807 res->swr.format = R32G32_UINT;
808 break;
809 case 16:
810 if (util_format_is_compressed(fmt))
811 res->swr.format = BC5_UNORM;
812 else
813 res->swr.format = R32G32B32A32_UINT;
814 break;
815 }
816 }
817
818 for (int level = 0; level <= pt->last_level; level++) {
819 res->mip_offsets[level] =
820 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
821 }
822
823 size_t total_size = res->swr.depth * res->swr.qpitch * res->swr.pitch *
824 res->swr.numSamples;
825 if (total_size > SWR_MAX_TEXTURE_SIZE)
826 return false;
827
828 if (allocate) {
829 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
830
831 if (res->has_depth && res->has_stencil) {
832 res->secondary = res->swr;
833 res->secondary.format = R8_UINT;
834 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
835
836 for (int level = 0; level <= pt->last_level; level++) {
837 res->secondary_mip_offsets[level] =
838 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
839 }
840
841 total_size = res->secondary.depth * res->secondary.qpitch *
842 res->secondary.pitch * res->secondary.numSamples;
843
844 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
845 }
846 }
847
848 return true;
849 }
850
851 static boolean
852 swr_can_create_resource(struct pipe_screen *screen,
853 const struct pipe_resource *templat)
854 {
855 struct swr_resource res;
856 memset(&res, 0, sizeof(res));
857 res.base = *templat;
858 return swr_texture_layout(swr_screen(screen), &res, false);
859 }
860
861 /* Helper function that conditionally creates a single-sample resolve resource
862 * and attaches it to main multisample resource. */
863 static boolean
864 swr_create_resolve_resource(struct pipe_screen *_screen,
865 struct swr_resource *msaa_res)
866 {
867 struct swr_screen *screen = swr_screen(_screen);
868
869 /* If resource is multisample, create a single-sample resolve resource */
870 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
871 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
872
873 /* Create a single-sample copy of the resource. Copy the original
874 * resource parameters and set flag to prevent recursion when re-calling
875 * resource_create */
876 struct pipe_resource alt_template = msaa_res->base;
877 alt_template.nr_samples = 0;
878 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
879
880 /* Note: Display_target is a special single-sample resource, only the
881 * display_target has been created already. */
882 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
883 | PIPE_BIND_SHARED)) {
884 /* Allocate the multisample buffers. */
885 if (!swr_texture_layout(screen, msaa_res, true))
886 return false;
887
888 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
889 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
890 alt_template.bind = PIPE_BIND_RENDER_TARGET;
891 }
892
893 /* Allocate single-sample resolve surface */
894 struct pipe_resource *alt;
895 alt = _screen->resource_create(_screen, &alt_template);
896 if (!alt)
897 return false;
898
899 /* Attach it to the multisample resource */
900 msaa_res->resolve_target = alt;
901
902 /* Hang resolve surface state off the multisample surface state to so
903 * StoreTiles knows where to resolve the surface. */
904 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
905 }
906
907 return true; /* success */
908 }
909
910 static struct pipe_resource *
911 swr_resource_create(struct pipe_screen *_screen,
912 const struct pipe_resource *templat)
913 {
914 struct swr_screen *screen = swr_screen(_screen);
915 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
916 if (!res)
917 return NULL;
918
919 res->base = *templat;
920 pipe_reference_init(&res->base.reference, 1);
921 res->base.screen = &screen->base;
922
923 if (swr_resource_is_texture(&res->base)) {
924 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
925 | PIPE_BIND_SHARED)) {
926 /* displayable surface
927 * first call swr_texture_layout without allocating to finish
928 * filling out the SWR_SURFACE_STATE in res */
929 swr_texture_layout(screen, res, false);
930 if (!swr_displaytarget_layout(screen, res))
931 goto fail;
932 } else {
933 /* texture map */
934 if (!swr_texture_layout(screen, res, true))
935 goto fail;
936 }
937
938 /* If resource was multisample, create resolve resource and attach
939 * it to multisample resource. */
940 if (!swr_create_resolve_resource(_screen, res))
941 goto fail;
942
943 } else {
944 /* other data (vertex buffer, const buffer, etc) */
945 assert(util_format_get_blocksize(templat->format) == 1);
946 assert(templat->height0 == 1);
947 assert(templat->depth0 == 1);
948 assert(templat->last_level == 0);
949
950 /* Easiest to just call swr_texture_layout, as it sets up
951 * SWR_SURFACE_STATE in res */
952 if (!swr_texture_layout(screen, res, true))
953 goto fail;
954 }
955
956 return &res->base;
957
958 fail:
959 FREE(res);
960 return NULL;
961 }
962
963 static void
964 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
965 {
966 struct swr_screen *screen = swr_screen(p_screen);
967 struct swr_resource *spr = swr_resource(pt);
968
969 if (spr->display_target) {
970 /* If resource is display target, winsys manages the buffer and will
971 * free it on displaytarget_destroy. */
972 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
973
974 struct sw_winsys *winsys = screen->winsys;
975 winsys->displaytarget_destroy(winsys, spr->display_target);
976
977 if (spr->swr.numSamples > 1) {
978 /* Free an attached resolve resource */
979 struct swr_resource *alt = swr_resource(spr->resolve_target);
980 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
981
982 /* Free multisample buffer */
983 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
984 }
985 } else {
986 /* For regular resources, defer deletion */
987 swr_resource_unused(pt);
988
989 if (spr->swr.numSamples > 1) {
990 /* Free an attached resolve resource */
991 struct swr_resource *alt = swr_resource(spr->resolve_target);
992 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
993 }
994
995 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
996 swr_fence_work_free(screen->flush_fence,
997 (void*)(spr->secondary.xpBaseAddress), true);
998
999 /* If work queue grows too large, submit a fence to force queue to
1000 * drain. This is mainly to decrease the amount of memory used by the
1001 * piglit streaming-texture-leak test */
1002 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1003 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1004 }
1005
1006 FREE(spr);
1007 }
1008
1009
1010 static void
1011 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1012 struct pipe_resource *resource,
1013 unsigned level,
1014 unsigned layer,
1015 void *context_private,
1016 struct pipe_box *sub_box)
1017 {
1018 struct swr_screen *screen = swr_screen(p_screen);
1019 struct sw_winsys *winsys = screen->winsys;
1020 struct swr_resource *spr = swr_resource(resource);
1021 struct pipe_context *pipe = screen->pipe;
1022 struct swr_context *ctx = swr_context(pipe);
1023
1024 if (pipe) {
1025 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1026 swr_resource_unused(resource);
1027 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1028 }
1029
1030 /* Multisample resolved into resolve_target at flush with store_resource */
1031 if (pipe && spr->swr.numSamples > 1) {
1032 struct pipe_resource *resolve_target = spr->resolve_target;
1033
1034 /* Once resolved, copy into display target */
1035 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1036
1037 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1038 PIPE_TRANSFER_WRITE);
1039 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1040 winsys->displaytarget_unmap(winsys, spr->display_target);
1041 }
1042
1043 debug_assert(spr->display_target);
1044 if (spr->display_target)
1045 winsys->displaytarget_display(
1046 winsys, spr->display_target, context_private, sub_box);
1047 }
1048
1049
1050 static void
1051 swr_destroy_screen(struct pipe_screen *p_screen)
1052 {
1053 struct swr_screen *screen = swr_screen(p_screen);
1054 struct sw_winsys *winsys = screen->winsys;
1055
1056 fprintf(stderr, "SWR destroy screen!\n");
1057
1058 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1059 swr_fence_reference(p_screen, &screen->flush_fence, NULL);
1060
1061 JitDestroyContext(screen->hJitMgr);
1062
1063 if (winsys->destroy)
1064 winsys->destroy(winsys);
1065
1066 FREE(screen);
1067 }
1068
1069
1070 static void
1071 swr_validate_env_options(struct swr_screen *screen)
1072 {
1073 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1074 * copied to scratch space on a draw. Past this, the draw will access
1075 * user-buffer directly and then block. This is faster than queuing many
1076 * large client draws. */
1077 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1078 int client_copy_limit =
1079 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1080 if (client_copy_limit > 0)
1081 screen->client_copy_limit = client_copy_limit;
1082
1083 /* XXX msaa under development, disable by default for now */
1084 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1085
1086 /* validate env override values, within range and power of 2 */
1087 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1088 if (msaa_max_count != 1) {
1089 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1090 || !util_is_power_of_two(msaa_max_count)) {
1091 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1092 fprintf(stderr, "must be power of 2 between 1 and %d" \
1093 " (or 1 to disable msaa)\n",
1094 SWR_MAX_NUM_MULTISAMPLES);
1095 msaa_max_count = 1;
1096 }
1097
1098 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1099 if (msaa_max_count == 1)
1100 fprintf(stderr, "(msaa disabled)\n");
1101
1102 screen->msaa_max_count = msaa_max_count;
1103 }
1104
1105 screen->msaa_force_enable = debug_get_bool_option(
1106 "SWR_MSAA_FORCE_ENABLE", false);
1107 if (screen->msaa_force_enable)
1108 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1109 }
1110
1111
1112 PUBLIC
1113 struct pipe_screen *
1114 swr_create_screen_internal(struct sw_winsys *winsys)
1115 {
1116 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1117
1118 if (!screen)
1119 return NULL;
1120
1121 if (!lp_build_init()) {
1122 FREE(screen);
1123 return NULL;
1124 }
1125
1126 screen->winsys = winsys;
1127 screen->base.get_name = swr_get_name;
1128 screen->base.get_vendor = swr_get_vendor;
1129 screen->base.is_format_supported = swr_is_format_supported;
1130 screen->base.context_create = swr_create_context;
1131 screen->base.can_create_resource = swr_can_create_resource;
1132
1133 screen->base.destroy = swr_destroy_screen;
1134 screen->base.get_param = swr_get_param;
1135 screen->base.get_shader_param = swr_get_shader_param;
1136 screen->base.get_paramf = swr_get_paramf;
1137
1138 screen->base.resource_create = swr_resource_create;
1139 screen->base.resource_destroy = swr_resource_destroy;
1140
1141 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1142
1143 // Pass in "" for architecture for run-time determination
1144 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1145
1146 swr_fence_init(&screen->base);
1147
1148 util_format_s3tc_init();
1149
1150 swr_validate_env_options(screen);
1151
1152 return &screen->base;
1153 }
1154