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swr: rework resource layout and surface setup
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38
39 #include "state_tracker/sw_winsys.h"
40
41 extern "C" {
42 #include "gallivm/lp_bld_limits.h"
43 }
44
45 #include "jit_api.h"
46
47 #include "memory/TilingFunctions.h"
48
49 #include <stdio.h>
50 #include <map>
51
52 /* MSVC case instensitive compare */
53 #if defined(PIPE_CC_MSVC)
54 #define strcasecmp lstrcmpiA
55 #endif
56
57 /*
58 * Max texture sizes
59 * XXX Check max texture size values against core and sampler.
60 */
61 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
62 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
63 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
64 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
65 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 return "SWR";
71 }
72
73 static const char *
74 swr_get_vendor(struct pipe_screen *screen)
75 {
76 return "Intel Corporation";
77 }
78
79 static boolean
80 swr_is_format_supported(struct pipe_screen *screen,
81 enum pipe_format format,
82 enum pipe_texture_target target,
83 unsigned sample_count,
84 unsigned bind)
85 {
86 struct sw_winsys *winsys = swr_screen(screen)->winsys;
87 const struct util_format_description *format_desc;
88
89 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
90 || target == PIPE_TEXTURE_1D_ARRAY
91 || target == PIPE_TEXTURE_2D
92 || target == PIPE_TEXTURE_2D_ARRAY
93 || target == PIPE_TEXTURE_RECT
94 || target == PIPE_TEXTURE_3D
95 || target == PIPE_TEXTURE_CUBE
96 || target == PIPE_TEXTURE_CUBE_ARRAY);
97
98 format_desc = util_format_description(format);
99 if (!format_desc)
100 return FALSE;
101
102 if (sample_count > 1)
103 return FALSE;
104
105 if (bind
106 & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) {
107 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
108 return FALSE;
109 }
110
111 if (bind & PIPE_BIND_RENDER_TARGET) {
112 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
113 return FALSE;
114
115 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
116 return FALSE;
117
118 /*
119 * Although possible, it is unnatural to render into compressed or YUV
120 * surfaces. So disable these here to avoid going into weird paths
121 * inside the state trackers.
122 */
123 if (format_desc->block.width != 1 || format_desc->block.height != 1)
124 return FALSE;
125 }
126
127 if (bind & PIPE_BIND_DEPTH_STENCIL) {
128 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
129 return FALSE;
130
131 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
132 return FALSE;
133 }
134
135 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
136 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
137 return FALSE;
138 }
139
140 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
141 format != PIPE_FORMAT_ETC1_RGB8) {
142 return FALSE;
143 }
144
145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
146 return util_format_s3tc_enabled;
147 }
148
149 return TRUE;
150 }
151
152 static int
153 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
154 {
155 switch (param) {
156 case PIPE_CAP_NPOT_TEXTURES:
157 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
158 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
159 return 1;
160 case PIPE_CAP_TWO_SIDED_STENCIL:
161 return 1;
162 case PIPE_CAP_SM3:
163 return 1;
164 case PIPE_CAP_ANISOTROPIC_FILTER:
165 return 0;
166 case PIPE_CAP_POINT_SPRITE:
167 return 1;
168 case PIPE_CAP_MAX_RENDER_TARGETS:
169 return PIPE_MAX_COLOR_BUFS;
170 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
171 return 1;
172 case PIPE_CAP_OCCLUSION_QUERY:
173 case PIPE_CAP_QUERY_TIME_ELAPSED:
174 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
175 return 1;
176 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
177 return 1;
178 case PIPE_CAP_TEXTURE_SHADOW_MAP:
179 return 1;
180 case PIPE_CAP_TEXTURE_SWIZZLE:
181 return 1;
182 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
183 return 0;
184 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
185 return SWR_MAX_TEXTURE_2D_LEVELS;
186 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
187 return SWR_MAX_TEXTURE_3D_LEVELS;
188 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
189 return SWR_MAX_TEXTURE_CUBE_LEVELS;
190 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
191 return 1;
192 case PIPE_CAP_INDEP_BLEND_ENABLE:
193 return 1;
194 case PIPE_CAP_INDEP_BLEND_FUNC:
195 return 1;
196 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
197 return 0; // Don't support lower left frag coord.
198 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
199 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
200 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
201 return 1;
202 case PIPE_CAP_DEPTH_CLIP_DISABLE:
203 return 1;
204 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
205 return MAX_SO_STREAMS;
206 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
207 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
208 return MAX_ATTRIBUTES;
209 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
210 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
211 return 1024;
212 case PIPE_CAP_MAX_VERTEX_STREAMS:
213 return 1;
214 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
215 return 2048;
216 case PIPE_CAP_PRIMITIVE_RESTART:
217 return 1;
218 case PIPE_CAP_SHADER_STENCIL_EXPORT:
219 return 0;
220 case PIPE_CAP_TGSI_INSTANCEID:
221 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
222 case PIPE_CAP_START_INSTANCE:
223 return 1;
224 case PIPE_CAP_SEAMLESS_CUBE_MAP:
225 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
226 return 1;
227 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
228 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
229 case PIPE_CAP_MIN_TEXEL_OFFSET:
230 return -8;
231 case PIPE_CAP_MAX_TEXEL_OFFSET:
232 return 7;
233 case PIPE_CAP_CONDITIONAL_RENDER:
234 return 1;
235 case PIPE_CAP_TEXTURE_BARRIER:
236 return 0;
237 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
238 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
239 return 0;
240 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
241 return 1;
242 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
243 return 1;
244 case PIPE_CAP_GLSL_FEATURE_LEVEL:
245 return 330;
246 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
247 return 1;
248 case PIPE_CAP_COMPUTE:
249 return 0;
250 case PIPE_CAP_USER_VERTEX_BUFFERS:
251 case PIPE_CAP_USER_INDEX_BUFFERS:
252 case PIPE_CAP_USER_CONSTANT_BUFFERS:
253 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
254 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
255 return 1;
256 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
257 return 16;
258 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
259 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
260 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
261 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
262 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
263 case PIPE_CAP_TEXTURE_MULTISAMPLE:
264 return 0;
265 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
266 return 64;
267 case PIPE_CAP_QUERY_TIMESTAMP:
268 return 1;
269 case PIPE_CAP_CUBE_MAP_ARRAY:
270 return 0;
271 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
272 return 1;
273 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
274 return 65536;
275 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
276 return 0;
277 case PIPE_CAP_TGSI_TEXCOORD:
278 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
279 return 0;
280 case PIPE_CAP_MAX_VIEWPORTS:
281 return 1;
282 case PIPE_CAP_ENDIANNESS:
283 return PIPE_ENDIAN_NATIVE;
284 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
285 case PIPE_CAP_TEXTURE_GATHER_SM5:
286 return 0;
287 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
288 return 1;
289 case PIPE_CAP_TEXTURE_QUERY_LOD:
290 case PIPE_CAP_SAMPLE_SHADING:
291 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
292 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
293 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
294 case PIPE_CAP_SAMPLER_VIEW_TARGET:
295 return 0;
296 case PIPE_CAP_FAKE_SW_MSAA:
297 return 1;
298 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
299 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
300 return 0;
301 case PIPE_CAP_DRAW_INDIRECT:
302 return 1;
303
304 case PIPE_CAP_VENDOR_ID:
305 return 0xFFFFFFFF;
306 case PIPE_CAP_DEVICE_ID:
307 return 0xFFFFFFFF;
308 case PIPE_CAP_ACCELERATED:
309 return 0;
310 case PIPE_CAP_VIDEO_MEMORY: {
311 /* XXX: Do we want to return the full amount of system memory ? */
312 uint64_t system_memory;
313
314 if (!os_get_total_physical_memory(&system_memory))
315 return 0;
316
317 return (int)(system_memory >> 20);
318 }
319 case PIPE_CAP_UMA:
320 return 1;
321 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
322 return 1;
323 case PIPE_CAP_CLIP_HALFZ:
324 return 1;
325 case PIPE_CAP_VERTEXID_NOBASE:
326 return 0;
327 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
328 return 1;
329 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
330 return 0;
331 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
332 return 0; // xxx
333 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
334 return 0;
335 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
336 return 0;
337 case PIPE_CAP_DEPTH_BOUNDS_TEST:
338 return 1;
339 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
340 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
341 return 1;
342 case PIPE_CAP_CULL_DISTANCE:
343 return 1;
344 case PIPE_CAP_TGSI_TXQS:
345 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
346 case PIPE_CAP_SHAREABLE_SHADERS:
347 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
348 case PIPE_CAP_CLEAR_TEXTURE:
349 case PIPE_CAP_DRAW_PARAMETERS:
350 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
351 case PIPE_CAP_MULTI_DRAW_INDIRECT:
352 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
353 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
354 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
355 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
356 case PIPE_CAP_INVALIDATE_BUFFER:
357 case PIPE_CAP_GENERATE_MIPMAP:
358 case PIPE_CAP_STRING_MARKER:
359 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
360 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
361 case PIPE_CAP_QUERY_BUFFER_OBJECT:
362 case PIPE_CAP_QUERY_MEMORY_INFO:
363 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
364 case PIPE_CAP_PCI_GROUP:
365 case PIPE_CAP_PCI_BUS:
366 case PIPE_CAP_PCI_DEVICE:
367 case PIPE_CAP_PCI_FUNCTION:
368 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
369 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
370 case PIPE_CAP_TGSI_VOTE:
371 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
372 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
373 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
374 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
375 return 0;
376 }
377
378 /* should only get here on unhandled cases */
379 debug_printf("Unexpected PIPE_CAP %d query\n", param);
380 return 0;
381 }
382
383 static int
384 swr_get_shader_param(struct pipe_screen *screen,
385 unsigned shader,
386 enum pipe_shader_cap param)
387 {
388 if (shader == PIPE_SHADER_VERTEX || shader == PIPE_SHADER_FRAGMENT)
389 return gallivm_get_shader_param(param);
390
391 // Todo: geometry, tesselation, compute
392 return 0;
393 }
394
395
396 static float
397 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
398 {
399 switch (param) {
400 case PIPE_CAPF_MAX_LINE_WIDTH:
401 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
402 case PIPE_CAPF_MAX_POINT_WIDTH:
403 return 255.0; /* arbitrary */
404 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
405 return 0.0;
406 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
407 return 0.0;
408 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
409 return 0.0;
410 case PIPE_CAPF_GUARD_BAND_LEFT:
411 case PIPE_CAPF_GUARD_BAND_TOP:
412 case PIPE_CAPF_GUARD_BAND_RIGHT:
413 case PIPE_CAPF_GUARD_BAND_BOTTOM:
414 return 0.0;
415 }
416 /* should only get here on unhandled cases */
417 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
418 return 0.0;
419 }
420
421 SWR_FORMAT
422 mesa_to_swr_format(enum pipe_format format)
423 {
424 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
425 {PIPE_FORMAT_NONE, (SWR_FORMAT)-1},
426 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
427 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
428 {PIPE_FORMAT_A8R8G8B8_UNORM, (SWR_FORMAT)-1},
429 {PIPE_FORMAT_X8R8G8B8_UNORM, (SWR_FORMAT)-1},
430 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
431 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
432 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
433 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
434 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
435 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
436 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
437 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
438 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
439 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
440 {PIPE_FORMAT_YUYV, (SWR_FORMAT)-1},
441 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
442 {PIPE_FORMAT_Z32_UNORM, (SWR_FORMAT)-1},
443 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
444 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
445 {PIPE_FORMAT_S8_UINT_Z24_UNORM, (SWR_FORMAT)-1},
446 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
447 {PIPE_FORMAT_X8Z24_UNORM, (SWR_FORMAT)-1},
448 {PIPE_FORMAT_S8_UINT, (SWR_FORMAT)-1},
449 {PIPE_FORMAT_R64_FLOAT, (SWR_FORMAT)-1},
450 {PIPE_FORMAT_R64G64_FLOAT, (SWR_FORMAT)-1},
451 {PIPE_FORMAT_R64G64B64_FLOAT, (SWR_FORMAT)-1},
452 {PIPE_FORMAT_R64G64B64A64_FLOAT, (SWR_FORMAT)-1},
453 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
454 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
455 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
456 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
457 {PIPE_FORMAT_R32_UNORM, (SWR_FORMAT)-1},
458 {PIPE_FORMAT_R32G32_UNORM, (SWR_FORMAT)-1},
459 {PIPE_FORMAT_R32G32B32_UNORM, (SWR_FORMAT)-1},
460 {PIPE_FORMAT_R32G32B32A32_UNORM, (SWR_FORMAT)-1},
461 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
462 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
463 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
464 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
465 {PIPE_FORMAT_R32_SNORM, (SWR_FORMAT)-1},
466 {PIPE_FORMAT_R32G32_SNORM, (SWR_FORMAT)-1},
467 {PIPE_FORMAT_R32G32B32_SNORM, (SWR_FORMAT)-1},
468 {PIPE_FORMAT_R32G32B32A32_SNORM, (SWR_FORMAT)-1},
469 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
470 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
471 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
472 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
473 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
474 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
475 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
476 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
477 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
478 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
479 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
480 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
481 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
482 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
483 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
484 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
485 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
486 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
487 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
488 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
489 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
490 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
491 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
492 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
493 {PIPE_FORMAT_X8B8G8R8_UNORM, (SWR_FORMAT)-1},
494 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
495 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
496 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
497 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
498 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
499 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
500 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
501 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
502 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
503 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
504 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
505 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
506 {PIPE_FORMAT_R32_FIXED, (SWR_FORMAT)-1},
507 {PIPE_FORMAT_R32G32_FIXED, (SWR_FORMAT)-1},
508 {PIPE_FORMAT_R32G32B32_FIXED, (SWR_FORMAT)-1},
509 {PIPE_FORMAT_R32G32B32A32_FIXED, (SWR_FORMAT)-1},
510 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
511 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
512 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
513 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
514
515 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
516 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
517 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
518 {PIPE_FORMAT_A8B8G8R8_SRGB, (SWR_FORMAT)-1},
519 {PIPE_FORMAT_X8B8G8R8_SRGB, (SWR_FORMAT)-1},
520 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
521 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
522 {PIPE_FORMAT_A8R8G8B8_SRGB, (SWR_FORMAT)-1},
523 {PIPE_FORMAT_X8R8G8B8_SRGB, (SWR_FORMAT)-1},
524 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
525
526 {PIPE_FORMAT_DXT1_RGB, (SWR_FORMAT)-1},
527 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
528 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
529 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
530
531 {PIPE_FORMAT_DXT1_SRGB, (SWR_FORMAT)-1},
532 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
533 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
534 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
535
536 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
537 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
538 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
539 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
540
541 {PIPE_FORMAT_R8G8_B8G8_UNORM, (SWR_FORMAT)-1},
542 {PIPE_FORMAT_G8R8_G8B8_UNORM, (SWR_FORMAT)-1},
543
544 {PIPE_FORMAT_R8SG8SB8UX8U_NORM, (SWR_FORMAT)-1},
545 {PIPE_FORMAT_R5SG5SB6U_NORM, (SWR_FORMAT)-1},
546
547 {PIPE_FORMAT_A8B8G8R8_UNORM, (SWR_FORMAT)-1},
548 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
549 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
550 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
551 {PIPE_FORMAT_R9G9B9E5_FLOAT, (SWR_FORMAT)-1},
552 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
553 {PIPE_FORMAT_R1_UNORM, (SWR_FORMAT)-1},
554 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
555 {PIPE_FORMAT_R10G10B10X2_SNORM, (SWR_FORMAT)-1},
556 {PIPE_FORMAT_L4A4_UNORM, (SWR_FORMAT)-1},
557 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
558 {PIPE_FORMAT_R10SG10SB10SA2U_NORM, (SWR_FORMAT)-1},
559 {PIPE_FORMAT_R8G8Bx_SNORM, (SWR_FORMAT)-1},
560 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
561 {PIPE_FORMAT_B4G4R4X4_UNORM, (SWR_FORMAT)-1},
562
563 {PIPE_FORMAT_X24S8_UINT, (SWR_FORMAT)-1},
564 {PIPE_FORMAT_S8X24_UINT, (SWR_FORMAT)-1},
565 {PIPE_FORMAT_X32_S8X24_UINT, (SWR_FORMAT)-1},
566
567 {PIPE_FORMAT_B2G3R3_UNORM, (SWR_FORMAT)-1},
568 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
569 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
570 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
571
572 {PIPE_FORMAT_LATC1_UNORM, (SWR_FORMAT)-1},
573 {PIPE_FORMAT_LATC1_SNORM, (SWR_FORMAT)-1},
574 {PIPE_FORMAT_LATC2_UNORM, (SWR_FORMAT)-1},
575 {PIPE_FORMAT_LATC2_SNORM, (SWR_FORMAT)-1},
576
577 {PIPE_FORMAT_A8_SNORM, (SWR_FORMAT)-1},
578 {PIPE_FORMAT_L8_SNORM, (SWR_FORMAT)-1},
579 {PIPE_FORMAT_L8A8_SNORM, (SWR_FORMAT)-1},
580 {PIPE_FORMAT_I8_SNORM, (SWR_FORMAT)-1},
581 {PIPE_FORMAT_A16_SNORM, (SWR_FORMAT)-1},
582 {PIPE_FORMAT_L16_SNORM, (SWR_FORMAT)-1},
583 {PIPE_FORMAT_L16A16_SNORM, (SWR_FORMAT)-1},
584 {PIPE_FORMAT_I16_SNORM, (SWR_FORMAT)-1},
585
586 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
587 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
588 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
589 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
590 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
591 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
592 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
593 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
594
595 {PIPE_FORMAT_YV12, (SWR_FORMAT)-1},
596 {PIPE_FORMAT_YV16, (SWR_FORMAT)-1},
597 {PIPE_FORMAT_IYUV, (SWR_FORMAT)-1},
598 {PIPE_FORMAT_NV12, (SWR_FORMAT)-1},
599 {PIPE_FORMAT_NV21, (SWR_FORMAT)-1},
600
601 {PIPE_FORMAT_A4R4_UNORM, (SWR_FORMAT)-1},
602 {PIPE_FORMAT_R4A4_UNORM, (SWR_FORMAT)-1},
603 {PIPE_FORMAT_R8A8_UNORM, (SWR_FORMAT)-1},
604 {PIPE_FORMAT_A8R8_UNORM, (SWR_FORMAT)-1},
605
606 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
607 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
608
609 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
610 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
611 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
612
613 {PIPE_FORMAT_R8_UINT, R8_UINT},
614 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
615 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
616 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
617
618 {PIPE_FORMAT_R8_SINT, R8_SINT},
619 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
620 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
621 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
622
623 {PIPE_FORMAT_R16_UINT, R16_UINT},
624 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
625 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
626 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
627
628 {PIPE_FORMAT_R16_SINT, R16_SINT},
629 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
630 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
631 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
632
633 {PIPE_FORMAT_R32_UINT, R32_UINT},
634 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
635 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
636 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
637
638 {PIPE_FORMAT_R32_SINT, R32_SINT},
639 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
640 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
641 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
642
643 {PIPE_FORMAT_A8_UINT, (SWR_FORMAT)-1},
644 {PIPE_FORMAT_I8_UINT, I8_UINT},
645 {PIPE_FORMAT_L8_UINT, L8_UINT},
646 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
647
648 {PIPE_FORMAT_A8_SINT, (SWR_FORMAT)-1},
649 {PIPE_FORMAT_I8_SINT, I8_SINT},
650 {PIPE_FORMAT_L8_SINT, L8_SINT},
651 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
652
653 {PIPE_FORMAT_A16_UINT, (SWR_FORMAT)-1},
654 {PIPE_FORMAT_I16_UINT, (SWR_FORMAT)-1},
655 {PIPE_FORMAT_L16_UINT, (SWR_FORMAT)-1},
656 {PIPE_FORMAT_L16A16_UINT, (SWR_FORMAT)-1},
657
658 {PIPE_FORMAT_A16_SINT, (SWR_FORMAT)-1},
659 {PIPE_FORMAT_I16_SINT, (SWR_FORMAT)-1},
660 {PIPE_FORMAT_L16_SINT, (SWR_FORMAT)-1},
661 {PIPE_FORMAT_L16A16_SINT, (SWR_FORMAT)-1},
662
663 {PIPE_FORMAT_A32_UINT, (SWR_FORMAT)-1},
664 {PIPE_FORMAT_I32_UINT, (SWR_FORMAT)-1},
665 {PIPE_FORMAT_L32_UINT, (SWR_FORMAT)-1},
666 {PIPE_FORMAT_L32A32_UINT, (SWR_FORMAT)-1},
667
668 {PIPE_FORMAT_A32_SINT, (SWR_FORMAT)-1},
669 {PIPE_FORMAT_I32_SINT, (SWR_FORMAT)-1},
670 {PIPE_FORMAT_L32_SINT, (SWR_FORMAT)-1},
671 {PIPE_FORMAT_L32A32_SINT, (SWR_FORMAT)-1},
672
673 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
674
675 {PIPE_FORMAT_ETC1_RGB8, (SWR_FORMAT)-1},
676
677 {PIPE_FORMAT_R8G8_R8B8_UNORM, (SWR_FORMAT)-1},
678 {PIPE_FORMAT_G8R8_B8R8_UNORM, (SWR_FORMAT)-1},
679
680 {PIPE_FORMAT_R8G8B8X8_SNORM, (SWR_FORMAT)-1},
681 {PIPE_FORMAT_R8G8B8X8_SRGB, (SWR_FORMAT)-1},
682 {PIPE_FORMAT_R8G8B8X8_UINT, (SWR_FORMAT)-1},
683 {PIPE_FORMAT_R8G8B8X8_SINT, (SWR_FORMAT)-1},
684 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
685 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
686 {PIPE_FORMAT_R16G16B16X16_SNORM, (SWR_FORMAT)-1},
687 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
688 {PIPE_FORMAT_R16G16B16X16_UINT, (SWR_FORMAT)-1},
689 {PIPE_FORMAT_R16G16B16X16_SINT, (SWR_FORMAT)-1},
690 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
691 {PIPE_FORMAT_R32G32B32X32_UINT, (SWR_FORMAT)-1},
692 {PIPE_FORMAT_R32G32B32X32_SINT, (SWR_FORMAT)-1},
693
694 {PIPE_FORMAT_R8A8_SNORM, (SWR_FORMAT)-1},
695 {PIPE_FORMAT_R16A16_UNORM, (SWR_FORMAT)-1},
696 {PIPE_FORMAT_R16A16_SNORM, (SWR_FORMAT)-1},
697 {PIPE_FORMAT_R16A16_FLOAT, (SWR_FORMAT)-1},
698 {PIPE_FORMAT_R32A32_FLOAT, (SWR_FORMAT)-1},
699 {PIPE_FORMAT_R8A8_UINT, (SWR_FORMAT)-1},
700 {PIPE_FORMAT_R8A8_SINT, (SWR_FORMAT)-1},
701 {PIPE_FORMAT_R16A16_UINT, (SWR_FORMAT)-1},
702 {PIPE_FORMAT_R16A16_SINT, (SWR_FORMAT)-1},
703 {PIPE_FORMAT_R32A32_UINT, (SWR_FORMAT)-1},
704 {PIPE_FORMAT_R32A32_SINT, (SWR_FORMAT)-1},
705 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
706
707 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB}
708 };
709
710 try {
711 return mesa2swr.at(format);
712 }
713 catch (std::out_of_range) {
714 debug_printf("asked to convert unsupported format %s\n",
715 util_format_name(format));
716
717 return (SWR_FORMAT)-1;
718 }
719 }
720
721 static boolean
722 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
723 {
724 struct sw_winsys *winsys = screen->winsys;
725 struct sw_displaytarget *dt;
726
727 const unsigned width = align(res->swr.width, res->swr.halign);
728 const unsigned height = align(res->swr.height, res->swr.valign);
729
730 UINT stride;
731 dt = winsys->displaytarget_create(winsys,
732 res->base.bind,
733 res->base.format,
734 width, height,
735 64, NULL,
736 &stride);
737
738 if (dt == NULL)
739 return FALSE;
740
741 void *map = winsys->displaytarget_map(winsys, dt, 0);
742
743 res->display_target = dt;
744 res->swr.pBaseAddress = (uint8_t*) map;
745
746 /* Clear the display target surface */
747 if (map)
748 memset(map, 0, height * stride);
749
750 winsys->displaytarget_unmap(winsys, dt);
751
752 return TRUE;
753 }
754
755 static bool
756 swr_texture_layout(struct swr_screen *screen,
757 struct swr_resource *res,
758 boolean allocate)
759 {
760 struct pipe_resource *pt = &res->base;
761
762 pipe_format fmt = pt->format;
763 const struct util_format_description *desc = util_format_description(fmt);
764
765 res->has_depth = util_format_has_depth(desc);
766 res->has_stencil = util_format_has_stencil(desc);
767
768 if (res->has_stencil && !res->has_depth)
769 fmt = PIPE_FORMAT_R8_UINT;
770
771 /* We always use the SWR layout. For 2D and 3D textures this looks like:
772 *
773 * |<------- pitch ------->|
774 * +=======================+-------
775 * |Array 0 | ^
776 * | | |
777 * | Level 0 | |
778 * | | |
779 * | | qpitch
780 * +-----------+-----------+ |
781 * | | L2L2L2L2 | |
782 * | Level 1 | L3L3 | |
783 * | | L4 | v
784 * +===========+===========+-------
785 * |Array 1 |
786 * | |
787 * | Level 0 |
788 * | |
789 * | |
790 * +-----------+-----------+
791 * | | L2L2L2L2 |
792 * | Level 1 | L3L3 |
793 * | | L4 |
794 * +===========+===========+
795 *
796 * The overall width in bytes is known as the pitch, while the overall
797 * height in rows is the qpitch. Array slices are laid out logically below
798 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
799 * just invalid for the higher array numbers (since depth is also
800 * minified). 1D and 1D array surfaces are stored effectively the same way,
801 * except that pitch never plays into it. All the levels are logically
802 * adjacent to each other on the X axis. The qpitch becomes the number of
803 * elements between array slices, while the pitch is unused.
804 *
805 * Each level's sizes are subject to the valign and halign settings of the
806 * surface. For compressed formats that swr is unaware of, we will use an
807 * appropriately-sized uncompressed format, and scale the widths/heights.
808 *
809 * This surface is stored inside res->swr. For depth/stencil textures,
810 * res->secondary will have an identically-laid-out but R8_UINT-formatted
811 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
812 * texels, to simplify map/unmap logic which copies the stencil values
813 * in/out.
814 */
815
816 res->swr.width = pt->width0;
817 res->swr.height = pt->height0;
818 res->swr.type = swr_convert_target_type(pt->target);
819 res->swr.tileMode = SWR_TILE_NONE;
820 res->swr.format = mesa_to_swr_format(fmt);
821 res->swr.numSamples = std::max(1u, pt->nr_samples);
822
823 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
824 res->swr.halign = KNOB_MACROTILE_X_DIM;
825 res->swr.valign = KNOB_MACROTILE_Y_DIM;
826 } else {
827 res->swr.halign = 1;
828 res->swr.valign = 1;
829 }
830
831 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
832 unsigned width = align(pt->width0, halign);
833 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
834 for (int level = 1; level <= pt->last_level; level++)
835 width += align(u_minify(pt->width0, level), halign);
836 res->swr.pitch = util_format_get_blocksize(fmt);
837 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
838 } else {
839 // The pitch is the overall width of the texture in bytes. Most of the
840 // time this is the pitch of level 0 since all the other levels fit
841 // underneath it. However in some degenerate situations, the width of
842 // level1 + level2 may be larger. In that case, we use those
843 // widths. This can happen if, e.g. halign is 32, and the width of level
844 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
845 // be 32 each, adding up to 64.
846 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
847 if (pt->last_level > 1) {
848 width = std::max<uint32_t>(
849 width,
850 align(u_minify(pt->width0, 1), halign) +
851 align(u_minify(pt->width0, 2), halign));
852 }
853 res->swr.pitch = util_format_get_stride(fmt, width);
854
855 // The qpitch is controlled by either the height of the second LOD, or
856 // the combination of all the later LODs.
857 unsigned height = align(pt->height0, valign);
858 if (pt->last_level == 1) {
859 height += align(u_minify(pt->height0, 1), valign);
860 } else if (pt->last_level > 1) {
861 unsigned level1 = align(u_minify(pt->height0, 1), valign);
862 unsigned level2 = 0;
863 for (int level = 2; level <= pt->last_level; level++) {
864 level2 += align(u_minify(pt->height0, level), valign);
865 }
866 height += std::max(level1, level2);
867 }
868 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
869 }
870
871 if (pt->target == PIPE_TEXTURE_3D)
872 res->swr.depth = pt->depth0;
873 else
874 res->swr.depth = pt->array_size;
875
876 // Fix up swr format if necessary so that LOD offset computation works
877 if (res->swr.format == (SWR_FORMAT)-1) {
878 switch (util_format_get_blocksize(fmt)) {
879 default:
880 unreachable("Unexpected format block size");
881 case 1: res->swr.format = R8_UINT; break;
882 case 2: res->swr.format = R16_UINT; break;
883 case 4: res->swr.format = R32_UINT; break;
884 case 8:
885 if (util_format_is_compressed(fmt))
886 res->swr.format = BC4_UNORM;
887 else
888 res->swr.format = R32G32_UINT;
889 break;
890 case 16:
891 if (util_format_is_compressed(fmt))
892 res->swr.format = BC5_UNORM;
893 else
894 res->swr.format = R32G32B32A32_UINT;
895 break;
896 }
897 }
898
899 for (int level = 0; level <= pt->last_level; level++) {
900 res->mip_offsets[level] =
901 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
902 }
903
904 size_t total_size =
905 (size_t)res->swr.depth * res->swr.qpitch * res->swr.pitch;
906 if (total_size > SWR_MAX_TEXTURE_SIZE)
907 return false;
908
909 if (allocate) {
910 res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
911
912 if (res->has_depth && res->has_stencil) {
913 res->secondary = res->swr;
914 res->secondary.format = R8_UINT;
915 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
916
917 for (int level = 0; level <= pt->last_level; level++) {
918 res->secondary_mip_offsets[level] =
919 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
920 }
921
922 res->secondary.pBaseAddress = (uint8_t *)AlignedMalloc(
923 res->secondary.depth * res->secondary.qpitch *
924 res->secondary.pitch, 64);
925 }
926 }
927
928 return true;
929 }
930
931 static boolean
932 swr_can_create_resource(struct pipe_screen *screen,
933 const struct pipe_resource *templat)
934 {
935 struct swr_resource res;
936 memset(&res, 0, sizeof(res));
937 res.base = *templat;
938 return swr_texture_layout(swr_screen(screen), &res, false);
939 }
940
941 static struct pipe_resource *
942 swr_resource_create(struct pipe_screen *_screen,
943 const struct pipe_resource *templat)
944 {
945 struct swr_screen *screen = swr_screen(_screen);
946 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
947 if (!res)
948 return NULL;
949
950 res->base = *templat;
951 pipe_reference_init(&res->base.reference, 1);
952 res->base.screen = &screen->base;
953
954 if (swr_resource_is_texture(&res->base)) {
955 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
956 | PIPE_BIND_SHARED)) {
957 /* displayable surface
958 * first call swr_texture_layout without allocating to finish
959 * filling out the SWR_SURFAE_STATE in res */
960 swr_texture_layout(screen, res, false);
961 if (!swr_displaytarget_layout(screen, res))
962 goto fail;
963 } else {
964 /* texture map */
965 if (!swr_texture_layout(screen, res, true))
966 goto fail;
967 }
968 } else {
969 /* other data (vertex buffer, const buffer, etc) */
970 assert(util_format_get_blocksize(templat->format) == 1);
971 assert(templat->height0 == 1);
972 assert(templat->depth0 == 1);
973 assert(templat->last_level == 0);
974
975 /* Easiest to just call swr_texture_layout, as it sets up
976 * SWR_SURFAE_STATE in res */
977 if (!swr_texture_layout(screen, res, true))
978 goto fail;
979 }
980
981 return &res->base;
982
983 fail:
984 FREE(res);
985 return NULL;
986 }
987
988 static void
989 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
990 {
991 struct swr_screen *screen = swr_screen(p_screen);
992 struct swr_resource *spr = swr_resource(pt);
993 struct pipe_context *pipe = screen->pipe;
994
995 /* Only wait on fence if the resource is being used */
996 if (pipe && spr->status) {
997 /* But, if there's no fence pending, submit one.
998 * XXX: Remove once draw timestamps are implmented. */
999 if (!swr_is_fence_pending(screen->flush_fence))
1000 swr_fence_submit(swr_context(pipe), screen->flush_fence);
1001
1002 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1003 swr_resource_unused(pt);
1004 }
1005
1006 /*
1007 * Free resource primary surface. If resource is display target, winsys
1008 * manages the buffer and will free it on displaytarget_destroy.
1009 */
1010 if (spr->display_target) {
1011 /* display target */
1012 struct sw_winsys *winsys = screen->winsys;
1013 winsys->displaytarget_destroy(winsys, spr->display_target);
1014 } else
1015 AlignedFree(spr->swr.pBaseAddress);
1016
1017 AlignedFree(spr->secondary.pBaseAddress);
1018
1019 FREE(spr);
1020 }
1021
1022
1023 static void
1024 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1025 struct pipe_resource *resource,
1026 unsigned level,
1027 unsigned layer,
1028 void *context_private,
1029 struct pipe_box *sub_box)
1030 {
1031 struct swr_screen *screen = swr_screen(p_screen);
1032 struct sw_winsys *winsys = screen->winsys;
1033 struct swr_resource *spr = swr_resource(resource);
1034 struct pipe_context *pipe = screen->pipe;
1035
1036 if (pipe) {
1037 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1038 swr_resource_unused(resource);
1039 SwrEndFrame(swr_context(pipe)->swrContext);
1040 }
1041
1042 debug_assert(spr->display_target);
1043 if (spr->display_target)
1044 winsys->displaytarget_display(
1045 winsys, spr->display_target, context_private, sub_box);
1046 }
1047
1048
1049 static void
1050 swr_destroy_screen(struct pipe_screen *p_screen)
1051 {
1052 struct swr_screen *screen = swr_screen(p_screen);
1053 struct sw_winsys *winsys = screen->winsys;
1054
1055 fprintf(stderr, "SWR destroy screen!\n");
1056
1057 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1058 swr_fence_reference(p_screen, &screen->flush_fence, NULL);
1059
1060 JitDestroyContext(screen->hJitMgr);
1061
1062 if (winsys->destroy)
1063 winsys->destroy(winsys);
1064
1065 FREE(screen);
1066 }
1067
1068 PUBLIC
1069 struct pipe_screen *
1070 swr_create_screen_internal(struct sw_winsys *winsys)
1071 {
1072 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1073
1074 if (!screen)
1075 return NULL;
1076
1077 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
1078 g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152);
1079 }
1080
1081 screen->winsys = winsys;
1082 screen->base.get_name = swr_get_name;
1083 screen->base.get_vendor = swr_get_vendor;
1084 screen->base.is_format_supported = swr_is_format_supported;
1085 screen->base.context_create = swr_create_context;
1086 screen->base.can_create_resource = swr_can_create_resource;
1087
1088 screen->base.destroy = swr_destroy_screen;
1089 screen->base.get_param = swr_get_param;
1090 screen->base.get_shader_param = swr_get_shader_param;
1091 screen->base.get_paramf = swr_get_paramf;
1092
1093 screen->base.resource_create = swr_resource_create;
1094 screen->base.resource_destroy = swr_resource_destroy;
1095
1096 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1097
1098 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
1099
1100 swr_fence_init(&screen->base);
1101
1102 util_format_s3tc_init();
1103
1104 return &screen->base;
1105 }
1106