src/gallium/drivers/swr/swr_screen.cpp

   1 /****************************************************************************
   2  * Copyright (C) 2015 Intel Corporation.   All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  ***************************************************************************/
  23
  24 #include "swr_context.h"
  25 #include "swr_public.h"
  26 #include "swr_screen.h"
  27 #include "swr_resource.h"
  28 #include "swr_fence.h"
  29 #include "gen_knobs.h"
  30
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_defines.h"
  33 #include "util/u_memory.h"
  34 #include "util/u_format.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_cpu_detect.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39
  40 #include "state_tracker/sw_winsys.h"
  41
  42 #include "jit_api.h"
  43
  44 #include "memory/TilingFunctions.h"
  45
  46 #include <stdio.h>
  47 #include <map>
  48
  49 /* MSVC case instensitive compare */
  50 #if defined(PIPE_CC_MSVC)
  51    #define strcasecmp lstrcmpiA
  52 #endif
  53
  54 /*
  55  * Max texture sizes
  56  * XXX Check max texture size values against core and sampler.
  57  */
  58 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
  59 #define SWR_MAX_TEXTURE_2D_LEVELS 14  /* 8K x 8K for now */
  60 #define SWR_MAX_TEXTURE_3D_LEVELS 12  /* 2K x 2K x 2K for now */
  61 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14  /* 8K x 8K for now */
  62 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
  63
  64 /* Default max client_copy_limit */
  65 #define SWR_CLIENT_COPY_LIMIT 32768
  66
  67 /* Flag indicates creation of alternate surface, to prevent recursive loop
  68  * in resource creation when msaa_force_enable is set. */
  69 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
  70
  71
  72 static const char *
  73 swr_get_name(struct pipe_screen *screen)
  74 {
  75    static char buf[100];
  76    util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
  77                  HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
  78                  lp_native_vector_width );
  79    return buf;
  80 }
  81
  82 static const char *
  83 swr_get_vendor(struct pipe_screen *screen)
  84 {
  85    return "Intel Corporation";
  86 }
  87
  88 static boolean
  89 swr_is_format_supported(struct pipe_screen *_screen,
  90                         enum pipe_format format,
  91                         enum pipe_texture_target target,
  92                         unsigned sample_count,
  93                         unsigned bind)
  94 {
  95    struct swr_screen *screen = swr_screen(_screen);
  96    struct sw_winsys *winsys = screen->winsys;
  97    const struct util_format_description *format_desc;
  98
  99    assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
 100           || target == PIPE_TEXTURE_1D_ARRAY
 101           || target == PIPE_TEXTURE_2D
 102           || target == PIPE_TEXTURE_2D_ARRAY
 103           || target == PIPE_TEXTURE_RECT
 104           || target == PIPE_TEXTURE_3D
 105           || target == PIPE_TEXTURE_CUBE
 106           || target == PIPE_TEXTURE_CUBE_ARRAY);
 107
 108    format_desc = util_format_description(format);
 109    if (!format_desc)
 110       return FALSE;
 111
 112    if ((sample_count > screen->msaa_max_count)
 113       || !util_is_power_of_two(sample_count))
 114       return FALSE;
 115
 116    if (bind & PIPE_BIND_DISPLAY_TARGET) {
 117       if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
 118          return FALSE;
 119    }
 120
 121    if (bind & PIPE_BIND_RENDER_TARGET) {
 122       if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
 123          return FALSE;
 124
 125       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 126          return FALSE;
 127
 128       /*
 129        * Although possible, it is unnatural to render into compressed or YUV
 130        * surfaces. So disable these here to avoid going into weird paths
 131        * inside the state trackers.
 132        */
 133       if (format_desc->block.width != 1 || format_desc->block.height != 1)
 134          return FALSE;
 135    }
 136
 137    if (bind & PIPE_BIND_DEPTH_STENCIL) {
 138       if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
 139          return FALSE;
 140
 141       if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
 142          return FALSE;
 143    }
 144
 145    if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
 146        format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
 147       return FALSE;
 148    }
 149
 150    if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
 151        format != PIPE_FORMAT_ETC1_RGB8) {
 152       return FALSE;
 153    }
 154
 155    if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
 156       return util_format_s3tc_enabled;
 157    }
 158
 159    return TRUE;
 160 }
 161
 162 static int
 163 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
 164 {
 165    switch (param) {
 166       /* limits */
 167    case PIPE_CAP_MAX_RENDER_TARGETS:
 168       return PIPE_MAX_COLOR_BUFS;
 169    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 170       return SWR_MAX_TEXTURE_2D_LEVELS;
 171    case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 172       return SWR_MAX_TEXTURE_3D_LEVELS;
 173    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 174       return SWR_MAX_TEXTURE_CUBE_LEVELS;
 175    case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 176       return MAX_SO_STREAMS;
 177    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 178    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 179       return MAX_ATTRIBUTES * 4;
 180    case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 181    case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 182       return 1024;
 183    case PIPE_CAP_MAX_VERTEX_STREAMS:
 184       return 1;
 185    case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 186       return 2048;
 187    case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 188       return SWR_MAX_TEXTURE_ARRAY_LAYERS;
 189    case PIPE_CAP_MIN_TEXEL_OFFSET:
 190       return -8;
 191    case PIPE_CAP_MAX_TEXEL_OFFSET:
 192       return 7;
 193    case PIPE_CAP_GLSL_FEATURE_LEVEL:
 194       return 330;
 195    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 196       return 16;
 197    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 198       return 64;
 199    case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 200       return 65536;
 201    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 202       return 0;
 203    case PIPE_CAP_MAX_VIEWPORTS:
 204       return 1;
 205    case PIPE_CAP_ENDIANNESS:
 206       return PIPE_ENDIAN_NATIVE;
 207    case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 208    case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 209       return 0;
 210
 211       /* supported features */
 212    case PIPE_CAP_NPOT_TEXTURES:
 213    case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 214    case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 215    case PIPE_CAP_TWO_SIDED_STENCIL:
 216    case PIPE_CAP_SM3:
 217    case PIPE_CAP_POINT_SPRITE:
 218    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 219    case PIPE_CAP_OCCLUSION_QUERY:
 220    case PIPE_CAP_QUERY_TIME_ELAPSED:
 221    case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 222    case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 223    case PIPE_CAP_TEXTURE_SHADOW_MAP:
 224    case PIPE_CAP_TEXTURE_SWIZZLE:
 225    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 226    case PIPE_CAP_INDEP_BLEND_ENABLE:
 227    case PIPE_CAP_INDEP_BLEND_FUNC:
 228    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 229    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 230    case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 231    case PIPE_CAP_DEPTH_CLIP_DISABLE:
 232    case PIPE_CAP_PRIMITIVE_RESTART:
 233    case PIPE_CAP_TGSI_INSTANCEID:
 234    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 235    case PIPE_CAP_START_INSTANCE:
 236    case PIPE_CAP_SEAMLESS_CUBE_MAP:
 237    case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 238    case PIPE_CAP_CONDITIONAL_RENDER:
 239    case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 240    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 241    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 242    case PIPE_CAP_USER_VERTEX_BUFFERS:
 243    case PIPE_CAP_USER_CONSTANT_BUFFERS:
 244    case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 245    case PIPE_CAP_QUERY_TIMESTAMP:
 246    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 247    case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 248    case PIPE_CAP_DRAW_INDIRECT:
 249    case PIPE_CAP_UMA:
 250    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 251    case PIPE_CAP_CLIP_HALFZ:
 252    case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 253    case PIPE_CAP_DEPTH_BOUNDS_TEST:
 254    case PIPE_CAP_CLEAR_TEXTURE:
 255    case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 256    case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 257    case PIPE_CAP_CULL_DISTANCE:
 258    case PIPE_CAP_CUBE_MAP_ARRAY:
 259    case PIPE_CAP_DOUBLES:
 260       return 1;
 261
 262    /* MSAA support
 263     * If user has explicitly set max_sample_count = 0 (via SWR_MSAA_MAX_COUNT)
 264     * then disable all MSAA support and go back to old caps. */
 265    case PIPE_CAP_TEXTURE_MULTISAMPLE:
 266    case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 267       return swr_screen(screen)->msaa_max_count ? 1 : 0;
 268    case PIPE_CAP_FAKE_SW_MSAA:
 269       return swr_screen(screen)->msaa_max_count ? 0 : 1;
 270
 271       /* unsupported features */
 272    case PIPE_CAP_ANISOTROPIC_FILTER:
 273    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 274    case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 275    case PIPE_CAP_SHADER_STENCIL_EXPORT:
 276    case PIPE_CAP_TEXTURE_BARRIER:
 277    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 278    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 279    case PIPE_CAP_COMPUTE:
 280    case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 281    case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 282    case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 283    case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 284    case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 285    case PIPE_CAP_TGSI_TEXCOORD:
 286    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 287    case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 288    case PIPE_CAP_TEXTURE_GATHER_SM5:
 289    case PIPE_CAP_TEXTURE_QUERY_LOD:
 290    case PIPE_CAP_SAMPLE_SHADING:
 291    case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 292    case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 293    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 294    case PIPE_CAP_SAMPLER_VIEW_TARGET:
 295    case PIPE_CAP_VERTEXID_NOBASE:
 296    case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 297    case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 298    case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 299    case PIPE_CAP_TGSI_TXQS:
 300    case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 301    case PIPE_CAP_SHAREABLE_SHADERS:
 302    case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 303    case PIPE_CAP_DRAW_PARAMETERS:
 304    case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 305    case PIPE_CAP_MULTI_DRAW_INDIRECT:
 306    case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 307    case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 308    case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 309    case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 310    case PIPE_CAP_INVALIDATE_BUFFER:
 311    case PIPE_CAP_GENERATE_MIPMAP:
 312    case PIPE_CAP_STRING_MARKER:
 313    case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 314    case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 315    case PIPE_CAP_QUERY_BUFFER_OBJECT:
 316    case PIPE_CAP_QUERY_MEMORY_INFO:
 317    case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 318    case PIPE_CAP_PCI_GROUP:
 319    case PIPE_CAP_PCI_BUS:
 320    case PIPE_CAP_PCI_DEVICE:
 321    case PIPE_CAP_PCI_FUNCTION:
 322    case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 323    case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 324    case PIPE_CAP_TGSI_VOTE:
 325    case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 326    case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 327    case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 328    case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 329    case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 330    case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 331    case PIPE_CAP_NATIVE_FENCE_FD:
 332    case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 333    case PIPE_CAP_TGSI_FS_FBFETCH:
 334    case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 335    case PIPE_CAP_INT64:
 336    case PIPE_CAP_INT64_DIVMOD:
 337    case PIPE_CAP_TGSI_TEX_TXF_LZ:
 338    case PIPE_CAP_TGSI_CLOCK:
 339    case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 340    case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 341    case PIPE_CAP_TGSI_BALLOT:
 342    case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 343    case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 344    case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 345    case PIPE_CAP_POST_DEPTH_COVERAGE:
 346    case PIPE_CAP_BINDLESS_TEXTURE:
 347       return 0;
 348
 349    case PIPE_CAP_VENDOR_ID:
 350       return 0xFFFFFFFF;
 351    case PIPE_CAP_DEVICE_ID:
 352       return 0xFFFFFFFF;
 353    case PIPE_CAP_ACCELERATED:
 354       return 0;
 355    case PIPE_CAP_VIDEO_MEMORY: {
 356       /* XXX: Do we want to return the full amount of system memory ? */
 357       uint64_t system_memory;
 358
 359       if (!os_get_total_physical_memory(&system_memory))
 360          return 0;
 361
 362       return (int)(system_memory >> 20);
 363    }
 364    }
 365
 366    /* should only get here on unhandled cases */
 367    debug_printf("Unexpected PIPE_CAP %d query\n", param);
 368    return 0;
 369 }
 370
 371 static int
 372 swr_get_shader_param(struct pipe_screen *screen,
 373                      enum pipe_shader_type shader,
 374                      enum pipe_shader_cap param)
 375 {
 376    if (shader == PIPE_SHADER_VERTEX ||
 377        shader == PIPE_SHADER_FRAGMENT ||
 378        shader == PIPE_SHADER_GEOMETRY)
 379       return gallivm_get_shader_param(param);
 380
 381    // Todo: tesselation, compute
 382    return 0;
 383 }
 384
 385
 386 static float
 387 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
 388 {
 389    switch (param) {
 390    case PIPE_CAPF_MAX_LINE_WIDTH:
 391    case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 392    case PIPE_CAPF_MAX_POINT_WIDTH:
 393       return 255.0; /* arbitrary */
 394    case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 395       return 0.0;
 396    case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 397       return 0.0;
 398    case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 399       return 16.0; /* arbitrary */
 400    case PIPE_CAPF_GUARD_BAND_LEFT:
 401    case PIPE_CAPF_GUARD_BAND_TOP:
 402    case PIPE_CAPF_GUARD_BAND_RIGHT:
 403    case PIPE_CAPF_GUARD_BAND_BOTTOM:
 404       return 0.0;
 405    }
 406    /* should only get here on unhandled cases */
 407    debug_printf("Unexpected PIPE_CAPF %d query\n", param);
 408    return 0.0;
 409 }
 410
 411 SWR_FORMAT
 412 mesa_to_swr_format(enum pipe_format format)
 413 {
 414    static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
 415       /* depth / stencil */
 416       {PIPE_FORMAT_Z16_UNORM,              R16_UNORM}, // z
 417       {PIPE_FORMAT_Z32_FLOAT,              R32_FLOAT}, // z
 418       {PIPE_FORMAT_Z24_UNORM_S8_UINT,      R24_UNORM_X8_TYPELESS}, // z
 419       {PIPE_FORMAT_Z24X8_UNORM,            R24_UNORM_X8_TYPELESS}, // z
 420       {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT,   R32_FLOAT_X8X24_TYPELESS}, // z
 421
 422       /* alpha */
 423       {PIPE_FORMAT_A8_UNORM,               A8_UNORM},
 424       {PIPE_FORMAT_A16_UNORM,              A16_UNORM},
 425       {PIPE_FORMAT_A16_FLOAT,              A16_FLOAT},
 426       {PIPE_FORMAT_A32_FLOAT,              A32_FLOAT},
 427
 428       /* odd sizes, bgr */
 429       {PIPE_FORMAT_B5G6R5_UNORM,           B5G6R5_UNORM},
 430       {PIPE_FORMAT_B5G6R5_SRGB,            B5G6R5_UNORM_SRGB},
 431       {PIPE_FORMAT_B5G5R5A1_UNORM,         B5G5R5A1_UNORM},
 432       {PIPE_FORMAT_B5G5R5X1_UNORM,         B5G5R5X1_UNORM},
 433       {PIPE_FORMAT_B4G4R4A4_UNORM,         B4G4R4A4_UNORM},
 434       {PIPE_FORMAT_B8G8R8A8_UNORM,         B8G8R8A8_UNORM},
 435       {PIPE_FORMAT_B8G8R8A8_SRGB,          B8G8R8A8_UNORM_SRGB},
 436       {PIPE_FORMAT_B8G8R8X8_UNORM,         B8G8R8X8_UNORM},
 437       {PIPE_FORMAT_B8G8R8X8_SRGB,          B8G8R8X8_UNORM_SRGB},
 438
 439       /* rgb10a2 */
 440       {PIPE_FORMAT_R10G10B10A2_UNORM,      R10G10B10A2_UNORM},
 441       {PIPE_FORMAT_R10G10B10A2_SNORM,      R10G10B10A2_SNORM},
 442       {PIPE_FORMAT_R10G10B10A2_USCALED,    R10G10B10A2_USCALED},
 443       {PIPE_FORMAT_R10G10B10A2_SSCALED,    R10G10B10A2_SSCALED},
 444       {PIPE_FORMAT_R10G10B10A2_UINT,       R10G10B10A2_UINT},
 445
 446       /* rgb10x2 */
 447       {PIPE_FORMAT_R10G10B10X2_USCALED,    R10G10B10X2_USCALED},
 448
 449       /* bgr10a2 */
 450       {PIPE_FORMAT_B10G10R10A2_UNORM,      B10G10R10A2_UNORM},
 451       {PIPE_FORMAT_B10G10R10A2_SNORM,      B10G10R10A2_SNORM},
 452       {PIPE_FORMAT_B10G10R10A2_USCALED,    B10G10R10A2_USCALED},
 453       {PIPE_FORMAT_B10G10R10A2_SSCALED,    B10G10R10A2_SSCALED},
 454       {PIPE_FORMAT_B10G10R10A2_UINT,       B10G10R10A2_UINT},
 455
 456       /* bgr10x2 */
 457       {PIPE_FORMAT_B10G10R10X2_UNORM,      B10G10R10X2_UNORM},
 458
 459       /* r11g11b10 */
 460       {PIPE_FORMAT_R11G11B10_FLOAT,        R11G11B10_FLOAT},
 461
 462       /* 32 bits per component */
 463       {PIPE_FORMAT_R32_FLOAT,              R32_FLOAT},
 464       {PIPE_FORMAT_R32G32_FLOAT,           R32G32_FLOAT},
 465       {PIPE_FORMAT_R32G32B32_FLOAT,        R32G32B32_FLOAT},
 466       {PIPE_FORMAT_R32G32B32A32_FLOAT,     R32G32B32A32_FLOAT},
 467       {PIPE_FORMAT_R32G32B32X32_FLOAT,     R32G32B32X32_FLOAT},
 468
 469       {PIPE_FORMAT_R32_USCALED,            R32_USCALED},
 470       {PIPE_FORMAT_R32G32_USCALED,         R32G32_USCALED},
 471       {PIPE_FORMAT_R32G32B32_USCALED,      R32G32B32_USCALED},
 472       {PIPE_FORMAT_R32G32B32A32_USCALED,   R32G32B32A32_USCALED},
 473
 474       {PIPE_FORMAT_R32_SSCALED,            R32_SSCALED},
 475       {PIPE_FORMAT_R32G32_SSCALED,         R32G32_SSCALED},
 476       {PIPE_FORMAT_R32G32B32_SSCALED,      R32G32B32_SSCALED},
 477       {PIPE_FORMAT_R32G32B32A32_SSCALED,   R32G32B32A32_SSCALED},
 478
 479       {PIPE_FORMAT_R32_UINT,               R32_UINT},
 480       {PIPE_FORMAT_R32G32_UINT,            R32G32_UINT},
 481       {PIPE_FORMAT_R32G32B32_UINT,         R32G32B32_UINT},
 482       {PIPE_FORMAT_R32G32B32A32_UINT,      R32G32B32A32_UINT},
 483
 484       {PIPE_FORMAT_R32_SINT,               R32_SINT},
 485       {PIPE_FORMAT_R32G32_SINT,            R32G32_SINT},
 486       {PIPE_FORMAT_R32G32B32_SINT,         R32G32B32_SINT},
 487       {PIPE_FORMAT_R32G32B32A32_SINT,      R32G32B32A32_SINT},
 488
 489       /* 16 bits per component */
 490       {PIPE_FORMAT_R16_UNORM,              R16_UNORM},
 491       {PIPE_FORMAT_R16G16_UNORM,           R16G16_UNORM},
 492       {PIPE_FORMAT_R16G16B16_UNORM,        R16G16B16_UNORM},
 493       {PIPE_FORMAT_R16G16B16A16_UNORM,     R16G16B16A16_UNORM},
 494       {PIPE_FORMAT_R16G16B16X16_UNORM,     R16G16B16X16_UNORM},
 495
 496       {PIPE_FORMAT_R16_USCALED,            R16_USCALED},
 497       {PIPE_FORMAT_R16G16_USCALED,         R16G16_USCALED},
 498       {PIPE_FORMAT_R16G16B16_USCALED,      R16G16B16_USCALED},
 499       {PIPE_FORMAT_R16G16B16A16_USCALED,   R16G16B16A16_USCALED},
 500
 501       {PIPE_FORMAT_R16_SNORM,              R16_SNORM},
 502       {PIPE_FORMAT_R16G16_SNORM,           R16G16_SNORM},
 503       {PIPE_FORMAT_R16G16B16_SNORM,        R16G16B16_SNORM},
 504       {PIPE_FORMAT_R16G16B16A16_SNORM,     R16G16B16A16_SNORM},
 505
 506       {PIPE_FORMAT_R16_SSCALED,            R16_SSCALED},
 507       {PIPE_FORMAT_R16G16_SSCALED,         R16G16_SSCALED},
 508       {PIPE_FORMAT_R16G16B16_SSCALED,      R16G16B16_SSCALED},
 509       {PIPE_FORMAT_R16G16B16A16_SSCALED,   R16G16B16A16_SSCALED},
 510
 511       {PIPE_FORMAT_R16_UINT,               R16_UINT},
 512       {PIPE_FORMAT_R16G16_UINT,            R16G16_UINT},
 513       {PIPE_FORMAT_R16G16B16_UINT,         R16G16B16_UINT},
 514       {PIPE_FORMAT_R16G16B16A16_UINT,      R16G16B16A16_UINT},
 515
 516       {PIPE_FORMAT_R16_SINT,               R16_SINT},
 517       {PIPE_FORMAT_R16G16_SINT,            R16G16_SINT},
 518       {PIPE_FORMAT_R16G16B16_SINT,         R16G16B16_SINT},
 519       {PIPE_FORMAT_R16G16B16A16_SINT,      R16G16B16A16_SINT},
 520
 521       {PIPE_FORMAT_R16_FLOAT,              R16_FLOAT},
 522       {PIPE_FORMAT_R16G16_FLOAT,           R16G16_FLOAT},
 523       {PIPE_FORMAT_R16G16B16_FLOAT,        R16G16B16_FLOAT},
 524       {PIPE_FORMAT_R16G16B16A16_FLOAT,     R16G16B16A16_FLOAT},
 525       {PIPE_FORMAT_R16G16B16X16_FLOAT,     R16G16B16X16_FLOAT},
 526
 527       /* 8 bits per component */
 528       {PIPE_FORMAT_R8_UNORM,               R8_UNORM},
 529       {PIPE_FORMAT_R8G8_UNORM,             R8G8_UNORM},
 530       {PIPE_FORMAT_R8G8B8_UNORM,           R8G8B8_UNORM},
 531       {PIPE_FORMAT_R8G8B8_SRGB,            R8G8B8_UNORM_SRGB},
 532       {PIPE_FORMAT_R8G8B8A8_UNORM,         R8G8B8A8_UNORM},
 533       {PIPE_FORMAT_R8G8B8A8_SRGB,          R8G8B8A8_UNORM_SRGB},
 534       {PIPE_FORMAT_R8G8B8X8_UNORM,         R8G8B8X8_UNORM},
 535       {PIPE_FORMAT_R8G8B8X8_SRGB,          R8G8B8X8_UNORM_SRGB},
 536
 537       {PIPE_FORMAT_R8_USCALED,             R8_USCALED},
 538       {PIPE_FORMAT_R8G8_USCALED,           R8G8_USCALED},
 539       {PIPE_FORMAT_R8G8B8_USCALED,         R8G8B8_USCALED},
 540       {PIPE_FORMAT_R8G8B8A8_USCALED,       R8G8B8A8_USCALED},
 541
 542       {PIPE_FORMAT_R8_SNORM,               R8_SNORM},
 543       {PIPE_FORMAT_R8G8_SNORM,             R8G8_SNORM},
 544       {PIPE_FORMAT_R8G8B8_SNORM,           R8G8B8_SNORM},
 545       {PIPE_FORMAT_R8G8B8A8_SNORM,         R8G8B8A8_SNORM},
 546
 547       {PIPE_FORMAT_R8_SSCALED,             R8_SSCALED},
 548       {PIPE_FORMAT_R8G8_SSCALED,           R8G8_SSCALED},
 549       {PIPE_FORMAT_R8G8B8_SSCALED,         R8G8B8_SSCALED},
 550       {PIPE_FORMAT_R8G8B8A8_SSCALED,       R8G8B8A8_SSCALED},
 551
 552       {PIPE_FORMAT_R8_UINT,                R8_UINT},
 553       {PIPE_FORMAT_R8G8_UINT,              R8G8_UINT},
 554       {PIPE_FORMAT_R8G8B8_UINT,            R8G8B8_UINT},
 555       {PIPE_FORMAT_R8G8B8A8_UINT,          R8G8B8A8_UINT},
 556
 557       {PIPE_FORMAT_R8_SINT,                R8_SINT},
 558       {PIPE_FORMAT_R8G8_SINT,              R8G8_SINT},
 559       {PIPE_FORMAT_R8G8B8_SINT,            R8G8B8_SINT},
 560       {PIPE_FORMAT_R8G8B8A8_SINT,          R8G8B8A8_SINT},
 561
 562       /* These formats are valid for vertex data, but should not be used
 563        * for render targets.
 564        */
 565
 566       {PIPE_FORMAT_R32_FIXED,              R32_SFIXED},
 567       {PIPE_FORMAT_R32G32_FIXED,           R32G32_SFIXED},
 568       {PIPE_FORMAT_R32G32B32_FIXED,        R32G32B32_SFIXED},
 569       {PIPE_FORMAT_R32G32B32A32_FIXED,     R32G32B32A32_SFIXED},
 570
 571       {PIPE_FORMAT_R64_FLOAT,              R64_FLOAT},
 572       {PIPE_FORMAT_R64G64_FLOAT,           R64G64_FLOAT},
 573       {PIPE_FORMAT_R64G64B64_FLOAT,        R64G64B64_FLOAT},
 574       {PIPE_FORMAT_R64G64B64A64_FLOAT,     R64G64B64A64_FLOAT},
 575
 576       /* These formats have entries in SWR but don't have Load/StoreTile
 577        * implementations. That means these aren't renderable, and thus having
 578        * a mapping entry here is detrimental.
 579        */
 580       /*
 581
 582       {PIPE_FORMAT_L8_UNORM,               L8_UNORM},
 583       {PIPE_FORMAT_I8_UNORM,               I8_UNORM},
 584       {PIPE_FORMAT_L8A8_UNORM,             L8A8_UNORM},
 585       {PIPE_FORMAT_L16_UNORM,              L16_UNORM},
 586       {PIPE_FORMAT_UYVY,                   YCRCB_SWAPUVY},
 587
 588       {PIPE_FORMAT_L8_SRGB,                L8_UNORM_SRGB},
 589       {PIPE_FORMAT_L8A8_SRGB,              L8A8_UNORM_SRGB},
 590
 591       {PIPE_FORMAT_DXT1_RGBA,              BC1_UNORM},
 592       {PIPE_FORMAT_DXT3_RGBA,              BC2_UNORM},
 593       {PIPE_FORMAT_DXT5_RGBA,              BC3_UNORM},
 594
 595       {PIPE_FORMAT_DXT1_SRGBA,             BC1_UNORM_SRGB},
 596       {PIPE_FORMAT_DXT3_SRGBA,             BC2_UNORM_SRGB},
 597       {PIPE_FORMAT_DXT5_SRGBA,             BC3_UNORM_SRGB},
 598
 599       {PIPE_FORMAT_RGTC1_UNORM,            BC4_UNORM},
 600       {PIPE_FORMAT_RGTC1_SNORM,            BC4_SNORM},
 601       {PIPE_FORMAT_RGTC2_UNORM,            BC5_UNORM},
 602       {PIPE_FORMAT_RGTC2_SNORM,            BC5_SNORM},
 603
 604       {PIPE_FORMAT_L16A16_UNORM,           L16A16_UNORM},
 605       {PIPE_FORMAT_I16_UNORM,              I16_UNORM},
 606       {PIPE_FORMAT_L16_FLOAT,              L16_FLOAT},
 607       {PIPE_FORMAT_L16A16_FLOAT,           L16A16_FLOAT},
 608       {PIPE_FORMAT_I16_FLOAT,              I16_FLOAT},
 609       {PIPE_FORMAT_L32_FLOAT,              L32_FLOAT},
 610       {PIPE_FORMAT_L32A32_FLOAT,           L32A32_FLOAT},
 611       {PIPE_FORMAT_I32_FLOAT,              I32_FLOAT},
 612
 613       {PIPE_FORMAT_I8_UINT,                I8_UINT},
 614       {PIPE_FORMAT_L8_UINT,                L8_UINT},
 615       {PIPE_FORMAT_L8A8_UINT,              L8A8_UINT},
 616
 617       {PIPE_FORMAT_I8_SINT,                I8_SINT},
 618       {PIPE_FORMAT_L8_SINT,                L8_SINT},
 619       {PIPE_FORMAT_L8A8_SINT,              L8A8_SINT},
 620
 621       */
 622    };
 623
 624    auto it = mesa2swr.find(format);
 625    if (it == mesa2swr.end())
 626       return (SWR_FORMAT)-1;
 627    else
 628       return it->second;
 629 }
 630
 631 static boolean
 632 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
 633 {
 634    struct sw_winsys *winsys = screen->winsys;
 635    struct sw_displaytarget *dt;
 636
 637    const unsigned width = align(res->swr.width, res->swr.halign);
 638    const unsigned height = align(res->swr.height, res->swr.valign);
 639
 640    UINT stride;
 641    dt = winsys->displaytarget_create(winsys,
 642                                      res->base.bind,
 643                                      res->base.format,
 644                                      width, height,
 645                                      64, NULL,
 646                                      &stride);
 647
 648    if (dt == NULL)
 649       return FALSE;
 650
 651    void *map = winsys->displaytarget_map(winsys, dt, 0);
 652
 653    res->display_target = dt;
 654    res->swr.pBaseAddress = (uint8_t*) map;
 655
 656    /* Clear the display target surface */
 657    if (map)
 658       memset(map, 0, height * stride);
 659
 660    winsys->displaytarget_unmap(winsys, dt);
 661
 662    return TRUE;
 663 }
 664
 665 static bool
 666 swr_texture_layout(struct swr_screen *screen,
 667                    struct swr_resource *res,
 668                    boolean allocate)
 669 {
 670    struct pipe_resource *pt = &res->base;
 671
 672    pipe_format fmt = pt->format;
 673    const struct util_format_description *desc = util_format_description(fmt);
 674
 675    res->has_depth = util_format_has_depth(desc);
 676    res->has_stencil = util_format_has_stencil(desc);
 677
 678    if (res->has_stencil && !res->has_depth)
 679       fmt = PIPE_FORMAT_R8_UINT;
 680
 681    /* We always use the SWR layout. For 2D and 3D textures this looks like:
 682     *
 683     * |<------- pitch ------->|
 684     * +=======================+-------
 685     * |Array 0                |   ^
 686     * |                       |   |
 687     * |        Level 0        |   |
 688     * |                       |   |
 689     * |                       | qpitch
 690     * +-----------+-----------+   |
 691     * |           | L2L2L2L2  |   |
 692     * |  Level 1  | L3L3      |   |
 693     * |           | L4        |   v
 694     * +===========+===========+-------
 695     * |Array 1                |
 696     * |                       |
 697     * |        Level 0        |
 698     * |                       |
 699     * |                       |
 700     * +-----------+-----------+
 701     * |           | L2L2L2L2  |
 702     * |  Level 1  | L3L3      |
 703     * |           | L4        |
 704     * +===========+===========+
 705     *
 706     * The overall width in bytes is known as the pitch, while the overall
 707     * height in rows is the qpitch. Array slices are laid out logically below
 708     * one another, qpitch rows apart. For 3D surfaces, the "level" values are
 709     * just invalid for the higher array numbers (since depth is also
 710     * minified). 1D and 1D array surfaces are stored effectively the same way,
 711     * except that pitch never plays into it. All the levels are logically
 712     * adjacent to each other on the X axis. The qpitch becomes the number of
 713     * elements between array slices, while the pitch is unused.
 714     *
 715     * Each level's sizes are subject to the valign and halign settings of the
 716     * surface. For compressed formats that swr is unaware of, we will use an
 717     * appropriately-sized uncompressed format, and scale the widths/heights.
 718     *
 719     * This surface is stored inside res->swr. For depth/stencil textures,
 720     * res->secondary will have an identically-laid-out but R8_UINT-formatted
 721     * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
 722     * texels, to simplify map/unmap logic which copies the stencil values
 723     * in/out.
 724     */
 725
 726    res->swr.width = pt->width0;
 727    res->swr.height = pt->height0;
 728    res->swr.type = swr_convert_target_type(pt->target);
 729    res->swr.tileMode = SWR_TILE_NONE;
 730    res->swr.format = mesa_to_swr_format(fmt);
 731    res->swr.numSamples = std::max(1u, pt->nr_samples);
 732
 733    if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
 734       res->swr.halign = KNOB_MACROTILE_X_DIM;
 735       res->swr.valign = KNOB_MACROTILE_Y_DIM;
 736
 737       /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
 738        * surface sample count. */
 739       if (screen->msaa_force_enable) {
 740          res->swr.numSamples = screen->msaa_max_count;
 741          fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
 742                  res->swr.numSamples);
 743       }
 744    } else {
 745       res->swr.halign = 1;
 746       res->swr.valign = 1;
 747    }
 748
 749    unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
 750    unsigned width = align(pt->width0, halign);
 751    if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
 752       for (int level = 1; level <= pt->last_level; level++)
 753          width += align(u_minify(pt->width0, level), halign);
 754       res->swr.pitch = util_format_get_blocksize(fmt);
 755       res->swr.qpitch = util_format_get_nblocksx(fmt, width);
 756    } else {
 757       // The pitch is the overall width of the texture in bytes. Most of the
 758       // time this is the pitch of level 0 since all the other levels fit
 759       // underneath it. However in some degenerate situations, the width of
 760       // level1 + level2 may be larger. In that case, we use those
 761       // widths. This can happen if, e.g. halign is 32, and the width of level
 762       // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
 763       // be 32 each, adding up to 64.
 764       unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
 765       if (pt->last_level > 1) {
 766          width = std::max<uint32_t>(
 767                width,
 768                align(u_minify(pt->width0, 1), halign) +
 769                align(u_minify(pt->width0, 2), halign));
 770       }
 771       res->swr.pitch = util_format_get_stride(fmt, width);
 772
 773       // The qpitch is controlled by either the height of the second LOD, or
 774       // the combination of all the later LODs.
 775       unsigned height = align(pt->height0, valign);
 776       if (pt->last_level == 1) {
 777          height += align(u_minify(pt->height0, 1), valign);
 778       } else if (pt->last_level > 1) {
 779          unsigned level1 = align(u_minify(pt->height0, 1), valign);
 780          unsigned level2 = 0;
 781          for (int level = 2; level <= pt->last_level; level++) {
 782             level2 += align(u_minify(pt->height0, level), valign);
 783          }
 784          height += std::max(level1, level2);
 785       }
 786       res->swr.qpitch = util_format_get_nblocksy(fmt, height);
 787    }
 788
 789    if (pt->target == PIPE_TEXTURE_3D)
 790       res->swr.depth = pt->depth0;
 791    else
 792       res->swr.depth = pt->array_size;
 793
 794    // Fix up swr format if necessary so that LOD offset computation works
 795    if (res->swr.format == (SWR_FORMAT)-1) {
 796       switch (util_format_get_blocksize(fmt)) {
 797       default:
 798          unreachable("Unexpected format block size");
 799       case 1: res->swr.format = R8_UINT; break;
 800       case 2: res->swr.format = R16_UINT; break;
 801       case 4: res->swr.format = R32_UINT; break;
 802       case 8:
 803          if (util_format_is_compressed(fmt))
 804             res->swr.format = BC4_UNORM;
 805          else
 806             res->swr.format = R32G32_UINT;
 807          break;
 808       case 16:
 809          if (util_format_is_compressed(fmt))
 810             res->swr.format = BC5_UNORM;
 811          else
 812             res->swr.format = R32G32B32A32_UINT;
 813          break;
 814       }
 815    }
 816
 817    for (int level = 0; level <= pt->last_level; level++) {
 818       res->mip_offsets[level] =
 819          ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
 820    }
 821
 822    size_t total_size = res->swr.depth * res->swr.qpitch * res->swr.pitch *
 823                        res->swr.numSamples;
 824    if (total_size > SWR_MAX_TEXTURE_SIZE)
 825       return false;
 826
 827    if (allocate) {
 828       res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
 829
 830       if (res->has_depth && res->has_stencil) {
 831          res->secondary = res->swr;
 832          res->secondary.format = R8_UINT;
 833          res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
 834
 835          for (int level = 0; level <= pt->last_level; level++) {
 836             res->secondary_mip_offsets[level] =
 837                ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
 838          }
 839
 840          total_size = res->secondary.depth * res->secondary.qpitch *
 841                       res->secondary.pitch * res->secondary.numSamples;
 842
 843          res->secondary.pBaseAddress = (uint8_t *) AlignedMalloc(total_size,
 844                                                                  64);
 845       }
 846    }
 847
 848    return true;
 849 }
 850
 851 static boolean
 852 swr_can_create_resource(struct pipe_screen *screen,
 853                         const struct pipe_resource *templat)
 854 {
 855    struct swr_resource res;
 856    memset(&res, 0, sizeof(res));
 857    res.base = *templat;
 858    return swr_texture_layout(swr_screen(screen), &res, false);
 859 }
 860
 861 /* Helper function that conditionally creates a single-sample resolve resource
 862  * and attaches it to main multisample resource. */
 863 static boolean
 864 swr_create_resolve_resource(struct pipe_screen *_screen,
 865                             struct swr_resource *msaa_res)
 866 {
 867    struct swr_screen *screen = swr_screen(_screen);
 868
 869    /* If resource is multisample, create a single-sample resolve resource */
 870    if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
 871             !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
 872
 873       /* Create a single-sample copy of the resource.  Copy the original
 874        * resource parameters and set flag to prevent recursion when re-calling
 875        * resource_create */
 876       struct pipe_resource alt_template = msaa_res->base;
 877       alt_template.nr_samples = 0;
 878       alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
 879
 880       /* Note: Display_target is a special single-sample resource, only the
 881        * display_target has been created already. */
 882       if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 883                | PIPE_BIND_SHARED)) {
 884          /* Allocate the multisample buffers. */
 885          if (!swr_texture_layout(screen, msaa_res, true))
 886             return false;
 887
 888          /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
 889           * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
 890          alt_template.bind = PIPE_BIND_RENDER_TARGET;
 891       }
 892
 893       /* Allocate single-sample resolve surface */
 894       struct pipe_resource *alt;
 895       alt = _screen->resource_create(_screen, &alt_template);
 896       if (!alt)
 897          return false;
 898
 899       /* Attach it to the multisample resource */
 900       msaa_res->resolve_target = alt;
 901
 902       /* Hang resolve surface state off the multisample surface state to so
 903        * StoreTiles knows where to resolve the surface. */
 904       msaa_res->swr.pAuxBaseAddress =  (uint8_t *)&swr_resource(alt)->swr;
 905    }
 906
 907    return true; /* success */
 908 }
 909
 910 static struct pipe_resource *
 911 swr_resource_create(struct pipe_screen *_screen,
 912                     const struct pipe_resource *templat)
 913 {
 914    struct swr_screen *screen = swr_screen(_screen);
 915    struct swr_resource *res = CALLOC_STRUCT(swr_resource);
 916    if (!res)
 917       return NULL;
 918
 919    res->base = *templat;
 920    pipe_reference_init(&res->base.reference, 1);
 921    res->base.screen = &screen->base;
 922
 923    if (swr_resource_is_texture(&res->base)) {
 924       if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
 925                             | PIPE_BIND_SHARED)) {
 926          /* displayable surface
 927           * first call swr_texture_layout without allocating to finish
 928           * filling out the SWR_SURFACE_STATE in res */
 929          swr_texture_layout(screen, res, false);
 930          if (!swr_displaytarget_layout(screen, res))
 931             goto fail;
 932       } else {
 933          /* texture map */
 934          if (!swr_texture_layout(screen, res, true))
 935             goto fail;
 936       }
 937
 938       /* If resource was multisample, create resolve resource and attach
 939        * it to multisample resource. */
 940       if (!swr_create_resolve_resource(_screen, res))
 941             goto fail;
 942
 943    } else {
 944       /* other data (vertex buffer, const buffer, etc) */
 945       assert(util_format_get_blocksize(templat->format) == 1);
 946       assert(templat->height0 == 1);
 947       assert(templat->depth0 == 1);
 948       assert(templat->last_level == 0);
 949
 950       /* Easiest to just call swr_texture_layout, as it sets up
 951        * SWR_SURFACE_STATE in res */
 952       if (!swr_texture_layout(screen, res, true))
 953          goto fail;
 954    }
 955
 956    return &res->base;
 957
 958 fail:
 959    FREE(res);
 960    return NULL;
 961 }
 962
 963 static void
 964 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
 965 {
 966    struct swr_screen *screen = swr_screen(p_screen);
 967    struct swr_resource *spr = swr_resource(pt);
 968
 969    if (spr->display_target) {
 970       /* If resource is display target, winsys manages the buffer and will
 971        * free it on displaytarget_destroy. */
 972       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
 973
 974       struct sw_winsys *winsys = screen->winsys;
 975       winsys->displaytarget_destroy(winsys, spr->display_target);
 976
 977       if (spr->swr.numSamples > 1) {
 978          /* Free an attached resolve resource */
 979          struct swr_resource *alt = swr_resource(spr->resolve_target);
 980          swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true);
 981
 982          /* Free multisample buffer */
 983          swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
 984       }
 985    } else {
 986       /* For regular resources, defer deletion */
 987       swr_resource_unused(pt);
 988
 989       if (spr->swr.numSamples > 1) {
 990          /* Free an attached resolve resource */
 991          struct swr_resource *alt = swr_resource(spr->resolve_target);
 992          swr_fence_work_free(screen->flush_fence, alt->swr.pBaseAddress, true);
 993       }
 994
 995       swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
 996       swr_fence_work_free(screen->flush_fence,
 997                           spr->secondary.pBaseAddress, true);
 998
 999       /* If work queue grows too large, submit a fence to force queue to
1000        * drain.  This is mainly to decrease the amount of memory used by the
1001        * piglit streaming-texture-leak test */
1002       if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1003          swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1004    }
1005
1006    FREE(spr);
1007 }
1008
1009
1010 static void
1011 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1012                       struct pipe_resource *resource,
1013                       unsigned level,
1014                       unsigned layer,
1015                       void *context_private,
1016                       struct pipe_box *sub_box)
1017 {
1018    struct swr_screen *screen = swr_screen(p_screen);
1019    struct sw_winsys *winsys = screen->winsys;
1020    struct swr_resource *spr = swr_resource(resource);
1021    struct pipe_context *pipe = screen->pipe;
1022    struct swr_context *ctx = swr_context(pipe);
1023
1024    if (pipe) {
1025       swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1026       swr_resource_unused(resource);
1027       ctx->api.pfnSwrEndFrame(ctx->swrContext);
1028    }
1029
1030    /* Multisample resolved into resolve_target at flush with store_resource */
1031    if (pipe && spr->swr.numSamples > 1) {
1032       struct pipe_resource *resolve_target = spr->resolve_target;
1033
1034       /* Once resolved, copy into display target */
1035       SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1036
1037       void *map = winsys->displaytarget_map(winsys, spr->display_target,
1038                                             PIPE_TRANSFER_WRITE);
1039       memcpy(map, resolve->pBaseAddress, resolve->pitch * resolve->height);
1040       winsys->displaytarget_unmap(winsys, spr->display_target);
1041    }
1042
1043    debug_assert(spr->display_target);
1044    if (spr->display_target)
1045       winsys->displaytarget_display(
1046          winsys, spr->display_target, context_private, sub_box);
1047 }
1048
1049
1050 static void
1051 swr_destroy_screen(struct pipe_screen *p_screen)
1052 {
1053    struct swr_screen *screen = swr_screen(p_screen);
1054    struct sw_winsys *winsys = screen->winsys;
1055
1056    fprintf(stderr, "SWR destroy screen!\n");
1057
1058    swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1059    swr_fence_reference(p_screen, &screen->flush_fence, NULL);
1060
1061    JitDestroyContext(screen->hJitMgr);
1062
1063    if (winsys->destroy)
1064       winsys->destroy(winsys);
1065
1066    FREE(screen);
1067 }
1068
1069
1070 static void
1071 swr_validate_env_options(struct swr_screen *screen)
1072 {
1073    /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1074     * copied to scratch space on a draw.  Past this, the draw will access
1075     * user-buffer directly and then block.  This is faster than queuing many
1076     * large client draws. */
1077    screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1078    int client_copy_limit =
1079       debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1080    if (client_copy_limit > 0)
1081       screen->client_copy_limit = client_copy_limit;
1082
1083    /* XXX msaa under development, disable by default for now */
1084    screen->msaa_max_count = 0; /* was SWR_MAX_NUM_MULTISAMPLES; */
1085
1086    /* validate env override values, within range and power of 2 */
1087    int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 0);
1088    if (msaa_max_count) {
1089       if ((msaa_max_count < 0) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1090             || !util_is_power_of_two(msaa_max_count)) {
1091          fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1092          fprintf(stderr, "must be power of 2 between 1 and %d" \
1093                          " (or 0 to disable msaa)\n",
1094                SWR_MAX_NUM_MULTISAMPLES);
1095          msaa_max_count = 0;
1096       }
1097
1098       fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1099       if (!msaa_max_count)
1100          fprintf(stderr, "(msaa disabled)\n");
1101
1102       screen->msaa_max_count = msaa_max_count;
1103    }
1104
1105    screen->msaa_force_enable = debug_get_bool_option(
1106          "SWR_MSAA_FORCE_ENABLE", false);
1107    if (screen->msaa_force_enable)
1108       fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1109 }
1110
1111
1112 PUBLIC
1113 struct pipe_screen *
1114 swr_create_screen_internal(struct sw_winsys *winsys)
1115 {
1116    struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1117
1118    if (!screen)
1119       return NULL;
1120
1121    if (!lp_build_init()) {
1122       FREE(screen);
1123       return NULL;
1124    }
1125
1126    screen->winsys = winsys;
1127    screen->base.get_name = swr_get_name;
1128    screen->base.get_vendor = swr_get_vendor;
1129    screen->base.is_format_supported = swr_is_format_supported;
1130    screen->base.context_create = swr_create_context;
1131    screen->base.can_create_resource = swr_can_create_resource;
1132
1133    screen->base.destroy = swr_destroy_screen;
1134    screen->base.get_param = swr_get_param;
1135    screen->base.get_shader_param = swr_get_shader_param;
1136    screen->base.get_paramf = swr_get_paramf;
1137
1138    screen->base.resource_create = swr_resource_create;
1139    screen->base.resource_destroy = swr_resource_destroy;
1140
1141    screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1142
1143    // Pass in "" for architecture for run-time determination
1144    screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1145
1146    swr_fence_init(&screen->base);
1147
1148    util_format_s3tc_init();
1149
1150    swr_validate_env_options(screen);
1151
1152    return &screen->base;
1153 }
1154