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gallium: add storage_sample_count parameter into is_format_supported
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned storage_sample_count,
89 unsigned bind)
90 {
91 struct swr_screen *screen = swr_screen(_screen);
92 struct sw_winsys *winsys = screen->winsys;
93 const struct util_format_description *format_desc;
94
95 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
96 || target == PIPE_TEXTURE_1D_ARRAY
97 || target == PIPE_TEXTURE_2D
98 || target == PIPE_TEXTURE_2D_ARRAY
99 || target == PIPE_TEXTURE_RECT
100 || target == PIPE_TEXTURE_3D
101 || target == PIPE_TEXTURE_CUBE
102 || target == PIPE_TEXTURE_CUBE_ARRAY);
103
104 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
105 return false;
106
107 format_desc = util_format_description(format);
108 if (!format_desc)
109 return FALSE;
110
111 if ((sample_count > screen->msaa_max_count)
112 || !util_is_power_of_two_or_zero(sample_count))
113 return FALSE;
114
115 if (bind & PIPE_BIND_DISPLAY_TARGET) {
116 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
117 return FALSE;
118 }
119
120 if (bind & PIPE_BIND_RENDER_TARGET) {
121 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
122 return FALSE;
123
124 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
125 return FALSE;
126
127 /*
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside the state trackers.
131 */
132 if (format_desc->block.width != 1 || format_desc->block.height != 1)
133 return FALSE;
134 }
135
136 if (bind & PIPE_BIND_DEPTH_STENCIL) {
137 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
138 return FALSE;
139
140 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
141 return FALSE;
142 }
143
144 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
145 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
146 return FALSE;
147 }
148
149 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
150 format != PIPE_FORMAT_ETC1_RGB8) {
151 return FALSE;
152 }
153
154 return TRUE;
155 }
156
157 static int
158 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
159 {
160 switch (param) {
161 /* limits */
162 case PIPE_CAP_MAX_RENDER_TARGETS:
163 return PIPE_MAX_COLOR_BUFS;
164 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
165 return SWR_MAX_TEXTURE_2D_LEVELS;
166 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
167 return SWR_MAX_TEXTURE_3D_LEVELS;
168 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
169 return SWR_MAX_TEXTURE_CUBE_LEVELS;
170 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
171 return MAX_SO_STREAMS;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
173 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
174 return MAX_ATTRIBUTES * 4;
175 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
176 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
177 return 1024;
178 case PIPE_CAP_MAX_VERTEX_STREAMS:
179 return 1;
180 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
181 return 2048;
182 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
183 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
184 case PIPE_CAP_MIN_TEXEL_OFFSET:
185 return -8;
186 case PIPE_CAP_MAX_TEXEL_OFFSET:
187 return 7;
188 case PIPE_CAP_GLSL_FEATURE_LEVEL:
189 return 330;
190 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
191 return 140;
192 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
193 return 16;
194 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
195 return 64;
196 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
197 return 65536;
198 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
199 return 0;
200 case PIPE_CAP_MAX_VIEWPORTS:
201 return 1;
202 case PIPE_CAP_ENDIANNESS:
203 return PIPE_ENDIAN_NATIVE;
204 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
205 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
206 return 0;
207
208 /* supported features */
209 case PIPE_CAP_NPOT_TEXTURES:
210 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
211 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
212 case PIPE_CAP_SM3:
213 case PIPE_CAP_POINT_SPRITE:
214 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
215 case PIPE_CAP_OCCLUSION_QUERY:
216 case PIPE_CAP_QUERY_TIME_ELAPSED:
217 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
218 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
219 case PIPE_CAP_TEXTURE_SWIZZLE:
220 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
221 case PIPE_CAP_INDEP_BLEND_ENABLE:
222 case PIPE_CAP_INDEP_BLEND_FUNC:
223 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
224 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
225 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
226 case PIPE_CAP_DEPTH_CLIP_DISABLE:
227 case PIPE_CAP_PRIMITIVE_RESTART:
228 case PIPE_CAP_TGSI_INSTANCEID:
229 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
230 case PIPE_CAP_START_INSTANCE:
231 case PIPE_CAP_SEAMLESS_CUBE_MAP:
232 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
233 case PIPE_CAP_CONDITIONAL_RENDER:
234 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
235 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
236 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
237 case PIPE_CAP_USER_VERTEX_BUFFERS:
238 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
239 case PIPE_CAP_QUERY_TIMESTAMP:
240 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
241 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
242 case PIPE_CAP_DRAW_INDIRECT:
243 case PIPE_CAP_UMA:
244 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
245 case PIPE_CAP_CLIP_HALFZ:
246 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
247 case PIPE_CAP_DEPTH_BOUNDS_TEST:
248 case PIPE_CAP_CLEAR_TEXTURE:
249 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
250 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
251 case PIPE_CAP_CULL_DISTANCE:
252 case PIPE_CAP_CUBE_MAP_ARRAY:
253 case PIPE_CAP_DOUBLES:
254 return 1;
255
256 /* MSAA support
257 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
258 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
259 case PIPE_CAP_TEXTURE_MULTISAMPLE:
260 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
261 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
262 case PIPE_CAP_FAKE_SW_MSAA:
263 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
264
265 /* fetch jit change for 2-4GB buffers requires alignment */
266 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
267 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
268 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
269 return 1;
270
271 /* unsupported features */
272 case PIPE_CAP_ANISOTROPIC_FILTER:
273 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
274 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
275 case PIPE_CAP_SHADER_STENCIL_EXPORT:
276 case PIPE_CAP_TEXTURE_BARRIER:
277 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
278 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
279 case PIPE_CAP_COMPUTE:
280 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
281 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
282 case PIPE_CAP_TGSI_TEXCOORD:
283 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
284 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
285 case PIPE_CAP_TEXTURE_GATHER_SM5:
286 case PIPE_CAP_TEXTURE_QUERY_LOD:
287 case PIPE_CAP_SAMPLE_SHADING:
288 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
289 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
290 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
291 case PIPE_CAP_SAMPLER_VIEW_TARGET:
292 case PIPE_CAP_VERTEXID_NOBASE:
293 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
294 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
295 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
296 case PIPE_CAP_TGSI_TXQS:
297 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
298 case PIPE_CAP_SHAREABLE_SHADERS:
299 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
300 case PIPE_CAP_DRAW_PARAMETERS:
301 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
302 case PIPE_CAP_MULTI_DRAW_INDIRECT:
303 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
304 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
305 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
306 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
307 case PIPE_CAP_INVALIDATE_BUFFER:
308 case PIPE_CAP_GENERATE_MIPMAP:
309 case PIPE_CAP_STRING_MARKER:
310 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
311 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
312 case PIPE_CAP_QUERY_BUFFER_OBJECT:
313 case PIPE_CAP_QUERY_MEMORY_INFO:
314 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
315 case PIPE_CAP_PCI_GROUP:
316 case PIPE_CAP_PCI_BUS:
317 case PIPE_CAP_PCI_DEVICE:
318 case PIPE_CAP_PCI_FUNCTION:
319 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
320 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
321 case PIPE_CAP_TGSI_VOTE:
322 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
323 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
324 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
325 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
326 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
327 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
328 case PIPE_CAP_NATIVE_FENCE_FD:
329 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
330 case PIPE_CAP_TGSI_FS_FBFETCH:
331 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
332 case PIPE_CAP_INT64:
333 case PIPE_CAP_INT64_DIVMOD:
334 case PIPE_CAP_TGSI_TEX_TXF_LZ:
335 case PIPE_CAP_TGSI_CLOCK:
336 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
337 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
338 case PIPE_CAP_TGSI_BALLOT:
339 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
340 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
341 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
342 case PIPE_CAP_POST_DEPTH_COVERAGE:
343 case PIPE_CAP_BINDLESS_TEXTURE:
344 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
345 case PIPE_CAP_QUERY_SO_OVERFLOW:
346 case PIPE_CAP_MEMOBJ:
347 case PIPE_CAP_LOAD_CONSTBUF:
348 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
349 case PIPE_CAP_TILE_RASTER_ORDER:
350 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
351 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
352 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
353 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
354 case PIPE_CAP_FENCE_SIGNAL:
355 case PIPE_CAP_CONSTBUF0_FLAGS:
356 case PIPE_CAP_PACKED_UNIFORMS:
357 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
358 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
359 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
360 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
361 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
362 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
363 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
364 return 0;
365
366 case PIPE_CAP_VENDOR_ID:
367 return 0xFFFFFFFF;
368 case PIPE_CAP_DEVICE_ID:
369 return 0xFFFFFFFF;
370 case PIPE_CAP_ACCELERATED:
371 return 0;
372 case PIPE_CAP_VIDEO_MEMORY: {
373 /* XXX: Do we want to return the full amount of system memory ? */
374 uint64_t system_memory;
375
376 if (!os_get_total_physical_memory(&system_memory))
377 return 0;
378
379 return (int)(system_memory >> 20);
380 }
381 }
382
383 /* should only get here on unhandled cases */
384 debug_printf("Unexpected PIPE_CAP %d query\n", param);
385 return 0;
386 }
387
388 static int
389 swr_get_shader_param(struct pipe_screen *screen,
390 enum pipe_shader_type shader,
391 enum pipe_shader_cap param)
392 {
393 if (shader == PIPE_SHADER_VERTEX ||
394 shader == PIPE_SHADER_FRAGMENT ||
395 shader == PIPE_SHADER_GEOMETRY)
396 return gallivm_get_shader_param(param);
397
398 // Todo: tesselation, compute
399 return 0;
400 }
401
402
403 static float
404 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
405 {
406 switch (param) {
407 case PIPE_CAPF_MAX_LINE_WIDTH:
408 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
409 case PIPE_CAPF_MAX_POINT_WIDTH:
410 return 255.0; /* arbitrary */
411 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
412 return 0.0;
413 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
414 return 0.0;
415 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
416 return 16.0; /* arbitrary */
417 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
418 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
419 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
420 return 0.0f;
421 }
422 /* should only get here on unhandled cases */
423 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
424 return 0.0;
425 }
426
427 SWR_FORMAT
428 mesa_to_swr_format(enum pipe_format format)
429 {
430 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
431 /* depth / stencil */
432 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
433 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
434 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
435 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
436 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
437
438 /* alpha */
439 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
440 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
441 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
442 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
443
444 /* odd sizes, bgr */
445 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
446 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
447 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
448 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
449 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
450 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
451 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
452 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
453 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
454
455 /* rgb10a2 */
456 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
457 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
458 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
459 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
460 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
461
462 /* rgb10x2 */
463 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
464
465 /* bgr10a2 */
466 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
467 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
468 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
469 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
470 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
471
472 /* bgr10x2 */
473 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
474
475 /* r11g11b10 */
476 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
477
478 /* 32 bits per component */
479 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
480 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
481 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
482 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
483 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
484
485 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
486 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
487 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
488 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
489
490 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
491 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
492 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
493 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
494
495 {PIPE_FORMAT_R32_UINT, R32_UINT},
496 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
497 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
498 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
499
500 {PIPE_FORMAT_R32_SINT, R32_SINT},
501 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
502 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
503 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
504
505 /* 16 bits per component */
506 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
507 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
508 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
509 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
510 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
511
512 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
513 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
514 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
515 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
516
517 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
518 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
519 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
520 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
521
522 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
523 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
524 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
525 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
526
527 {PIPE_FORMAT_R16_UINT, R16_UINT},
528 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
529 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
530 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
531
532 {PIPE_FORMAT_R16_SINT, R16_SINT},
533 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
534 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
535 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
536
537 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
538 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
539 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
540 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
541 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
542
543 /* 8 bits per component */
544 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
545 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
546 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
547 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
548 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
549 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
550 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
551 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
552
553 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
554 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
555 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
556 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
557
558 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
559 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
560 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
561 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
562
563 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
564 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
565 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
566 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
567
568 {PIPE_FORMAT_R8_UINT, R8_UINT},
569 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
570 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
571 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
572
573 {PIPE_FORMAT_R8_SINT, R8_SINT},
574 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
575 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
576 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
577
578 /* These formats are valid for vertex data, but should not be used
579 * for render targets.
580 */
581
582 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
583 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
584 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
585 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
586
587 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
588 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
589 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
590 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
591
592 /* These formats have entries in SWR but don't have Load/StoreTile
593 * implementations. That means these aren't renderable, and thus having
594 * a mapping entry here is detrimental.
595 */
596 /*
597
598 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
599 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
600 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
601 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
602 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
603
604 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
605 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
606
607 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
608 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
609 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
610
611 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
612 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
613 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
614
615 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
616 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
617 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
618 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
619
620 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
621 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
622 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
623 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
624 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
625 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
626 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
627 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
628
629 {PIPE_FORMAT_I8_UINT, I8_UINT},
630 {PIPE_FORMAT_L8_UINT, L8_UINT},
631 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
632
633 {PIPE_FORMAT_I8_SINT, I8_SINT},
634 {PIPE_FORMAT_L8_SINT, L8_SINT},
635 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
636
637 */
638 };
639
640 auto it = mesa2swr.find(format);
641 if (it == mesa2swr.end())
642 return (SWR_FORMAT)-1;
643 else
644 return it->second;
645 }
646
647 static boolean
648 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
649 {
650 struct sw_winsys *winsys = screen->winsys;
651 struct sw_displaytarget *dt;
652
653 const unsigned width = align(res->swr.width, res->swr.halign);
654 const unsigned height = align(res->swr.height, res->swr.valign);
655
656 UINT stride;
657 dt = winsys->displaytarget_create(winsys,
658 res->base.bind,
659 res->base.format,
660 width, height,
661 64, NULL,
662 &stride);
663
664 if (dt == NULL)
665 return FALSE;
666
667 void *map = winsys->displaytarget_map(winsys, dt, 0);
668
669 res->display_target = dt;
670 res->swr.xpBaseAddress = (gfxptr_t)map;
671
672 /* Clear the display target surface */
673 if (map)
674 memset(map, 0, height * stride);
675
676 winsys->displaytarget_unmap(winsys, dt);
677
678 return TRUE;
679 }
680
681 static bool
682 swr_texture_layout(struct swr_screen *screen,
683 struct swr_resource *res,
684 boolean allocate)
685 {
686 struct pipe_resource *pt = &res->base;
687
688 pipe_format fmt = pt->format;
689 const struct util_format_description *desc = util_format_description(fmt);
690
691 res->has_depth = util_format_has_depth(desc);
692 res->has_stencil = util_format_has_stencil(desc);
693
694 if (res->has_stencil && !res->has_depth)
695 fmt = PIPE_FORMAT_R8_UINT;
696
697 /* We always use the SWR layout. For 2D and 3D textures this looks like:
698 *
699 * |<------- pitch ------->|
700 * +=======================+-------
701 * |Array 0 | ^
702 * | | |
703 * | Level 0 | |
704 * | | |
705 * | | qpitch
706 * +-----------+-----------+ |
707 * | | L2L2L2L2 | |
708 * | Level 1 | L3L3 | |
709 * | | L4 | v
710 * +===========+===========+-------
711 * |Array 1 |
712 * | |
713 * | Level 0 |
714 * | |
715 * | |
716 * +-----------+-----------+
717 * | | L2L2L2L2 |
718 * | Level 1 | L3L3 |
719 * | | L4 |
720 * +===========+===========+
721 *
722 * The overall width in bytes is known as the pitch, while the overall
723 * height in rows is the qpitch. Array slices are laid out logically below
724 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
725 * just invalid for the higher array numbers (since depth is also
726 * minified). 1D and 1D array surfaces are stored effectively the same way,
727 * except that pitch never plays into it. All the levels are logically
728 * adjacent to each other on the X axis. The qpitch becomes the number of
729 * elements between array slices, while the pitch is unused.
730 *
731 * Each level's sizes are subject to the valign and halign settings of the
732 * surface. For compressed formats that swr is unaware of, we will use an
733 * appropriately-sized uncompressed format, and scale the widths/heights.
734 *
735 * This surface is stored inside res->swr. For depth/stencil textures,
736 * res->secondary will have an identically-laid-out but R8_UINT-formatted
737 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
738 * texels, to simplify map/unmap logic which copies the stencil values
739 * in/out.
740 */
741
742 res->swr.width = pt->width0;
743 res->swr.height = pt->height0;
744 res->swr.type = swr_convert_target_type(pt->target);
745 res->swr.tileMode = SWR_TILE_NONE;
746 res->swr.format = mesa_to_swr_format(fmt);
747 res->swr.numSamples = std::max(1u, pt->nr_samples);
748
749 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
750 res->swr.halign = KNOB_MACROTILE_X_DIM;
751 res->swr.valign = KNOB_MACROTILE_Y_DIM;
752
753 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
754 * surface sample count. */
755 if (screen->msaa_force_enable) {
756 res->swr.numSamples = screen->msaa_max_count;
757 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
758 res->swr.numSamples);
759 }
760 } else {
761 res->swr.halign = 1;
762 res->swr.valign = 1;
763 }
764
765 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
766 unsigned width = align(pt->width0, halign);
767 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
768 for (int level = 1; level <= pt->last_level; level++)
769 width += align(u_minify(pt->width0, level), halign);
770 res->swr.pitch = util_format_get_blocksize(fmt);
771 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
772 } else {
773 // The pitch is the overall width of the texture in bytes. Most of the
774 // time this is the pitch of level 0 since all the other levels fit
775 // underneath it. However in some degenerate situations, the width of
776 // level1 + level2 may be larger. In that case, we use those
777 // widths. This can happen if, e.g. halign is 32, and the width of level
778 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
779 // be 32 each, adding up to 64.
780 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
781 if (pt->last_level > 1) {
782 width = std::max<uint32_t>(
783 width,
784 align(u_minify(pt->width0, 1), halign) +
785 align(u_minify(pt->width0, 2), halign));
786 }
787 res->swr.pitch = util_format_get_stride(fmt, width);
788
789 // The qpitch is controlled by either the height of the second LOD, or
790 // the combination of all the later LODs.
791 unsigned height = align(pt->height0, valign);
792 if (pt->last_level == 1) {
793 height += align(u_minify(pt->height0, 1), valign);
794 } else if (pt->last_level > 1) {
795 unsigned level1 = align(u_minify(pt->height0, 1), valign);
796 unsigned level2 = 0;
797 for (int level = 2; level <= pt->last_level; level++) {
798 level2 += align(u_minify(pt->height0, level), valign);
799 }
800 height += std::max(level1, level2);
801 }
802 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
803 }
804
805 if (pt->target == PIPE_TEXTURE_3D)
806 res->swr.depth = pt->depth0;
807 else
808 res->swr.depth = pt->array_size;
809
810 // Fix up swr format if necessary so that LOD offset computation works
811 if (res->swr.format == (SWR_FORMAT)-1) {
812 switch (util_format_get_blocksize(fmt)) {
813 default:
814 unreachable("Unexpected format block size");
815 case 1: res->swr.format = R8_UINT; break;
816 case 2: res->swr.format = R16_UINT; break;
817 case 4: res->swr.format = R32_UINT; break;
818 case 8:
819 if (util_format_is_compressed(fmt))
820 res->swr.format = BC4_UNORM;
821 else
822 res->swr.format = R32G32_UINT;
823 break;
824 case 16:
825 if (util_format_is_compressed(fmt))
826 res->swr.format = BC5_UNORM;
827 else
828 res->swr.format = R32G32B32A32_UINT;
829 break;
830 }
831 }
832
833 for (int level = 0; level <= pt->last_level; level++) {
834 res->mip_offsets[level] =
835 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
836 }
837
838 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
839 res->swr.pitch * res->swr.numSamples;
840 if (total_size > SWR_MAX_TEXTURE_SIZE)
841 return false;
842
843 if (allocate) {
844 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
845 if (!res->swr.xpBaseAddress)
846 return false;
847
848 if (res->has_depth && res->has_stencil) {
849 res->secondary = res->swr;
850 res->secondary.format = R8_UINT;
851 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
852
853 for (int level = 0; level <= pt->last_level; level++) {
854 res->secondary_mip_offsets[level] =
855 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
856 }
857
858 total_size = res->secondary.depth * res->secondary.qpitch *
859 res->secondary.pitch * res->secondary.numSamples;
860
861 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
862 if (!res->secondary.xpBaseAddress) {
863 AlignedFree((void *)res->swr.xpBaseAddress);
864 return false;
865 }
866 }
867 }
868
869 return true;
870 }
871
872 static boolean
873 swr_can_create_resource(struct pipe_screen *screen,
874 const struct pipe_resource *templat)
875 {
876 struct swr_resource res;
877 memset(&res, 0, sizeof(res));
878 res.base = *templat;
879 return swr_texture_layout(swr_screen(screen), &res, false);
880 }
881
882 /* Helper function that conditionally creates a single-sample resolve resource
883 * and attaches it to main multisample resource. */
884 static boolean
885 swr_create_resolve_resource(struct pipe_screen *_screen,
886 struct swr_resource *msaa_res)
887 {
888 struct swr_screen *screen = swr_screen(_screen);
889
890 /* If resource is multisample, create a single-sample resolve resource */
891 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
892 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
893
894 /* Create a single-sample copy of the resource. Copy the original
895 * resource parameters and set flag to prevent recursion when re-calling
896 * resource_create */
897 struct pipe_resource alt_template = msaa_res->base;
898 alt_template.nr_samples = 0;
899 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
900
901 /* Note: Display_target is a special single-sample resource, only the
902 * display_target has been created already. */
903 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
904 | PIPE_BIND_SHARED)) {
905 /* Allocate the multisample buffers. */
906 if (!swr_texture_layout(screen, msaa_res, true))
907 return false;
908
909 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
910 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
911 alt_template.bind = PIPE_BIND_RENDER_TARGET;
912 }
913
914 /* Allocate single-sample resolve surface */
915 struct pipe_resource *alt;
916 alt = _screen->resource_create(_screen, &alt_template);
917 if (!alt)
918 return false;
919
920 /* Attach it to the multisample resource */
921 msaa_res->resolve_target = alt;
922
923 /* Hang resolve surface state off the multisample surface state to so
924 * StoreTiles knows where to resolve the surface. */
925 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
926 }
927
928 return true; /* success */
929 }
930
931 static struct pipe_resource *
932 swr_resource_create(struct pipe_screen *_screen,
933 const struct pipe_resource *templat)
934 {
935 struct swr_screen *screen = swr_screen(_screen);
936 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
937 if (!res)
938 return NULL;
939
940 res->base = *templat;
941 pipe_reference_init(&res->base.reference, 1);
942 res->base.screen = &screen->base;
943
944 if (swr_resource_is_texture(&res->base)) {
945 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
946 | PIPE_BIND_SHARED)) {
947 /* displayable surface
948 * first call swr_texture_layout without allocating to finish
949 * filling out the SWR_SURFACE_STATE in res */
950 swr_texture_layout(screen, res, false);
951 if (!swr_displaytarget_layout(screen, res))
952 goto fail;
953 } else {
954 /* texture map */
955 if (!swr_texture_layout(screen, res, true))
956 goto fail;
957 }
958
959 /* If resource was multisample, create resolve resource and attach
960 * it to multisample resource. */
961 if (!swr_create_resolve_resource(_screen, res))
962 goto fail;
963
964 } else {
965 /* other data (vertex buffer, const buffer, etc) */
966 assert(util_format_get_blocksize(templat->format) == 1);
967 assert(templat->height0 == 1);
968 assert(templat->depth0 == 1);
969 assert(templat->last_level == 0);
970
971 /* Easiest to just call swr_texture_layout, as it sets up
972 * SWR_SURFACE_STATE in res */
973 if (!swr_texture_layout(screen, res, true))
974 goto fail;
975 }
976
977 return &res->base;
978
979 fail:
980 FREE(res);
981 return NULL;
982 }
983
984 static void
985 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
986 {
987 struct swr_screen *screen = swr_screen(p_screen);
988 struct swr_resource *spr = swr_resource(pt);
989
990 if (spr->display_target) {
991 /* If resource is display target, winsys manages the buffer and will
992 * free it on displaytarget_destroy. */
993 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
994
995 struct sw_winsys *winsys = screen->winsys;
996 winsys->displaytarget_destroy(winsys, spr->display_target);
997
998 if (spr->swr.numSamples > 1) {
999 /* Free an attached resolve resource */
1000 struct swr_resource *alt = swr_resource(spr->resolve_target);
1001 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1002
1003 /* Free multisample buffer */
1004 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1005 }
1006 } else {
1007 /* For regular resources, defer deletion */
1008 swr_resource_unused(pt);
1009
1010 if (spr->swr.numSamples > 1) {
1011 /* Free an attached resolve resource */
1012 struct swr_resource *alt = swr_resource(spr->resolve_target);
1013 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1014 }
1015
1016 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1017 swr_fence_work_free(screen->flush_fence,
1018 (void*)(spr->secondary.xpBaseAddress), true);
1019
1020 /* If work queue grows too large, submit a fence to force queue to
1021 * drain. This is mainly to decrease the amount of memory used by the
1022 * piglit streaming-texture-leak test */
1023 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1024 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1025 }
1026
1027 FREE(spr);
1028 }
1029
1030
1031 static void
1032 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1033 struct pipe_resource *resource,
1034 unsigned level,
1035 unsigned layer,
1036 void *context_private,
1037 struct pipe_box *sub_box)
1038 {
1039 struct swr_screen *screen = swr_screen(p_screen);
1040 struct sw_winsys *winsys = screen->winsys;
1041 struct swr_resource *spr = swr_resource(resource);
1042 struct pipe_context *pipe = screen->pipe;
1043 struct swr_context *ctx = swr_context(pipe);
1044
1045 if (pipe) {
1046 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1047 swr_resource_unused(resource);
1048 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1049 }
1050
1051 /* Multisample resolved into resolve_target at flush with store_resource */
1052 if (pipe && spr->swr.numSamples > 1) {
1053 struct pipe_resource *resolve_target = spr->resolve_target;
1054
1055 /* Once resolved, copy into display target */
1056 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1057
1058 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1059 PIPE_TRANSFER_WRITE);
1060 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1061 winsys->displaytarget_unmap(winsys, spr->display_target);
1062 }
1063
1064 debug_assert(spr->display_target);
1065 if (spr->display_target)
1066 winsys->displaytarget_display(
1067 winsys, spr->display_target, context_private, sub_box);
1068 }
1069
1070
1071 void
1072 swr_destroy_screen_internal(struct swr_screen **screen)
1073 {
1074 struct pipe_screen *p_screen = &(*screen)->base;
1075
1076 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1077 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1078
1079 JitDestroyContext((*screen)->hJitMgr);
1080
1081 if ((*screen)->pLibrary)
1082 util_dl_close((*screen)->pLibrary);
1083
1084 FREE(*screen);
1085 *screen = NULL;
1086 }
1087
1088
1089 static void
1090 swr_destroy_screen(struct pipe_screen *p_screen)
1091 {
1092 struct swr_screen *screen = swr_screen(p_screen);
1093 struct sw_winsys *winsys = screen->winsys;
1094
1095 fprintf(stderr, "SWR destroy screen!\n");
1096
1097 if (winsys->destroy)
1098 winsys->destroy(winsys);
1099
1100 swr_destroy_screen_internal(&screen);
1101 }
1102
1103
1104 static void
1105 swr_validate_env_options(struct swr_screen *screen)
1106 {
1107 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1108 * copied to scratch space on a draw. Past this, the draw will access
1109 * user-buffer directly and then block. This is faster than queuing many
1110 * large client draws. */
1111 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1112 int client_copy_limit =
1113 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1114 if (client_copy_limit > 0)
1115 screen->client_copy_limit = client_copy_limit;
1116
1117 /* XXX msaa under development, disable by default for now */
1118 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1119
1120 /* validate env override values, within range and power of 2 */
1121 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1122 if (msaa_max_count != 1) {
1123 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1124 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1125 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1126 fprintf(stderr, "must be power of 2 between 1 and %d" \
1127 " (or 1 to disable msaa)\n",
1128 SWR_MAX_NUM_MULTISAMPLES);
1129 msaa_max_count = 1;
1130 }
1131
1132 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1133 if (msaa_max_count == 1)
1134 fprintf(stderr, "(msaa disabled)\n");
1135
1136 screen->msaa_max_count = msaa_max_count;
1137 }
1138
1139 screen->msaa_force_enable = debug_get_bool_option(
1140 "SWR_MSAA_FORCE_ENABLE", false);
1141 if (screen->msaa_force_enable)
1142 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1143 }
1144
1145
1146 PUBLIC
1147 struct pipe_screen *
1148 swr_create_screen_internal(struct sw_winsys *winsys)
1149 {
1150 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1151 memset(screen, 0, sizeof(struct swr_screen));
1152
1153 if (!screen)
1154 return NULL;
1155
1156 if (!lp_build_init()) {
1157 FREE(screen);
1158 return NULL;
1159 }
1160
1161 screen->winsys = winsys;
1162 screen->base.get_name = swr_get_name;
1163 screen->base.get_vendor = swr_get_vendor;
1164 screen->base.is_format_supported = swr_is_format_supported;
1165 screen->base.context_create = swr_create_context;
1166 screen->base.can_create_resource = swr_can_create_resource;
1167
1168 screen->base.destroy = swr_destroy_screen;
1169 screen->base.get_param = swr_get_param;
1170 screen->base.get_shader_param = swr_get_shader_param;
1171 screen->base.get_paramf = swr_get_paramf;
1172
1173 screen->base.resource_create = swr_resource_create;
1174 screen->base.resource_destroy = swr_resource_destroy;
1175
1176 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1177
1178 // Pass in "" for architecture for run-time determination
1179 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1180
1181 swr_fence_init(&screen->base);
1182
1183 swr_validate_env_options(screen);
1184
1185 return &screen->base;
1186 }
1187