projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
swr/rast: Enable ARB_GL_texture_buffer_range
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39 #include "util/u_screen.h"
40
41 #include "state_tracker/sw_winsys.h"
42
43 #include "jit_api.h"
44
45 #include "memory/TilingFunctions.h"
46
47 #include <stdio.h>
48 #include <map>
49
50 /*
51 * Max texture sizes
52 * XXX Check max texture size values against core and sampler.
53 */
54 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
55 #define SWR_MAX_TEXTURE_2D_SIZE 8192
56 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
57 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
58 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
59
60 /* Default max client_copy_limit */
61 #define SWR_CLIENT_COPY_LIMIT 8192
62
63 /* Flag indicates creation of alternate surface, to prevent recursive loop
64 * in resource creation when msaa_force_enable is set. */
65 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
66
67
68 static const char *
69 swr_get_name(struct pipe_screen *screen)
70 {
71 static char buf[100];
72 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
73 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
74 lp_native_vector_width );
75 return buf;
76 }
77
78 static const char *
79 swr_get_vendor(struct pipe_screen *screen)
80 {
81 return "Intel Corporation";
82 }
83
84 static boolean
85 swr_is_format_supported(struct pipe_screen *_screen,
86 enum pipe_format format,
87 enum pipe_texture_target target,
88 unsigned sample_count,
89 unsigned storage_sample_count,
90 unsigned bind)
91 {
92 struct swr_screen *screen = swr_screen(_screen);
93 struct sw_winsys *winsys = screen->winsys;
94 const struct util_format_description *format_desc;
95
96 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
97 || target == PIPE_TEXTURE_1D_ARRAY
98 || target == PIPE_TEXTURE_2D
99 || target == PIPE_TEXTURE_2D_ARRAY
100 || target == PIPE_TEXTURE_RECT
101 || target == PIPE_TEXTURE_3D
102 || target == PIPE_TEXTURE_CUBE
103 || target == PIPE_TEXTURE_CUBE_ARRAY);
104
105 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
106 return false;
107
108 format_desc = util_format_description(format);
109 if (!format_desc)
110 return FALSE;
111
112 if ((sample_count > screen->msaa_max_count)
113 || !util_is_power_of_two_or_zero(sample_count))
114 return FALSE;
115
116 if (bind & PIPE_BIND_DISPLAY_TARGET) {
117 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
118 return FALSE;
119 }
120
121 if (bind & PIPE_BIND_RENDER_TARGET) {
122 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
123 return FALSE;
124
125 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
126 return FALSE;
127
128 /*
129 * Although possible, it is unnatural to render into compressed or YUV
130 * surfaces. So disable these here to avoid going into weird paths
131 * inside the state trackers.
132 */
133 if (format_desc->block.width != 1 || format_desc->block.height != 1)
134 return FALSE;
135 }
136
137 if (bind & PIPE_BIND_DEPTH_STENCIL) {
138 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
139 return FALSE;
140
141 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
142 return FALSE;
143 }
144
145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
146 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
147 return FALSE;
148 }
149
150 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
151 format != PIPE_FORMAT_ETC1_RGB8) {
152 return FALSE;
153 }
154
155 return TRUE;
156 }
157
158 static int
159 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
160 {
161 switch (param) {
162 /* limits */
163 case PIPE_CAP_MAX_RENDER_TARGETS:
164 return PIPE_MAX_COLOR_BUFS;
165 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
166 return SWR_MAX_TEXTURE_2D_SIZE;
167 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
168 return SWR_MAX_TEXTURE_3D_LEVELS;
169 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
170 return SWR_MAX_TEXTURE_CUBE_LEVELS;
171 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
172 return MAX_SO_STREAMS;
173 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
174 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
175 return MAX_ATTRIBUTES * 4;
176 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
177 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
178 return 1024;
179 case PIPE_CAP_MAX_VERTEX_STREAMS:
180 return 1;
181 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
182 return 2048;
183 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
184 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
185 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
186 case PIPE_CAP_MIN_TEXEL_OFFSET:
187 return -8;
188 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
189 case PIPE_CAP_MAX_TEXEL_OFFSET:
190 return 7;
191 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
192 return 4;
193 case PIPE_CAP_GLSL_FEATURE_LEVEL:
194 return 330;
195 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
196 return 140;
197 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
198 return 16;
199 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
200 return 64;
201 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
202 return 65536;
203 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
204 return 1;
205 case PIPE_CAP_MAX_VIEWPORTS:
206 return 1;
207 case PIPE_CAP_ENDIANNESS:
208 return PIPE_ENDIAN_NATIVE;
209 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
210 return 0;
211
212 /* supported features */
213 case PIPE_CAP_NPOT_TEXTURES:
214 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
215 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
216 case PIPE_CAP_SM3:
217 case PIPE_CAP_POINT_SPRITE:
218 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
219 case PIPE_CAP_OCCLUSION_QUERY:
220 case PIPE_CAP_QUERY_TIME_ELAPSED:
221 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
222 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
223 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
224 case PIPE_CAP_TEXTURE_SWIZZLE:
225 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
226 case PIPE_CAP_INDEP_BLEND_ENABLE:
227 case PIPE_CAP_INDEP_BLEND_FUNC:
228 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
229 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
230 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
231 case PIPE_CAP_DEPTH_CLIP_DISABLE:
232 case PIPE_CAP_PRIMITIVE_RESTART:
233 case PIPE_CAP_TGSI_INSTANCEID:
234 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
235 case PIPE_CAP_START_INSTANCE:
236 case PIPE_CAP_SEAMLESS_CUBE_MAP:
237 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
238 case PIPE_CAP_CONDITIONAL_RENDER:
239 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
240 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
241 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
242 case PIPE_CAP_USER_VERTEX_BUFFERS:
243 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
244 case PIPE_CAP_QUERY_TIMESTAMP:
245 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
246 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
247 case PIPE_CAP_DRAW_INDIRECT:
248 case PIPE_CAP_UMA:
249 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
250 case PIPE_CAP_CLIP_HALFZ:
251 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
252 case PIPE_CAP_DEPTH_BOUNDS_TEST:
253 case PIPE_CAP_CLEAR_TEXTURE:
254 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
255 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
256 case PIPE_CAP_CULL_DISTANCE:
257 case PIPE_CAP_CUBE_MAP_ARRAY:
258 case PIPE_CAP_DOUBLES:
259 case PIPE_CAP_TEXTURE_QUERY_LOD:
260 return 1;
261
262 /* MSAA support
263 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
264 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
265 case PIPE_CAP_TEXTURE_MULTISAMPLE:
266 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
267 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
268 case PIPE_CAP_FAKE_SW_MSAA:
269 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
270
271 /* fetch jit change for 2-4GB buffers requires alignment */
272 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
273 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
274 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
275 return 1;
276
277 /* unsupported features */
278 case PIPE_CAP_ANISOTROPIC_FILTER:
279 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
280 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
281 case PIPE_CAP_SHADER_STENCIL_EXPORT:
282 case PIPE_CAP_TEXTURE_BARRIER:
283 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
284 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
285 case PIPE_CAP_COMPUTE:
286 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
287 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
288 case PIPE_CAP_TGSI_TEXCOORD:
289 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
290 case PIPE_CAP_TEXTURE_GATHER_SM5:
291 case PIPE_CAP_SAMPLE_SHADING:
292 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
293 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
294 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
295 case PIPE_CAP_SAMPLER_VIEW_TARGET:
296 case PIPE_CAP_VERTEXID_NOBASE:
297 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
298 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
299 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
300 case PIPE_CAP_TGSI_TXQS:
301 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
302 case PIPE_CAP_SHAREABLE_SHADERS:
303 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
304 case PIPE_CAP_DRAW_PARAMETERS:
305 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
306 case PIPE_CAP_MULTI_DRAW_INDIRECT:
307 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
308 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
309 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
310 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
311 case PIPE_CAP_INVALIDATE_BUFFER:
312 case PIPE_CAP_GENERATE_MIPMAP:
313 case PIPE_CAP_STRING_MARKER:
314 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
315 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
316 case PIPE_CAP_QUERY_BUFFER_OBJECT:
317 case PIPE_CAP_QUERY_MEMORY_INFO:
318 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
319 case PIPE_CAP_PCI_GROUP:
320 case PIPE_CAP_PCI_BUS:
321 case PIPE_CAP_PCI_DEVICE:
322 case PIPE_CAP_PCI_FUNCTION:
323 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
324 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
325 case PIPE_CAP_TGSI_VOTE:
326 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
327 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
328 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
329 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
330 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
331 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
332 case PIPE_CAP_NATIVE_FENCE_FD:
333 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
334 case PIPE_CAP_FBFETCH:
335 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
336 case PIPE_CAP_INT64:
337 case PIPE_CAP_INT64_DIVMOD:
338 case PIPE_CAP_TGSI_TEX_TXF_LZ:
339 case PIPE_CAP_TGSI_CLOCK:
340 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
341 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
342 case PIPE_CAP_TGSI_BALLOT:
343 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
344 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
345 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
346 case PIPE_CAP_POST_DEPTH_COVERAGE:
347 case PIPE_CAP_BINDLESS_TEXTURE:
348 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
349 case PIPE_CAP_QUERY_SO_OVERFLOW:
350 case PIPE_CAP_MEMOBJ:
351 case PIPE_CAP_LOAD_CONSTBUF:
352 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
353 case PIPE_CAP_TILE_RASTER_ORDER:
354 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
355 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
356 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
357 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
358 case PIPE_CAP_FENCE_SIGNAL:
359 case PIPE_CAP_CONSTBUF0_FLAGS:
360 case PIPE_CAP_PACKED_UNIFORMS:
361 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
362 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
363 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
364 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
365 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
366 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
367 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
368 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
369 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
370 return 0;
371 case PIPE_CAP_MAX_GS_INVOCATIONS:
372 return 32;
373 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
374 return 1 << 27;
375 case PIPE_CAP_MAX_VARYINGS:
376 return 32;
377
378 case PIPE_CAP_VENDOR_ID:
379 return 0xFFFFFFFF;
380 case PIPE_CAP_DEVICE_ID:
381 return 0xFFFFFFFF;
382 case PIPE_CAP_ACCELERATED:
383 return 0;
384 case PIPE_CAP_VIDEO_MEMORY: {
385 /* XXX: Do we want to return the full amount of system memory ? */
386 uint64_t system_memory;
387
388 if (!os_get_total_physical_memory(&system_memory))
389 return 0;
390
391 return (int)(system_memory >> 20);
392 }
393 default:
394 return u_pipe_screen_get_param_defaults(screen, param);
395 }
396 }
397
398 static int
399 swr_get_shader_param(struct pipe_screen *screen,
400 enum pipe_shader_type shader,
401 enum pipe_shader_cap param)
402 {
403 if (shader == PIPE_SHADER_VERTEX ||
404 shader == PIPE_SHADER_FRAGMENT ||
405 shader == PIPE_SHADER_GEOMETRY)
406 return gallivm_get_shader_param(param);
407
408 // Todo: tesselation, compute
409 return 0;
410 }
411
412
413 static float
414 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
415 {
416 switch (param) {
417 case PIPE_CAPF_MAX_LINE_WIDTH:
418 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
419 case PIPE_CAPF_MAX_POINT_WIDTH:
420 return 255.0; /* arbitrary */
421 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
422 return 0.0;
423 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
424 return 0.0;
425 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
426 return 16.0; /* arbitrary */
427 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
428 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
429 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
430 return 0.0f;
431 }
432 /* should only get here on unhandled cases */
433 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
434 return 0.0;
435 }
436
437 SWR_FORMAT
438 mesa_to_swr_format(enum pipe_format format)
439 {
440 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
441 /* depth / stencil */
442 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
443 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
444 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
445 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
446 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
447
448 /* alpha */
449 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
450 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
451 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
452 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
453
454 /* odd sizes, bgr */
455 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
456 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
457 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
458 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
459 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
460 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
461 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
462 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
463 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
464
465 /* rgb10a2 */
466 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
467 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
468 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
469 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
470 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
471
472 /* rgb10x2 */
473 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
474
475 /* bgr10a2 */
476 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
477 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
478 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
479 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
480 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
481
482 /* bgr10x2 */
483 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
484
485 /* r11g11b10 */
486 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
487
488 /* 32 bits per component */
489 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
490 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
491 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
492 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
493 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
494
495 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
496 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
497 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
498 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
499
500 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
501 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
502 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
503 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
504
505 {PIPE_FORMAT_R32_UINT, R32_UINT},
506 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
507 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
508 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
509
510 {PIPE_FORMAT_R32_SINT, R32_SINT},
511 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
512 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
513 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
514
515 /* 16 bits per component */
516 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
517 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
518 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
519 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
520 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
521
522 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
523 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
524 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
525 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
526
527 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
528 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
529 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
530 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
531
532 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
533 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
534 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
535 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
536
537 {PIPE_FORMAT_R16_UINT, R16_UINT},
538 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
539 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
540 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
541
542 {PIPE_FORMAT_R16_SINT, R16_SINT},
543 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
544 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
545 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
546
547 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
548 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
549 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
550 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
551 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
552
553 /* 8 bits per component */
554 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
555 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
556 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
557 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
558 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
559 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
560 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
561 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
562
563 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
564 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
565 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
566 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
567
568 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
569 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
570 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
571 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
572
573 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
574 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
575 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
576 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
577
578 {PIPE_FORMAT_R8_UINT, R8_UINT},
579 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
580 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
581 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
582
583 {PIPE_FORMAT_R8_SINT, R8_SINT},
584 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
585 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
586 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
587
588 /* These formats are valid for vertex data, but should not be used
589 * for render targets.
590 */
591
592 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
593 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
594 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
595 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
596
597 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
598 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
599 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
600 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
601
602 /* These formats have entries in SWR but don't have Load/StoreTile
603 * implementations. That means these aren't renderable, and thus having
604 * a mapping entry here is detrimental.
605 */
606 /*
607
608 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
609 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
610 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
611 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
612 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
613
614 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
615 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
616
617 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
618 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
619 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
620
621 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
622 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
623 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
624
625 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
626 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
627 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
628 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
629
630 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
631 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
632 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
633 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
634 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
635 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
636 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
637 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
638
639 {PIPE_FORMAT_I8_UINT, I8_UINT},
640 {PIPE_FORMAT_L8_UINT, L8_UINT},
641 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
642
643 {PIPE_FORMAT_I8_SINT, I8_SINT},
644 {PIPE_FORMAT_L8_SINT, L8_SINT},
645 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
646
647 */
648 };
649
650 auto it = mesa2swr.find(format);
651 if (it == mesa2swr.end())
652 return (SWR_FORMAT)-1;
653 else
654 return it->second;
655 }
656
657 static boolean
658 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
659 {
660 struct sw_winsys *winsys = screen->winsys;
661 struct sw_displaytarget *dt;
662
663 const unsigned width = align(res->swr.width, res->swr.halign);
664 const unsigned height = align(res->swr.height, res->swr.valign);
665
666 UINT stride;
667 dt = winsys->displaytarget_create(winsys,
668 res->base.bind,
669 res->base.format,
670 width, height,
671 64, NULL,
672 &stride);
673
674 if (dt == NULL)
675 return FALSE;
676
677 void *map = winsys->displaytarget_map(winsys, dt, 0);
678
679 res->display_target = dt;
680 res->swr.xpBaseAddress = (gfxptr_t)map;
681
682 /* Clear the display target surface */
683 if (map)
684 memset(map, 0, height * stride);
685
686 winsys->displaytarget_unmap(winsys, dt);
687
688 return TRUE;
689 }
690
691 static bool
692 swr_texture_layout(struct swr_screen *screen,
693 struct swr_resource *res,
694 boolean allocate)
695 {
696 struct pipe_resource *pt = &res->base;
697
698 pipe_format fmt = pt->format;
699 const struct util_format_description *desc = util_format_description(fmt);
700
701 res->has_depth = util_format_has_depth(desc);
702 res->has_stencil = util_format_has_stencil(desc);
703
704 if (res->has_stencil && !res->has_depth)
705 fmt = PIPE_FORMAT_R8_UINT;
706
707 /* We always use the SWR layout. For 2D and 3D textures this looks like:
708 *
709 * |<------- pitch ------->|
710 * +=======================+-------
711 * |Array 0 | ^
712 * | | |
713 * | Level 0 | |
714 * | | |
715 * | | qpitch
716 * +-----------+-----------+ |
717 * | | L2L2L2L2 | |
718 * | Level 1 | L3L3 | |
719 * | | L4 | v
720 * +===========+===========+-------
721 * |Array 1 |
722 * | |
723 * | Level 0 |
724 * | |
725 * | |
726 * +-----------+-----------+
727 * | | L2L2L2L2 |
728 * | Level 1 | L3L3 |
729 * | | L4 |
730 * +===========+===========+
731 *
732 * The overall width in bytes is known as the pitch, while the overall
733 * height in rows is the qpitch. Array slices are laid out logically below
734 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
735 * just invalid for the higher array numbers (since depth is also
736 * minified). 1D and 1D array surfaces are stored effectively the same way,
737 * except that pitch never plays into it. All the levels are logically
738 * adjacent to each other on the X axis. The qpitch becomes the number of
739 * elements between array slices, while the pitch is unused.
740 *
741 * Each level's sizes are subject to the valign and halign settings of the
742 * surface. For compressed formats that swr is unaware of, we will use an
743 * appropriately-sized uncompressed format, and scale the widths/heights.
744 *
745 * This surface is stored inside res->swr. For depth/stencil textures,
746 * res->secondary will have an identically-laid-out but R8_UINT-formatted
747 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
748 * texels, to simplify map/unmap logic which copies the stencil values
749 * in/out.
750 */
751
752 res->swr.width = pt->width0;
753 res->swr.height = pt->height0;
754 res->swr.type = swr_convert_target_type(pt->target);
755 res->swr.tileMode = SWR_TILE_NONE;
756 res->swr.format = mesa_to_swr_format(fmt);
757 res->swr.numSamples = std::max(1u, pt->nr_samples);
758
759 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
760 res->swr.halign = KNOB_MACROTILE_X_DIM;
761 res->swr.valign = KNOB_MACROTILE_Y_DIM;
762
763 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
764 * surface sample count. */
765 if (screen->msaa_force_enable) {
766 res->swr.numSamples = screen->msaa_max_count;
767 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
768 res->swr.numSamples);
769 }
770 } else {
771 res->swr.halign = 1;
772 res->swr.valign = 1;
773 }
774
775 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
776 unsigned width = align(pt->width0, halign);
777 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
778 for (int level = 1; level <= pt->last_level; level++)
779 width += align(u_minify(pt->width0, level), halign);
780 res->swr.pitch = util_format_get_blocksize(fmt);
781 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
782 } else {
783 // The pitch is the overall width of the texture in bytes. Most of the
784 // time this is the pitch of level 0 since all the other levels fit
785 // underneath it. However in some degenerate situations, the width of
786 // level1 + level2 may be larger. In that case, we use those
787 // widths. This can happen if, e.g. halign is 32, and the width of level
788 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
789 // be 32 each, adding up to 64.
790 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
791 if (pt->last_level > 1) {
792 width = std::max<uint32_t>(
793 width,
794 align(u_minify(pt->width0, 1), halign) +
795 align(u_minify(pt->width0, 2), halign));
796 }
797 res->swr.pitch = util_format_get_stride(fmt, width);
798
799 // The qpitch is controlled by either the height of the second LOD, or
800 // the combination of all the later LODs.
801 unsigned height = align(pt->height0, valign);
802 if (pt->last_level == 1) {
803 height += align(u_minify(pt->height0, 1), valign);
804 } else if (pt->last_level > 1) {
805 unsigned level1 = align(u_minify(pt->height0, 1), valign);
806 unsigned level2 = 0;
807 for (int level = 2; level <= pt->last_level; level++) {
808 level2 += align(u_minify(pt->height0, level), valign);
809 }
810 height += std::max(level1, level2);
811 }
812 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
813 }
814
815 if (pt->target == PIPE_TEXTURE_3D)
816 res->swr.depth = pt->depth0;
817 else
818 res->swr.depth = pt->array_size;
819
820 // Fix up swr format if necessary so that LOD offset computation works
821 if (res->swr.format == (SWR_FORMAT)-1) {
822 switch (util_format_get_blocksize(fmt)) {
823 default:
824 unreachable("Unexpected format block size");
825 case 1: res->swr.format = R8_UINT; break;
826 case 2: res->swr.format = R16_UINT; break;
827 case 4: res->swr.format = R32_UINT; break;
828 case 8:
829 if (util_format_is_compressed(fmt))
830 res->swr.format = BC4_UNORM;
831 else
832 res->swr.format = R32G32_UINT;
833 break;
834 case 16:
835 if (util_format_is_compressed(fmt))
836 res->swr.format = BC5_UNORM;
837 else
838 res->swr.format = R32G32B32A32_UINT;
839 break;
840 }
841 }
842
843 for (int level = 0; level <= pt->last_level; level++) {
844 res->mip_offsets[level] =
845 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
846 }
847
848 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
849 res->swr.pitch * res->swr.numSamples;
850
851 // Let non-sampled textures (e.g. buffer objects) bypass the size limit
852 if (swr_resource_is_texture(&res->base) && total_size > SWR_MAX_TEXTURE_SIZE)
853 return false;
854
855 if (allocate) {
856 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
857 if (!res->swr.xpBaseAddress)
858 return false;
859
860 if (res->has_depth && res->has_stencil) {
861 res->secondary = res->swr;
862 res->secondary.format = R8_UINT;
863 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
864
865 for (int level = 0; level <= pt->last_level; level++) {
866 res->secondary_mip_offsets[level] =
867 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
868 }
869
870 total_size = res->secondary.depth * res->secondary.qpitch *
871 res->secondary.pitch * res->secondary.numSamples;
872
873 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
874 if (!res->secondary.xpBaseAddress) {
875 AlignedFree((void *)res->swr.xpBaseAddress);
876 return false;
877 }
878 }
879 }
880
881 return true;
882 }
883
884 static boolean
885 swr_can_create_resource(struct pipe_screen *screen,
886 const struct pipe_resource *templat)
887 {
888 struct swr_resource res;
889 memset(&res, 0, sizeof(res));
890 res.base = *templat;
891 return swr_texture_layout(swr_screen(screen), &res, false);
892 }
893
894 /* Helper function that conditionally creates a single-sample resolve resource
895 * and attaches it to main multisample resource. */
896 static boolean
897 swr_create_resolve_resource(struct pipe_screen *_screen,
898 struct swr_resource *msaa_res)
899 {
900 struct swr_screen *screen = swr_screen(_screen);
901
902 /* If resource is multisample, create a single-sample resolve resource */
903 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
904 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
905
906 /* Create a single-sample copy of the resource. Copy the original
907 * resource parameters and set flag to prevent recursion when re-calling
908 * resource_create */
909 struct pipe_resource alt_template = msaa_res->base;
910 alt_template.nr_samples = 0;
911 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
912
913 /* Note: Display_target is a special single-sample resource, only the
914 * display_target has been created already. */
915 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
916 | PIPE_BIND_SHARED)) {
917 /* Allocate the multisample buffers. */
918 if (!swr_texture_layout(screen, msaa_res, true))
919 return false;
920
921 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
922 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
923 alt_template.bind = PIPE_BIND_RENDER_TARGET;
924 }
925
926 /* Allocate single-sample resolve surface */
927 struct pipe_resource *alt;
928 alt = _screen->resource_create(_screen, &alt_template);
929 if (!alt)
930 return false;
931
932 /* Attach it to the multisample resource */
933 msaa_res->resolve_target = alt;
934
935 /* Hang resolve surface state off the multisample surface state to so
936 * StoreTiles knows where to resolve the surface. */
937 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
938 }
939
940 return true; /* success */
941 }
942
943 static struct pipe_resource *
944 swr_resource_create(struct pipe_screen *_screen,
945 const struct pipe_resource *templat)
946 {
947 struct swr_screen *screen = swr_screen(_screen);
948 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
949 if (!res)
950 return NULL;
951
952 res->base = *templat;
953 pipe_reference_init(&res->base.reference, 1);
954 res->base.screen = &screen->base;
955
956 if (swr_resource_is_texture(&res->base)) {
957 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
958 | PIPE_BIND_SHARED)) {
959 /* displayable surface
960 * first call swr_texture_layout without allocating to finish
961 * filling out the SWR_SURFACE_STATE in res */
962 swr_texture_layout(screen, res, false);
963 if (!swr_displaytarget_layout(screen, res))
964 goto fail;
965 } else {
966 /* texture map */
967 if (!swr_texture_layout(screen, res, true))
968 goto fail;
969 }
970
971 /* If resource was multisample, create resolve resource and attach
972 * it to multisample resource. */
973 if (!swr_create_resolve_resource(_screen, res))
974 goto fail;
975
976 } else {
977 /* other data (vertex buffer, const buffer, etc) */
978 assert(util_format_get_blocksize(templat->format) == 1);
979 assert(templat->height0 == 1);
980 assert(templat->depth0 == 1);
981 assert(templat->last_level == 0);
982
983 /* Easiest to just call swr_texture_layout, as it sets up
984 * SWR_SURFACE_STATE in res */
985 if (!swr_texture_layout(screen, res, true))
986 goto fail;
987 }
988
989 return &res->base;
990
991 fail:
992 FREE(res);
993 return NULL;
994 }
995
996 static void
997 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
998 {
999 struct swr_screen *screen = swr_screen(p_screen);
1000 struct swr_resource *spr = swr_resource(pt);
1001
1002 if (spr->display_target) {
1003 /* If resource is display target, winsys manages the buffer and will
1004 * free it on displaytarget_destroy. */
1005 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1006
1007 struct sw_winsys *winsys = screen->winsys;
1008 winsys->displaytarget_destroy(winsys, spr->display_target);
1009
1010 if (spr->swr.numSamples > 1) {
1011 /* Free an attached resolve resource */
1012 struct swr_resource *alt = swr_resource(spr->resolve_target);
1013 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1014
1015 /* Free multisample buffer */
1016 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1017 }
1018 } else {
1019 /* For regular resources, defer deletion */
1020 swr_resource_unused(pt);
1021
1022 if (spr->swr.numSamples > 1) {
1023 /* Free an attached resolve resource */
1024 struct swr_resource *alt = swr_resource(spr->resolve_target);
1025 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1026 }
1027
1028 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1029 swr_fence_work_free(screen->flush_fence,
1030 (void*)(spr->secondary.xpBaseAddress), true);
1031
1032 /* If work queue grows too large, submit a fence to force queue to
1033 * drain. This is mainly to decrease the amount of memory used by the
1034 * piglit streaming-texture-leak test */
1035 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1036 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1037 }
1038
1039 FREE(spr);
1040 }
1041
1042
1043 static void
1044 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1045 struct pipe_resource *resource,
1046 unsigned level,
1047 unsigned layer,
1048 void *context_private,
1049 struct pipe_box *sub_box)
1050 {
1051 struct swr_screen *screen = swr_screen(p_screen);
1052 struct sw_winsys *winsys = screen->winsys;
1053 struct swr_resource *spr = swr_resource(resource);
1054 struct pipe_context *pipe = screen->pipe;
1055 struct swr_context *ctx = swr_context(pipe);
1056
1057 if (pipe) {
1058 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1059 swr_resource_unused(resource);
1060 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1061 }
1062
1063 /* Multisample resolved into resolve_target at flush with store_resource */
1064 if (pipe && spr->swr.numSamples > 1) {
1065 struct pipe_resource *resolve_target = spr->resolve_target;
1066
1067 /* Once resolved, copy into display target */
1068 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1069
1070 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1071 PIPE_TRANSFER_WRITE);
1072 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1073 winsys->displaytarget_unmap(winsys, spr->display_target);
1074 }
1075
1076 debug_assert(spr->display_target);
1077 if (spr->display_target)
1078 winsys->displaytarget_display(
1079 winsys, spr->display_target, context_private, sub_box);
1080 }
1081
1082
1083 void
1084 swr_destroy_screen_internal(struct swr_screen **screen)
1085 {
1086 struct pipe_screen *p_screen = &(*screen)->base;
1087
1088 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1089 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1090
1091 JitDestroyContext((*screen)->hJitMgr);
1092
1093 if ((*screen)->pLibrary)
1094 util_dl_close((*screen)->pLibrary);
1095
1096 FREE(*screen);
1097 *screen = NULL;
1098 }
1099
1100
1101 static void
1102 swr_destroy_screen(struct pipe_screen *p_screen)
1103 {
1104 struct swr_screen *screen = swr_screen(p_screen);
1105 struct sw_winsys *winsys = screen->winsys;
1106
1107 fprintf(stderr, "SWR destroy screen!\n");
1108
1109 if (winsys->destroy)
1110 winsys->destroy(winsys);
1111
1112 swr_destroy_screen_internal(&screen);
1113 }
1114
1115
1116 static void
1117 swr_validate_env_options(struct swr_screen *screen)
1118 {
1119 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1120 * copied to scratch space on a draw. Past this, the draw will access
1121 * user-buffer directly and then block. This is faster than queuing many
1122 * large client draws. */
1123 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1124 int client_copy_limit =
1125 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1126 if (client_copy_limit > 0)
1127 screen->client_copy_limit = client_copy_limit;
1128
1129 /* XXX msaa under development, disable by default for now */
1130 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1131
1132 /* validate env override values, within range and power of 2 */
1133 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1134 if (msaa_max_count != 1) {
1135 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1136 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1137 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1138 fprintf(stderr, "must be power of 2 between 1 and %d" \
1139 " (or 1 to disable msaa)\n",
1140 SWR_MAX_NUM_MULTISAMPLES);
1141 msaa_max_count = 1;
1142 }
1143
1144 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1145 if (msaa_max_count == 1)
1146 fprintf(stderr, "(msaa disabled)\n");
1147
1148 screen->msaa_max_count = msaa_max_count;
1149 }
1150
1151 screen->msaa_force_enable = debug_get_bool_option(
1152 "SWR_MSAA_FORCE_ENABLE", false);
1153 if (screen->msaa_force_enable)
1154 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1155 }
1156
1157
1158 struct pipe_screen *
1159 swr_create_screen_internal(struct sw_winsys *winsys)
1160 {
1161 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1162
1163 if (!screen)
1164 return NULL;
1165
1166 if (!lp_build_init()) {
1167 FREE(screen);
1168 return NULL;
1169 }
1170
1171 screen->winsys = winsys;
1172 screen->base.get_name = swr_get_name;
1173 screen->base.get_vendor = swr_get_vendor;
1174 screen->base.is_format_supported = swr_is_format_supported;
1175 screen->base.context_create = swr_create_context;
1176 screen->base.can_create_resource = swr_can_create_resource;
1177
1178 screen->base.destroy = swr_destroy_screen;
1179 screen->base.get_param = swr_get_param;
1180 screen->base.get_shader_param = swr_get_shader_param;
1181 screen->base.get_paramf = swr_get_paramf;
1182
1183 screen->base.resource_create = swr_resource_create;
1184 screen->base.resource_destroy = swr_resource_destroy;
1185
1186 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1187
1188 // Pass in "" for architecture for run-time determination
1189 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1190
1191 swr_fence_init(&screen->base);
1192
1193 swr_validate_env_options(screen);
1194
1195 return &screen->base;
1196 }
1197