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gallium: add PIPE_CAP_TGSI_TEX_TXF_LZ
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /* MSVC case instensitive compare */
50 #if defined(PIPE_CC_MSVC)
51 #define strcasecmp lstrcmpiA
52 #endif
53
54 /*
55 * Max texture sizes
56 * XXX Check max texture size values against core and sampler.
57 */
58 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
59 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
60 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
61 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
62 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
63
64 static const char *
65 swr_get_name(struct pipe_screen *screen)
66 {
67 static char buf[100];
68 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
69 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
70 lp_native_vector_width );
71 return buf;
72 }
73
74 static const char *
75 swr_get_vendor(struct pipe_screen *screen)
76 {
77 return "Intel Corporation";
78 }
79
80 static boolean
81 swr_is_format_supported(struct pipe_screen *screen,
82 enum pipe_format format,
83 enum pipe_texture_target target,
84 unsigned sample_count,
85 unsigned bind)
86 {
87 struct sw_winsys *winsys = swr_screen(screen)->winsys;
88 const struct util_format_description *format_desc;
89
90 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
91 || target == PIPE_TEXTURE_1D_ARRAY
92 || target == PIPE_TEXTURE_2D
93 || target == PIPE_TEXTURE_2D_ARRAY
94 || target == PIPE_TEXTURE_RECT
95 || target == PIPE_TEXTURE_3D
96 || target == PIPE_TEXTURE_CUBE
97 || target == PIPE_TEXTURE_CUBE_ARRAY);
98
99 format_desc = util_format_description(format);
100 if (!format_desc)
101 return FALSE;
102
103 if (sample_count > 1)
104 return FALSE;
105
106 if (bind
107 & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) {
108 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
109 return FALSE;
110 }
111
112 if (bind & PIPE_BIND_RENDER_TARGET) {
113 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
114 return FALSE;
115
116 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
117 return FALSE;
118
119 /*
120 * Although possible, it is unnatural to render into compressed or YUV
121 * surfaces. So disable these here to avoid going into weird paths
122 * inside the state trackers.
123 */
124 if (format_desc->block.width != 1 || format_desc->block.height != 1)
125 return FALSE;
126 }
127
128 if (bind & PIPE_BIND_DEPTH_STENCIL) {
129 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
130 return FALSE;
131
132 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
133 return FALSE;
134 }
135
136 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
137 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
138 return FALSE;
139 }
140
141 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
142 format != PIPE_FORMAT_ETC1_RGB8) {
143 return FALSE;
144 }
145
146 if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
147 return util_format_s3tc_enabled;
148 }
149
150 return TRUE;
151 }
152
153 static int
154 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
155 {
156 switch (param) {
157 /* limits */
158 case PIPE_CAP_MAX_RENDER_TARGETS:
159 return PIPE_MAX_COLOR_BUFS;
160 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
161 return SWR_MAX_TEXTURE_2D_LEVELS;
162 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
163 return SWR_MAX_TEXTURE_3D_LEVELS;
164 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
165 return SWR_MAX_TEXTURE_CUBE_LEVELS;
166 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
167 return MAX_SO_STREAMS;
168 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
169 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
170 return MAX_ATTRIBUTES * 4;
171 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
172 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
173 return 1024;
174 case PIPE_CAP_MAX_VERTEX_STREAMS:
175 return 1;
176 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
177 return 2048;
178 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
179 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
180 case PIPE_CAP_MIN_TEXEL_OFFSET:
181 return -8;
182 case PIPE_CAP_MAX_TEXEL_OFFSET:
183 return 7;
184 case PIPE_CAP_GLSL_FEATURE_LEVEL:
185 return 330;
186 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
187 return 16;
188 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
189 return 64;
190 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
191 return 65536;
192 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
193 return 0;
194 case PIPE_CAP_MAX_VIEWPORTS:
195 return 1;
196 case PIPE_CAP_ENDIANNESS:
197 return PIPE_ENDIAN_NATIVE;
198 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
199 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
200 return 0;
201
202 /* supported features */
203 case PIPE_CAP_NPOT_TEXTURES:
204 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
205 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
206 case PIPE_CAP_TWO_SIDED_STENCIL:
207 case PIPE_CAP_SM3:
208 case PIPE_CAP_POINT_SPRITE:
209 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
210 case PIPE_CAP_OCCLUSION_QUERY:
211 case PIPE_CAP_QUERY_TIME_ELAPSED:
212 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
213 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
214 case PIPE_CAP_TEXTURE_SHADOW_MAP:
215 case PIPE_CAP_TEXTURE_SWIZZLE:
216 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
217 case PIPE_CAP_INDEP_BLEND_ENABLE:
218 case PIPE_CAP_INDEP_BLEND_FUNC:
219 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
220 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
221 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
222 case PIPE_CAP_DEPTH_CLIP_DISABLE:
223 case PIPE_CAP_PRIMITIVE_RESTART:
224 case PIPE_CAP_TGSI_INSTANCEID:
225 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
226 case PIPE_CAP_START_INSTANCE:
227 case PIPE_CAP_SEAMLESS_CUBE_MAP:
228 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
229 case PIPE_CAP_CONDITIONAL_RENDER:
230 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
231 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
232 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
233 case PIPE_CAP_USER_VERTEX_BUFFERS:
234 case PIPE_CAP_USER_CONSTANT_BUFFERS:
235 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
236 case PIPE_CAP_QUERY_TIMESTAMP:
237 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
238 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
239 case PIPE_CAP_FAKE_SW_MSAA:
240 case PIPE_CAP_DRAW_INDIRECT:
241 case PIPE_CAP_UMA:
242 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
243 case PIPE_CAP_CLIP_HALFZ:
244 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
245 case PIPE_CAP_DEPTH_BOUNDS_TEST:
246 case PIPE_CAP_CLEAR_TEXTURE:
247 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
248 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
249 case PIPE_CAP_CULL_DISTANCE:
250 case PIPE_CAP_CUBE_MAP_ARRAY:
251 return 1;
252
253 /* unsupported features */
254 case PIPE_CAP_ANISOTROPIC_FILTER:
255 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
256 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
257 case PIPE_CAP_SHADER_STENCIL_EXPORT:
258 case PIPE_CAP_TEXTURE_BARRIER:
259 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
260 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
261 case PIPE_CAP_COMPUTE:
262 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
263 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
264 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
265 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
266 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
267 case PIPE_CAP_TEXTURE_MULTISAMPLE:
268 case PIPE_CAP_TGSI_TEXCOORD:
269 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
270 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
271 case PIPE_CAP_TEXTURE_GATHER_SM5:
272 case PIPE_CAP_TEXTURE_QUERY_LOD:
273 case PIPE_CAP_SAMPLE_SHADING:
274 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
275 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
276 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
277 case PIPE_CAP_SAMPLER_VIEW_TARGET:
278 case PIPE_CAP_VERTEXID_NOBASE:
279 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
280 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
281 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
282 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
283 case PIPE_CAP_TGSI_TXQS:
284 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
285 case PIPE_CAP_SHAREABLE_SHADERS:
286 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
287 case PIPE_CAP_DRAW_PARAMETERS:
288 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
289 case PIPE_CAP_MULTI_DRAW_INDIRECT:
290 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
291 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
292 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
293 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
294 case PIPE_CAP_INVALIDATE_BUFFER:
295 case PIPE_CAP_GENERATE_MIPMAP:
296 case PIPE_CAP_STRING_MARKER:
297 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
298 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
299 case PIPE_CAP_QUERY_BUFFER_OBJECT:
300 case PIPE_CAP_QUERY_MEMORY_INFO:
301 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
302 case PIPE_CAP_PCI_GROUP:
303 case PIPE_CAP_PCI_BUS:
304 case PIPE_CAP_PCI_DEVICE:
305 case PIPE_CAP_PCI_FUNCTION:
306 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
307 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
308 case PIPE_CAP_TGSI_VOTE:
309 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
310 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
311 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
312 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
313 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
314 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
315 case PIPE_CAP_NATIVE_FENCE_FD:
316 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
317 case PIPE_CAP_TGSI_FS_FBFETCH:
318 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
319 case PIPE_CAP_INT64:
320 case PIPE_CAP_INT64_DIVMOD:
321 case PIPE_CAP_TGSI_TEX_TXF_LZ:
322 return 0;
323
324 case PIPE_CAP_VENDOR_ID:
325 return 0xFFFFFFFF;
326 case PIPE_CAP_DEVICE_ID:
327 return 0xFFFFFFFF;
328 case PIPE_CAP_ACCELERATED:
329 return 0;
330 case PIPE_CAP_VIDEO_MEMORY: {
331 /* XXX: Do we want to return the full amount of system memory ? */
332 uint64_t system_memory;
333
334 if (!os_get_total_physical_memory(&system_memory))
335 return 0;
336
337 return (int)(system_memory >> 20);
338 }
339 }
340
341 /* should only get here on unhandled cases */
342 debug_printf("Unexpected PIPE_CAP %d query\n", param);
343 return 0;
344 }
345
346 static int
347 swr_get_shader_param(struct pipe_screen *screen,
348 enum pipe_shader_type shader,
349 enum pipe_shader_cap param)
350 {
351 if (shader == PIPE_SHADER_VERTEX ||
352 shader == PIPE_SHADER_FRAGMENT ||
353 shader == PIPE_SHADER_GEOMETRY)
354 return gallivm_get_shader_param(param);
355
356 // Todo: tesselation, compute
357 return 0;
358 }
359
360
361 static float
362 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
363 {
364 switch (param) {
365 case PIPE_CAPF_MAX_LINE_WIDTH:
366 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
367 case PIPE_CAPF_MAX_POINT_WIDTH:
368 return 255.0; /* arbitrary */
369 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
370 return 0.0;
371 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
372 return 0.0;
373 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
374 return 16.0; /* arbitrary */
375 case PIPE_CAPF_GUARD_BAND_LEFT:
376 case PIPE_CAPF_GUARD_BAND_TOP:
377 case PIPE_CAPF_GUARD_BAND_RIGHT:
378 case PIPE_CAPF_GUARD_BAND_BOTTOM:
379 return 0.0;
380 }
381 /* should only get here on unhandled cases */
382 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
383 return 0.0;
384 }
385
386 SWR_FORMAT
387 mesa_to_swr_format(enum pipe_format format)
388 {
389 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
390 /* depth / stencil */
391 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
392 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
393 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
394 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
395 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
396
397 /* alpha */
398 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
399 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
400 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
401 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
402
403 /* odd sizes, bgr */
404 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
405 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
406 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
407 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
408 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
409 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
410 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
411 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
412 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
413
414 /* rgb10a2 */
415 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
416 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
417 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
418 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
419 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
420
421 /* rgb10x2 */
422 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
423
424 /* bgr10a2 */
425 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
426 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
427 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
428 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
429 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
430
431 /* bgr10x2 */
432 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
433
434 /* r11g11b10 */
435 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
436
437 /* 32 bits per component */
438 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
439 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
440 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
441 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
442 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
443
444 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
445 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
446 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
447 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
448
449 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
450 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
451 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
452 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
453
454 {PIPE_FORMAT_R32_UINT, R32_UINT},
455 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
456 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
457 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
458
459 {PIPE_FORMAT_R32_SINT, R32_SINT},
460 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
461 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
462 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
463
464 /* 16 bits per component */
465 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
466 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
467 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
468 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
469 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
470
471 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
472 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
473 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
474 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
475
476 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
477 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
478 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
479 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
480
481 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
482 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
483 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
484 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
485
486 {PIPE_FORMAT_R16_UINT, R16_UINT},
487 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
488 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
489 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
490
491 {PIPE_FORMAT_R16_SINT, R16_SINT},
492 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
493 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
494 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
495
496 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
497 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
498 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
499 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
500 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
501
502 /* 8 bits per component */
503 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
504 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
505 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
506 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
507 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
508 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
509 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
510 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
511
512 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
513 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
514 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
515 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
516
517 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
518 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
519 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
520 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
521
522 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
523 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
524 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
525 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
526
527 {PIPE_FORMAT_R8_UINT, R8_UINT},
528 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
529 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
530 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
531
532 {PIPE_FORMAT_R8_SINT, R8_SINT},
533 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
534 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
535 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
536
537 /* These formats are valid for vertex data, but should not be used
538 * for render targets.
539 */
540
541 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
542 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
543 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
544 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
545
546 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
547 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
548 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
549 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
550
551 /* These formats have entries in SWR but don't have Load/StoreTile
552 * implementations. That means these aren't renderable, and thus having
553 * a mapping entry here is detrimental.
554 */
555 /*
556
557 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
558 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
559 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
560 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
561 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
562
563 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
564 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
565
566 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
567 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
568 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
569
570 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
571 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
572 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
573
574 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
575 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
576 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
577 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
578
579 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
580 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
581 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
582 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
583 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
584 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
585 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
586 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
587
588 {PIPE_FORMAT_I8_UINT, I8_UINT},
589 {PIPE_FORMAT_L8_UINT, L8_UINT},
590 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
591
592 {PIPE_FORMAT_I8_SINT, I8_SINT},
593 {PIPE_FORMAT_L8_SINT, L8_SINT},
594 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
595
596 */
597 };
598
599 auto it = mesa2swr.find(format);
600 if (it == mesa2swr.end())
601 return (SWR_FORMAT)-1;
602 else
603 return it->second;
604 }
605
606 static boolean
607 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
608 {
609 struct sw_winsys *winsys = screen->winsys;
610 struct sw_displaytarget *dt;
611
612 const unsigned width = align(res->swr.width, res->swr.halign);
613 const unsigned height = align(res->swr.height, res->swr.valign);
614
615 UINT stride;
616 dt = winsys->displaytarget_create(winsys,
617 res->base.bind,
618 res->base.format,
619 width, height,
620 64, NULL,
621 &stride);
622
623 if (dt == NULL)
624 return FALSE;
625
626 void *map = winsys->displaytarget_map(winsys, dt, 0);
627
628 res->display_target = dt;
629 res->swr.pBaseAddress = (uint8_t*) map;
630
631 /* Clear the display target surface */
632 if (map)
633 memset(map, 0, height * stride);
634
635 winsys->displaytarget_unmap(winsys, dt);
636
637 return TRUE;
638 }
639
640 static bool
641 swr_texture_layout(struct swr_screen *screen,
642 struct swr_resource *res,
643 boolean allocate)
644 {
645 struct pipe_resource *pt = &res->base;
646
647 pipe_format fmt = pt->format;
648 const struct util_format_description *desc = util_format_description(fmt);
649
650 res->has_depth = util_format_has_depth(desc);
651 res->has_stencil = util_format_has_stencil(desc);
652
653 if (res->has_stencil && !res->has_depth)
654 fmt = PIPE_FORMAT_R8_UINT;
655
656 /* We always use the SWR layout. For 2D and 3D textures this looks like:
657 *
658 * |<------- pitch ------->|
659 * +=======================+-------
660 * |Array 0 | ^
661 * | | |
662 * | Level 0 | |
663 * | | |
664 * | | qpitch
665 * +-----------+-----------+ |
666 * | | L2L2L2L2 | |
667 * | Level 1 | L3L3 | |
668 * | | L4 | v
669 * +===========+===========+-------
670 * |Array 1 |
671 * | |
672 * | Level 0 |
673 * | |
674 * | |
675 * +-----------+-----------+
676 * | | L2L2L2L2 |
677 * | Level 1 | L3L3 |
678 * | | L4 |
679 * +===========+===========+
680 *
681 * The overall width in bytes is known as the pitch, while the overall
682 * height in rows is the qpitch. Array slices are laid out logically below
683 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
684 * just invalid for the higher array numbers (since depth is also
685 * minified). 1D and 1D array surfaces are stored effectively the same way,
686 * except that pitch never plays into it. All the levels are logically
687 * adjacent to each other on the X axis. The qpitch becomes the number of
688 * elements between array slices, while the pitch is unused.
689 *
690 * Each level's sizes are subject to the valign and halign settings of the
691 * surface. For compressed formats that swr is unaware of, we will use an
692 * appropriately-sized uncompressed format, and scale the widths/heights.
693 *
694 * This surface is stored inside res->swr. For depth/stencil textures,
695 * res->secondary will have an identically-laid-out but R8_UINT-formatted
696 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
697 * texels, to simplify map/unmap logic which copies the stencil values
698 * in/out.
699 */
700
701 res->swr.width = pt->width0;
702 res->swr.height = pt->height0;
703 res->swr.type = swr_convert_target_type(pt->target);
704 res->swr.tileMode = SWR_TILE_NONE;
705 res->swr.format = mesa_to_swr_format(fmt);
706 res->swr.numSamples = std::max(1u, pt->nr_samples);
707
708 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
709 res->swr.halign = KNOB_MACROTILE_X_DIM;
710 res->swr.valign = KNOB_MACROTILE_Y_DIM;
711 } else {
712 res->swr.halign = 1;
713 res->swr.valign = 1;
714 }
715
716 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
717 unsigned width = align(pt->width0, halign);
718 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
719 for (int level = 1; level <= pt->last_level; level++)
720 width += align(u_minify(pt->width0, level), halign);
721 res->swr.pitch = util_format_get_blocksize(fmt);
722 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
723 } else {
724 // The pitch is the overall width of the texture in bytes. Most of the
725 // time this is the pitch of level 0 since all the other levels fit
726 // underneath it. However in some degenerate situations, the width of
727 // level1 + level2 may be larger. In that case, we use those
728 // widths. This can happen if, e.g. halign is 32, and the width of level
729 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
730 // be 32 each, adding up to 64.
731 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
732 if (pt->last_level > 1) {
733 width = std::max<uint32_t>(
734 width,
735 align(u_minify(pt->width0, 1), halign) +
736 align(u_minify(pt->width0, 2), halign));
737 }
738 res->swr.pitch = util_format_get_stride(fmt, width);
739
740 // The qpitch is controlled by either the height of the second LOD, or
741 // the combination of all the later LODs.
742 unsigned height = align(pt->height0, valign);
743 if (pt->last_level == 1) {
744 height += align(u_minify(pt->height0, 1), valign);
745 } else if (pt->last_level > 1) {
746 unsigned level1 = align(u_minify(pt->height0, 1), valign);
747 unsigned level2 = 0;
748 for (int level = 2; level <= pt->last_level; level++) {
749 level2 += align(u_minify(pt->height0, level), valign);
750 }
751 height += std::max(level1, level2);
752 }
753 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
754 }
755
756 if (pt->target == PIPE_TEXTURE_3D)
757 res->swr.depth = pt->depth0;
758 else
759 res->swr.depth = pt->array_size;
760
761 // Fix up swr format if necessary so that LOD offset computation works
762 if (res->swr.format == (SWR_FORMAT)-1) {
763 switch (util_format_get_blocksize(fmt)) {
764 default:
765 unreachable("Unexpected format block size");
766 case 1: res->swr.format = R8_UINT; break;
767 case 2: res->swr.format = R16_UINT; break;
768 case 4: res->swr.format = R32_UINT; break;
769 case 8:
770 if (util_format_is_compressed(fmt))
771 res->swr.format = BC4_UNORM;
772 else
773 res->swr.format = R32G32_UINT;
774 break;
775 case 16:
776 if (util_format_is_compressed(fmt))
777 res->swr.format = BC5_UNORM;
778 else
779 res->swr.format = R32G32B32A32_UINT;
780 break;
781 }
782 }
783
784 for (int level = 0; level <= pt->last_level; level++) {
785 res->mip_offsets[level] =
786 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
787 }
788
789 size_t total_size =
790 (size_t)res->swr.depth * res->swr.qpitch * res->swr.pitch;
791 if (total_size > SWR_MAX_TEXTURE_SIZE)
792 return false;
793
794 if (allocate) {
795 res->swr.pBaseAddress = (uint8_t *)AlignedMalloc(total_size, 64);
796
797 if (res->has_depth && res->has_stencil) {
798 res->secondary = res->swr;
799 res->secondary.format = R8_UINT;
800 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
801
802 for (int level = 0; level <= pt->last_level; level++) {
803 res->secondary_mip_offsets[level] =
804 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
805 }
806
807 res->secondary.pBaseAddress = (uint8_t *)AlignedMalloc(
808 res->secondary.depth * res->secondary.qpitch *
809 res->secondary.pitch, 64);
810 }
811 }
812
813 return true;
814 }
815
816 static boolean
817 swr_can_create_resource(struct pipe_screen *screen,
818 const struct pipe_resource *templat)
819 {
820 struct swr_resource res;
821 memset(&res, 0, sizeof(res));
822 res.base = *templat;
823 return swr_texture_layout(swr_screen(screen), &res, false);
824 }
825
826 static struct pipe_resource *
827 swr_resource_create(struct pipe_screen *_screen,
828 const struct pipe_resource *templat)
829 {
830 struct swr_screen *screen = swr_screen(_screen);
831 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
832 if (!res)
833 return NULL;
834
835 res->base = *templat;
836 pipe_reference_init(&res->base.reference, 1);
837 res->base.screen = &screen->base;
838
839 if (swr_resource_is_texture(&res->base)) {
840 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
841 | PIPE_BIND_SHARED)) {
842 /* displayable surface
843 * first call swr_texture_layout without allocating to finish
844 * filling out the SWR_SURFAE_STATE in res */
845 swr_texture_layout(screen, res, false);
846 if (!swr_displaytarget_layout(screen, res))
847 goto fail;
848 } else {
849 /* texture map */
850 if (!swr_texture_layout(screen, res, true))
851 goto fail;
852 }
853 } else {
854 /* other data (vertex buffer, const buffer, etc) */
855 assert(util_format_get_blocksize(templat->format) == 1);
856 assert(templat->height0 == 1);
857 assert(templat->depth0 == 1);
858 assert(templat->last_level == 0);
859
860 /* Easiest to just call swr_texture_layout, as it sets up
861 * SWR_SURFAE_STATE in res */
862 if (!swr_texture_layout(screen, res, true))
863 goto fail;
864 }
865
866 return &res->base;
867
868 fail:
869 FREE(res);
870 return NULL;
871 }
872
873 static void
874 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
875 {
876 struct swr_screen *screen = swr_screen(p_screen);
877 struct swr_resource *spr = swr_resource(pt);
878 struct pipe_context *pipe = screen->pipe;
879
880 if (spr->display_target) {
881 /* If resource is display target, winsys manages the buffer and will
882 * free it on displaytarget_destroy. */
883 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
884
885 struct sw_winsys *winsys = screen->winsys;
886 winsys->displaytarget_destroy(winsys, spr->display_target);
887
888 } else {
889 /* For regular resources, defer deletion */
890 swr_resource_unused(pt);
891 swr_fence_work_free(screen->flush_fence, spr->swr.pBaseAddress, true);
892 swr_fence_work_free(screen->flush_fence,
893 spr->secondary.pBaseAddress, true);
894 }
895
896 FREE(spr);
897 }
898
899
900 static void
901 swr_flush_frontbuffer(struct pipe_screen *p_screen,
902 struct pipe_resource *resource,
903 unsigned level,
904 unsigned layer,
905 void *context_private,
906 struct pipe_box *sub_box)
907 {
908 struct swr_screen *screen = swr_screen(p_screen);
909 struct sw_winsys *winsys = screen->winsys;
910 struct swr_resource *spr = swr_resource(resource);
911 struct pipe_context *pipe = screen->pipe;
912
913 if (pipe) {
914 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
915 swr_resource_unused(resource);
916 SwrEndFrame(swr_context(pipe)->swrContext);
917 }
918
919 debug_assert(spr->display_target);
920 if (spr->display_target)
921 winsys->displaytarget_display(
922 winsys, spr->display_target, context_private, sub_box);
923 }
924
925
926 static void
927 swr_destroy_screen(struct pipe_screen *p_screen)
928 {
929 struct swr_screen *screen = swr_screen(p_screen);
930 struct sw_winsys *winsys = screen->winsys;
931
932 fprintf(stderr, "SWR destroy screen!\n");
933
934 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
935 swr_fence_reference(p_screen, &screen->flush_fence, NULL);
936
937 JitDestroyContext(screen->hJitMgr);
938
939 if (winsys->destroy)
940 winsys->destroy(winsys);
941
942 FREE(screen);
943 }
944
945 PUBLIC
946 struct pipe_screen *
947 swr_create_screen_internal(struct sw_winsys *winsys)
948 {
949 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
950
951 if (!screen)
952 return NULL;
953
954 if (!getenv("KNOB_MAX_PRIMS_PER_DRAW")) {
955 g_GlobalKnobs.MAX_PRIMS_PER_DRAW.Value(49152);
956 }
957
958 if (!lp_build_init()) {
959 FREE(screen);
960 return NULL;
961 }
962
963 screen->winsys = winsys;
964 screen->base.get_name = swr_get_name;
965 screen->base.get_vendor = swr_get_vendor;
966 screen->base.is_format_supported = swr_is_format_supported;
967 screen->base.context_create = swr_create_context;
968 screen->base.can_create_resource = swr_can_create_resource;
969
970 screen->base.destroy = swr_destroy_screen;
971 screen->base.get_param = swr_get_param;
972 screen->base.get_shader_param = swr_get_shader_param;
973 screen->base.get_paramf = swr_get_paramf;
974
975 screen->base.resource_create = swr_resource_create;
976 screen->base.resource_destroy = swr_resource_destroy;
977
978 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
979
980 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, KNOB_ARCH_STR, "swr");
981
982 swr_fence_init(&screen->base);
983
984 util_format_s3tc_init();
985
986 return &screen->base;
987 }
988