projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
gallium: add PIPE_CAP_MAX_SHADER_BUFFER_SIZE
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (2 * 1024 * 1024 * 1024ULL) /* 2GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned storage_sample_count,
89 unsigned bind)
90 {
91 struct swr_screen *screen = swr_screen(_screen);
92 struct sw_winsys *winsys = screen->winsys;
93 const struct util_format_description *format_desc;
94
95 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
96 || target == PIPE_TEXTURE_1D_ARRAY
97 || target == PIPE_TEXTURE_2D
98 || target == PIPE_TEXTURE_2D_ARRAY
99 || target == PIPE_TEXTURE_RECT
100 || target == PIPE_TEXTURE_3D
101 || target == PIPE_TEXTURE_CUBE
102 || target == PIPE_TEXTURE_CUBE_ARRAY);
103
104 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
105 return false;
106
107 format_desc = util_format_description(format);
108 if (!format_desc)
109 return FALSE;
110
111 if ((sample_count > screen->msaa_max_count)
112 || !util_is_power_of_two_or_zero(sample_count))
113 return FALSE;
114
115 if (bind & PIPE_BIND_DISPLAY_TARGET) {
116 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
117 return FALSE;
118 }
119
120 if (bind & PIPE_BIND_RENDER_TARGET) {
121 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
122 return FALSE;
123
124 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
125 return FALSE;
126
127 /*
128 * Although possible, it is unnatural to render into compressed or YUV
129 * surfaces. So disable these here to avoid going into weird paths
130 * inside the state trackers.
131 */
132 if (format_desc->block.width != 1 || format_desc->block.height != 1)
133 return FALSE;
134 }
135
136 if (bind & PIPE_BIND_DEPTH_STENCIL) {
137 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
138 return FALSE;
139
140 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
141 return FALSE;
142 }
143
144 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
145 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
146 return FALSE;
147 }
148
149 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
150 format != PIPE_FORMAT_ETC1_RGB8) {
151 return FALSE;
152 }
153
154 return TRUE;
155 }
156
157 static int
158 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
159 {
160 switch (param) {
161 /* limits */
162 case PIPE_CAP_MAX_RENDER_TARGETS:
163 return PIPE_MAX_COLOR_BUFS;
164 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
165 return SWR_MAX_TEXTURE_2D_LEVELS;
166 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
167 return SWR_MAX_TEXTURE_3D_LEVELS;
168 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
169 return SWR_MAX_TEXTURE_CUBE_LEVELS;
170 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
171 return MAX_SO_STREAMS;
172 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
173 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
174 return MAX_ATTRIBUTES * 4;
175 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
176 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
177 return 1024;
178 case PIPE_CAP_MAX_VERTEX_STREAMS:
179 return 1;
180 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
181 return 2048;
182 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
183 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
184 case PIPE_CAP_MIN_TEXEL_OFFSET:
185 return -8;
186 case PIPE_CAP_MAX_TEXEL_OFFSET:
187 return 7;
188 case PIPE_CAP_GLSL_FEATURE_LEVEL:
189 return 330;
190 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
191 return 140;
192 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
193 return 16;
194 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
195 return 64;
196 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
197 return 65536;
198 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
199 return 0;
200 case PIPE_CAP_MAX_VIEWPORTS:
201 return 1;
202 case PIPE_CAP_ENDIANNESS:
203 return PIPE_ENDIAN_NATIVE;
204 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
205 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
206 return 0;
207
208 /* supported features */
209 case PIPE_CAP_NPOT_TEXTURES:
210 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
211 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
212 case PIPE_CAP_SM3:
213 case PIPE_CAP_POINT_SPRITE:
214 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
215 case PIPE_CAP_OCCLUSION_QUERY:
216 case PIPE_CAP_QUERY_TIME_ELAPSED:
217 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
218 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
219 case PIPE_CAP_TEXTURE_SWIZZLE:
220 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
221 case PIPE_CAP_INDEP_BLEND_ENABLE:
222 case PIPE_CAP_INDEP_BLEND_FUNC:
223 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
224 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
225 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
226 case PIPE_CAP_DEPTH_CLIP_DISABLE:
227 case PIPE_CAP_PRIMITIVE_RESTART:
228 case PIPE_CAP_TGSI_INSTANCEID:
229 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
230 case PIPE_CAP_START_INSTANCE:
231 case PIPE_CAP_SEAMLESS_CUBE_MAP:
232 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
233 case PIPE_CAP_CONDITIONAL_RENDER:
234 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
235 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
236 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
237 case PIPE_CAP_USER_VERTEX_BUFFERS:
238 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
239 case PIPE_CAP_QUERY_TIMESTAMP:
240 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
241 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
242 case PIPE_CAP_DRAW_INDIRECT:
243 case PIPE_CAP_UMA:
244 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
245 case PIPE_CAP_CLIP_HALFZ:
246 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
247 case PIPE_CAP_DEPTH_BOUNDS_TEST:
248 case PIPE_CAP_CLEAR_TEXTURE:
249 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
250 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
251 case PIPE_CAP_CULL_DISTANCE:
252 case PIPE_CAP_CUBE_MAP_ARRAY:
253 case PIPE_CAP_DOUBLES:
254 return 1;
255
256 /* MSAA support
257 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
258 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
259 case PIPE_CAP_TEXTURE_MULTISAMPLE:
260 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
261 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
262 case PIPE_CAP_FAKE_SW_MSAA:
263 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
264
265 /* fetch jit change for 2-4GB buffers requires alignment */
266 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
267 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
268 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
269 return 1;
270
271 /* unsupported features */
272 case PIPE_CAP_ANISOTROPIC_FILTER:
273 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
274 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
275 case PIPE_CAP_SHADER_STENCIL_EXPORT:
276 case PIPE_CAP_TEXTURE_BARRIER:
277 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
278 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
279 case PIPE_CAP_COMPUTE:
280 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
281 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
282 case PIPE_CAP_TGSI_TEXCOORD:
283 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
284 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
285 case PIPE_CAP_TEXTURE_GATHER_SM5:
286 case PIPE_CAP_TEXTURE_QUERY_LOD:
287 case PIPE_CAP_SAMPLE_SHADING:
288 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
289 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
290 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
291 case PIPE_CAP_SAMPLER_VIEW_TARGET:
292 case PIPE_CAP_VERTEXID_NOBASE:
293 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
294 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
295 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
296 case PIPE_CAP_TGSI_TXQS:
297 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
298 case PIPE_CAP_SHAREABLE_SHADERS:
299 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
300 case PIPE_CAP_DRAW_PARAMETERS:
301 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
302 case PIPE_CAP_MULTI_DRAW_INDIRECT:
303 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
304 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
305 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
306 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
307 case PIPE_CAP_INVALIDATE_BUFFER:
308 case PIPE_CAP_GENERATE_MIPMAP:
309 case PIPE_CAP_STRING_MARKER:
310 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
311 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
312 case PIPE_CAP_QUERY_BUFFER_OBJECT:
313 case PIPE_CAP_QUERY_MEMORY_INFO:
314 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
315 case PIPE_CAP_PCI_GROUP:
316 case PIPE_CAP_PCI_BUS:
317 case PIPE_CAP_PCI_DEVICE:
318 case PIPE_CAP_PCI_FUNCTION:
319 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
320 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
321 case PIPE_CAP_TGSI_VOTE:
322 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
323 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
324 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
325 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
326 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
327 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
328 case PIPE_CAP_NATIVE_FENCE_FD:
329 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
330 case PIPE_CAP_TGSI_FS_FBFETCH:
331 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
332 case PIPE_CAP_INT64:
333 case PIPE_CAP_INT64_DIVMOD:
334 case PIPE_CAP_TGSI_TEX_TXF_LZ:
335 case PIPE_CAP_TGSI_CLOCK:
336 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
337 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
338 case PIPE_CAP_TGSI_BALLOT:
339 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
340 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
341 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
342 case PIPE_CAP_POST_DEPTH_COVERAGE:
343 case PIPE_CAP_BINDLESS_TEXTURE:
344 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
345 case PIPE_CAP_QUERY_SO_OVERFLOW:
346 case PIPE_CAP_MEMOBJ:
347 case PIPE_CAP_LOAD_CONSTBUF:
348 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
349 case PIPE_CAP_TILE_RASTER_ORDER:
350 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
351 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
352 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
353 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
354 case PIPE_CAP_FENCE_SIGNAL:
355 case PIPE_CAP_CONSTBUF0_FLAGS:
356 case PIPE_CAP_PACKED_UNIFORMS:
357 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
358 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
359 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
360 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
361 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
362 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
363 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
364 return 0;
365 case PIPE_CAP_MAX_GS_INVOCATIONS:
366 return 32;
367 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
368 return 1 << 27;
369
370 case PIPE_CAP_VENDOR_ID:
371 return 0xFFFFFFFF;
372 case PIPE_CAP_DEVICE_ID:
373 return 0xFFFFFFFF;
374 case PIPE_CAP_ACCELERATED:
375 return 0;
376 case PIPE_CAP_VIDEO_MEMORY: {
377 /* XXX: Do we want to return the full amount of system memory ? */
378 uint64_t system_memory;
379
380 if (!os_get_total_physical_memory(&system_memory))
381 return 0;
382
383 return (int)(system_memory >> 20);
384 }
385 }
386
387 /* should only get here on unhandled cases */
388 debug_printf("Unexpected PIPE_CAP %d query\n", param);
389 return 0;
390 }
391
392 static int
393 swr_get_shader_param(struct pipe_screen *screen,
394 enum pipe_shader_type shader,
395 enum pipe_shader_cap param)
396 {
397 if (shader == PIPE_SHADER_VERTEX ||
398 shader == PIPE_SHADER_FRAGMENT ||
399 shader == PIPE_SHADER_GEOMETRY)
400 return gallivm_get_shader_param(param);
401
402 // Todo: tesselation, compute
403 return 0;
404 }
405
406
407 static float
408 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
409 {
410 switch (param) {
411 case PIPE_CAPF_MAX_LINE_WIDTH:
412 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
413 case PIPE_CAPF_MAX_POINT_WIDTH:
414 return 255.0; /* arbitrary */
415 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
416 return 0.0;
417 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
418 return 0.0;
419 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
420 return 16.0; /* arbitrary */
421 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
422 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
423 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
424 return 0.0f;
425 }
426 /* should only get here on unhandled cases */
427 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
428 return 0.0;
429 }
430
431 SWR_FORMAT
432 mesa_to_swr_format(enum pipe_format format)
433 {
434 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
435 /* depth / stencil */
436 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
437 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
438 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
439 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
440 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
441
442 /* alpha */
443 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
444 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
445 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
446 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
447
448 /* odd sizes, bgr */
449 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
450 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
451 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
452 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
453 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
454 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
455 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
456 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
457 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
458
459 /* rgb10a2 */
460 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
461 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
462 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
463 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
464 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
465
466 /* rgb10x2 */
467 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
468
469 /* bgr10a2 */
470 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
471 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
472 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
473 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
474 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
475
476 /* bgr10x2 */
477 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
478
479 /* r11g11b10 */
480 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
481
482 /* 32 bits per component */
483 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
484 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
485 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
486 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
487 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
488
489 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
490 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
491 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
492 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
493
494 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
495 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
496 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
497 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
498
499 {PIPE_FORMAT_R32_UINT, R32_UINT},
500 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
501 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
502 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
503
504 {PIPE_FORMAT_R32_SINT, R32_SINT},
505 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
506 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
507 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
508
509 /* 16 bits per component */
510 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
511 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
512 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
513 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
514 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
515
516 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
517 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
518 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
519 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
520
521 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
522 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
523 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
524 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
525
526 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
527 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
528 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
529 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
530
531 {PIPE_FORMAT_R16_UINT, R16_UINT},
532 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
533 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
534 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
535
536 {PIPE_FORMAT_R16_SINT, R16_SINT},
537 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
538 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
539 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
540
541 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
542 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
543 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
544 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
545 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
546
547 /* 8 bits per component */
548 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
549 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
550 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
551 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
552 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
553 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
554 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
555 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
556
557 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
558 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
559 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
560 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
561
562 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
563 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
564 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
565 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
566
567 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
568 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
569 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
570 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
571
572 {PIPE_FORMAT_R8_UINT, R8_UINT},
573 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
574 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
575 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
576
577 {PIPE_FORMAT_R8_SINT, R8_SINT},
578 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
579 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
580 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
581
582 /* These formats are valid for vertex data, but should not be used
583 * for render targets.
584 */
585
586 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
587 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
588 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
589 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
590
591 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
592 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
593 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
594 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
595
596 /* These formats have entries in SWR but don't have Load/StoreTile
597 * implementations. That means these aren't renderable, and thus having
598 * a mapping entry here is detrimental.
599 */
600 /*
601
602 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
603 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
604 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
605 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
606 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
607
608 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
609 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
610
611 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
612 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
613 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
614
615 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
616 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
617 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
618
619 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
620 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
621 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
622 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
623
624 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
625 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
626 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
627 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
628 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
629 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
630 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
631 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
632
633 {PIPE_FORMAT_I8_UINT, I8_UINT},
634 {PIPE_FORMAT_L8_UINT, L8_UINT},
635 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
636
637 {PIPE_FORMAT_I8_SINT, I8_SINT},
638 {PIPE_FORMAT_L8_SINT, L8_SINT},
639 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
640
641 */
642 };
643
644 auto it = mesa2swr.find(format);
645 if (it == mesa2swr.end())
646 return (SWR_FORMAT)-1;
647 else
648 return it->second;
649 }
650
651 static boolean
652 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
653 {
654 struct sw_winsys *winsys = screen->winsys;
655 struct sw_displaytarget *dt;
656
657 const unsigned width = align(res->swr.width, res->swr.halign);
658 const unsigned height = align(res->swr.height, res->swr.valign);
659
660 UINT stride;
661 dt = winsys->displaytarget_create(winsys,
662 res->base.bind,
663 res->base.format,
664 width, height,
665 64, NULL,
666 &stride);
667
668 if (dt == NULL)
669 return FALSE;
670
671 void *map = winsys->displaytarget_map(winsys, dt, 0);
672
673 res->display_target = dt;
674 res->swr.xpBaseAddress = (gfxptr_t)map;
675
676 /* Clear the display target surface */
677 if (map)
678 memset(map, 0, height * stride);
679
680 winsys->displaytarget_unmap(winsys, dt);
681
682 return TRUE;
683 }
684
685 static bool
686 swr_texture_layout(struct swr_screen *screen,
687 struct swr_resource *res,
688 boolean allocate)
689 {
690 struct pipe_resource *pt = &res->base;
691
692 pipe_format fmt = pt->format;
693 const struct util_format_description *desc = util_format_description(fmt);
694
695 res->has_depth = util_format_has_depth(desc);
696 res->has_stencil = util_format_has_stencil(desc);
697
698 if (res->has_stencil && !res->has_depth)
699 fmt = PIPE_FORMAT_R8_UINT;
700
701 /* We always use the SWR layout. For 2D and 3D textures this looks like:
702 *
703 * |<------- pitch ------->|
704 * +=======================+-------
705 * |Array 0 | ^
706 * | | |
707 * | Level 0 | |
708 * | | |
709 * | | qpitch
710 * +-----------+-----------+ |
711 * | | L2L2L2L2 | |
712 * | Level 1 | L3L3 | |
713 * | | L4 | v
714 * +===========+===========+-------
715 * |Array 1 |
716 * | |
717 * | Level 0 |
718 * | |
719 * | |
720 * +-----------+-----------+
721 * | | L2L2L2L2 |
722 * | Level 1 | L3L3 |
723 * | | L4 |
724 * +===========+===========+
725 *
726 * The overall width in bytes is known as the pitch, while the overall
727 * height in rows is the qpitch. Array slices are laid out logically below
728 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
729 * just invalid for the higher array numbers (since depth is also
730 * minified). 1D and 1D array surfaces are stored effectively the same way,
731 * except that pitch never plays into it. All the levels are logically
732 * adjacent to each other on the X axis. The qpitch becomes the number of
733 * elements between array slices, while the pitch is unused.
734 *
735 * Each level's sizes are subject to the valign and halign settings of the
736 * surface. For compressed formats that swr is unaware of, we will use an
737 * appropriately-sized uncompressed format, and scale the widths/heights.
738 *
739 * This surface is stored inside res->swr. For depth/stencil textures,
740 * res->secondary will have an identically-laid-out but R8_UINT-formatted
741 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
742 * texels, to simplify map/unmap logic which copies the stencil values
743 * in/out.
744 */
745
746 res->swr.width = pt->width0;
747 res->swr.height = pt->height0;
748 res->swr.type = swr_convert_target_type(pt->target);
749 res->swr.tileMode = SWR_TILE_NONE;
750 res->swr.format = mesa_to_swr_format(fmt);
751 res->swr.numSamples = std::max(1u, pt->nr_samples);
752
753 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
754 res->swr.halign = KNOB_MACROTILE_X_DIM;
755 res->swr.valign = KNOB_MACROTILE_Y_DIM;
756
757 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
758 * surface sample count. */
759 if (screen->msaa_force_enable) {
760 res->swr.numSamples = screen->msaa_max_count;
761 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
762 res->swr.numSamples);
763 }
764 } else {
765 res->swr.halign = 1;
766 res->swr.valign = 1;
767 }
768
769 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
770 unsigned width = align(pt->width0, halign);
771 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
772 for (int level = 1; level <= pt->last_level; level++)
773 width += align(u_minify(pt->width0, level), halign);
774 res->swr.pitch = util_format_get_blocksize(fmt);
775 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
776 } else {
777 // The pitch is the overall width of the texture in bytes. Most of the
778 // time this is the pitch of level 0 since all the other levels fit
779 // underneath it. However in some degenerate situations, the width of
780 // level1 + level2 may be larger. In that case, we use those
781 // widths. This can happen if, e.g. halign is 32, and the width of level
782 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
783 // be 32 each, adding up to 64.
784 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
785 if (pt->last_level > 1) {
786 width = std::max<uint32_t>(
787 width,
788 align(u_minify(pt->width0, 1), halign) +
789 align(u_minify(pt->width0, 2), halign));
790 }
791 res->swr.pitch = util_format_get_stride(fmt, width);
792
793 // The qpitch is controlled by either the height of the second LOD, or
794 // the combination of all the later LODs.
795 unsigned height = align(pt->height0, valign);
796 if (pt->last_level == 1) {
797 height += align(u_minify(pt->height0, 1), valign);
798 } else if (pt->last_level > 1) {
799 unsigned level1 = align(u_minify(pt->height0, 1), valign);
800 unsigned level2 = 0;
801 for (int level = 2; level <= pt->last_level; level++) {
802 level2 += align(u_minify(pt->height0, level), valign);
803 }
804 height += std::max(level1, level2);
805 }
806 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
807 }
808
809 if (pt->target == PIPE_TEXTURE_3D)
810 res->swr.depth = pt->depth0;
811 else
812 res->swr.depth = pt->array_size;
813
814 // Fix up swr format if necessary so that LOD offset computation works
815 if (res->swr.format == (SWR_FORMAT)-1) {
816 switch (util_format_get_blocksize(fmt)) {
817 default:
818 unreachable("Unexpected format block size");
819 case 1: res->swr.format = R8_UINT; break;
820 case 2: res->swr.format = R16_UINT; break;
821 case 4: res->swr.format = R32_UINT; break;
822 case 8:
823 if (util_format_is_compressed(fmt))
824 res->swr.format = BC4_UNORM;
825 else
826 res->swr.format = R32G32_UINT;
827 break;
828 case 16:
829 if (util_format_is_compressed(fmt))
830 res->swr.format = BC5_UNORM;
831 else
832 res->swr.format = R32G32B32A32_UINT;
833 break;
834 }
835 }
836
837 for (int level = 0; level <= pt->last_level; level++) {
838 res->mip_offsets[level] =
839 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
840 }
841
842 size_t total_size = (uint64_t)res->swr.depth * res->swr.qpitch *
843 res->swr.pitch * res->swr.numSamples;
844 if (total_size > SWR_MAX_TEXTURE_SIZE)
845 return false;
846
847 if (allocate) {
848 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
849 if (!res->swr.xpBaseAddress)
850 return false;
851
852 if (res->has_depth && res->has_stencil) {
853 res->secondary = res->swr;
854 res->secondary.format = R8_UINT;
855 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
856
857 for (int level = 0; level <= pt->last_level; level++) {
858 res->secondary_mip_offsets[level] =
859 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
860 }
861
862 total_size = res->secondary.depth * res->secondary.qpitch *
863 res->secondary.pitch * res->secondary.numSamples;
864
865 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
866 if (!res->secondary.xpBaseAddress) {
867 AlignedFree((void *)res->swr.xpBaseAddress);
868 return false;
869 }
870 }
871 }
872
873 return true;
874 }
875
876 static boolean
877 swr_can_create_resource(struct pipe_screen *screen,
878 const struct pipe_resource *templat)
879 {
880 struct swr_resource res;
881 memset(&res, 0, sizeof(res));
882 res.base = *templat;
883 return swr_texture_layout(swr_screen(screen), &res, false);
884 }
885
886 /* Helper function that conditionally creates a single-sample resolve resource
887 * and attaches it to main multisample resource. */
888 static boolean
889 swr_create_resolve_resource(struct pipe_screen *_screen,
890 struct swr_resource *msaa_res)
891 {
892 struct swr_screen *screen = swr_screen(_screen);
893
894 /* If resource is multisample, create a single-sample resolve resource */
895 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
896 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
897
898 /* Create a single-sample copy of the resource. Copy the original
899 * resource parameters and set flag to prevent recursion when re-calling
900 * resource_create */
901 struct pipe_resource alt_template = msaa_res->base;
902 alt_template.nr_samples = 0;
903 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
904
905 /* Note: Display_target is a special single-sample resource, only the
906 * display_target has been created already. */
907 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
908 | PIPE_BIND_SHARED)) {
909 /* Allocate the multisample buffers. */
910 if (!swr_texture_layout(screen, msaa_res, true))
911 return false;
912
913 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
914 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
915 alt_template.bind = PIPE_BIND_RENDER_TARGET;
916 }
917
918 /* Allocate single-sample resolve surface */
919 struct pipe_resource *alt;
920 alt = _screen->resource_create(_screen, &alt_template);
921 if (!alt)
922 return false;
923
924 /* Attach it to the multisample resource */
925 msaa_res->resolve_target = alt;
926
927 /* Hang resolve surface state off the multisample surface state to so
928 * StoreTiles knows where to resolve the surface. */
929 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
930 }
931
932 return true; /* success */
933 }
934
935 static struct pipe_resource *
936 swr_resource_create(struct pipe_screen *_screen,
937 const struct pipe_resource *templat)
938 {
939 struct swr_screen *screen = swr_screen(_screen);
940 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
941 if (!res)
942 return NULL;
943
944 res->base = *templat;
945 pipe_reference_init(&res->base.reference, 1);
946 res->base.screen = &screen->base;
947
948 if (swr_resource_is_texture(&res->base)) {
949 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
950 | PIPE_BIND_SHARED)) {
951 /* displayable surface
952 * first call swr_texture_layout without allocating to finish
953 * filling out the SWR_SURFACE_STATE in res */
954 swr_texture_layout(screen, res, false);
955 if (!swr_displaytarget_layout(screen, res))
956 goto fail;
957 } else {
958 /* texture map */
959 if (!swr_texture_layout(screen, res, true))
960 goto fail;
961 }
962
963 /* If resource was multisample, create resolve resource and attach
964 * it to multisample resource. */
965 if (!swr_create_resolve_resource(_screen, res))
966 goto fail;
967
968 } else {
969 /* other data (vertex buffer, const buffer, etc) */
970 assert(util_format_get_blocksize(templat->format) == 1);
971 assert(templat->height0 == 1);
972 assert(templat->depth0 == 1);
973 assert(templat->last_level == 0);
974
975 /* Easiest to just call swr_texture_layout, as it sets up
976 * SWR_SURFACE_STATE in res */
977 if (!swr_texture_layout(screen, res, true))
978 goto fail;
979 }
980
981 return &res->base;
982
983 fail:
984 FREE(res);
985 return NULL;
986 }
987
988 static void
989 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
990 {
991 struct swr_screen *screen = swr_screen(p_screen);
992 struct swr_resource *spr = swr_resource(pt);
993
994 if (spr->display_target) {
995 /* If resource is display target, winsys manages the buffer and will
996 * free it on displaytarget_destroy. */
997 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
998
999 struct sw_winsys *winsys = screen->winsys;
1000 winsys->displaytarget_destroy(winsys, spr->display_target);
1001
1002 if (spr->swr.numSamples > 1) {
1003 /* Free an attached resolve resource */
1004 struct swr_resource *alt = swr_resource(spr->resolve_target);
1005 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1006
1007 /* Free multisample buffer */
1008 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1009 }
1010 } else {
1011 /* For regular resources, defer deletion */
1012 swr_resource_unused(pt);
1013
1014 if (spr->swr.numSamples > 1) {
1015 /* Free an attached resolve resource */
1016 struct swr_resource *alt = swr_resource(spr->resolve_target);
1017 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
1018 }
1019
1020 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
1021 swr_fence_work_free(screen->flush_fence,
1022 (void*)(spr->secondary.xpBaseAddress), true);
1023
1024 /* If work queue grows too large, submit a fence to force queue to
1025 * drain. This is mainly to decrease the amount of memory used by the
1026 * piglit streaming-texture-leak test */
1027 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1028 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1029 }
1030
1031 FREE(spr);
1032 }
1033
1034
1035 static void
1036 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1037 struct pipe_resource *resource,
1038 unsigned level,
1039 unsigned layer,
1040 void *context_private,
1041 struct pipe_box *sub_box)
1042 {
1043 struct swr_screen *screen = swr_screen(p_screen);
1044 struct sw_winsys *winsys = screen->winsys;
1045 struct swr_resource *spr = swr_resource(resource);
1046 struct pipe_context *pipe = screen->pipe;
1047 struct swr_context *ctx = swr_context(pipe);
1048
1049 if (pipe) {
1050 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1051 swr_resource_unused(resource);
1052 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1053 }
1054
1055 /* Multisample resolved into resolve_target at flush with store_resource */
1056 if (pipe && spr->swr.numSamples > 1) {
1057 struct pipe_resource *resolve_target = spr->resolve_target;
1058
1059 /* Once resolved, copy into display target */
1060 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1061
1062 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1063 PIPE_TRANSFER_WRITE);
1064 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1065 winsys->displaytarget_unmap(winsys, spr->display_target);
1066 }
1067
1068 debug_assert(spr->display_target);
1069 if (spr->display_target)
1070 winsys->displaytarget_display(
1071 winsys, spr->display_target, context_private, sub_box);
1072 }
1073
1074
1075 void
1076 swr_destroy_screen_internal(struct swr_screen **screen)
1077 {
1078 struct pipe_screen *p_screen = &(*screen)->base;
1079
1080 swr_fence_finish(p_screen, NULL, (*screen)->flush_fence, 0);
1081 swr_fence_reference(p_screen, &(*screen)->flush_fence, NULL);
1082
1083 JitDestroyContext((*screen)->hJitMgr);
1084
1085 if ((*screen)->pLibrary)
1086 util_dl_close((*screen)->pLibrary);
1087
1088 FREE(*screen);
1089 *screen = NULL;
1090 }
1091
1092
1093 static void
1094 swr_destroy_screen(struct pipe_screen *p_screen)
1095 {
1096 struct swr_screen *screen = swr_screen(p_screen);
1097 struct sw_winsys *winsys = screen->winsys;
1098
1099 fprintf(stderr, "SWR destroy screen!\n");
1100
1101 if (winsys->destroy)
1102 winsys->destroy(winsys);
1103
1104 swr_destroy_screen_internal(&screen);
1105 }
1106
1107
1108 static void
1109 swr_validate_env_options(struct swr_screen *screen)
1110 {
1111 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1112 * copied to scratch space on a draw. Past this, the draw will access
1113 * user-buffer directly and then block. This is faster than queuing many
1114 * large client draws. */
1115 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1116 int client_copy_limit =
1117 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1118 if (client_copy_limit > 0)
1119 screen->client_copy_limit = client_copy_limit;
1120
1121 /* XXX msaa under development, disable by default for now */
1122 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1123
1124 /* validate env override values, within range and power of 2 */
1125 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1126 if (msaa_max_count != 1) {
1127 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1128 || !util_is_power_of_two_or_zero(msaa_max_count)) {
1129 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1130 fprintf(stderr, "must be power of 2 between 1 and %d" \
1131 " (or 1 to disable msaa)\n",
1132 SWR_MAX_NUM_MULTISAMPLES);
1133 msaa_max_count = 1;
1134 }
1135
1136 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1137 if (msaa_max_count == 1)
1138 fprintf(stderr, "(msaa disabled)\n");
1139
1140 screen->msaa_max_count = msaa_max_count;
1141 }
1142
1143 screen->msaa_force_enable = debug_get_bool_option(
1144 "SWR_MSAA_FORCE_ENABLE", false);
1145 if (screen->msaa_force_enable)
1146 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1147 }
1148
1149
1150 struct pipe_screen *
1151 swr_create_screen_internal(struct sw_winsys *winsys)
1152 {
1153 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1154
1155 if (!screen)
1156 return NULL;
1157
1158 if (!lp_build_init()) {
1159 FREE(screen);
1160 return NULL;
1161 }
1162
1163 screen->winsys = winsys;
1164 screen->base.get_name = swr_get_name;
1165 screen->base.get_vendor = swr_get_vendor;
1166 screen->base.is_format_supported = swr_is_format_supported;
1167 screen->base.context_create = swr_create_context;
1168 screen->base.can_create_resource = swr_can_create_resource;
1169
1170 screen->base.destroy = swr_destroy_screen;
1171 screen->base.get_param = swr_get_param;
1172 screen->base.get_shader_param = swr_get_shader_param;
1173 screen->base.get_paramf = swr_get_paramf;
1174
1175 screen->base.resource_create = swr_resource_create;
1176 screen->base.resource_destroy = swr_resource_destroy;
1177
1178 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1179
1180 // Pass in "" for architecture for run-time determination
1181 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1182
1183 swr_fence_init(&screen->base);
1184
1185 swr_validate_env_options(screen);
1186
1187 return &screen->base;
1188 }
1189