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swr: Rework scratch space allocation
[mesa.git] / src / gallium / drivers / swr / swr_screen.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #include "swr_context.h"
25 #include "swr_public.h"
26 #include "swr_screen.h"
27 #include "swr_resource.h"
28 #include "swr_fence.h"
29 #include "gen_knobs.h"
30
31 #include "pipe/p_screen.h"
32 #include "pipe/p_defines.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_inlines.h"
36 #include "util/u_cpu_detect.h"
37 #include "util/u_format_s3tc.h"
38 #include "util/u_string.h"
39
40 #include "state_tracker/sw_winsys.h"
41
42 #include "jit_api.h"
43
44 #include "memory/TilingFunctions.h"
45
46 #include <stdio.h>
47 #include <map>
48
49 /*
50 * Max texture sizes
51 * XXX Check max texture size values against core and sampler.
52 */
53 #define SWR_MAX_TEXTURE_SIZE (4 * 1024 * 1024 * 1024ULL) /* 4GB */
54 #define SWR_MAX_TEXTURE_2D_LEVELS 14 /* 8K x 8K for now */
55 #define SWR_MAX_TEXTURE_3D_LEVELS 12 /* 2K x 2K x 2K for now */
56 #define SWR_MAX_TEXTURE_CUBE_LEVELS 14 /* 8K x 8K for now */
57 #define SWR_MAX_TEXTURE_ARRAY_LAYERS 512 /* 8K x 512 / 8K x 8K x 512 */
58
59 /* Default max client_copy_limit */
60 #define SWR_CLIENT_COPY_LIMIT 8192
61
62 /* Flag indicates creation of alternate surface, to prevent recursive loop
63 * in resource creation when msaa_force_enable is set. */
64 #define SWR_RESOURCE_FLAG_ALT_SURFACE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
65
66
67 static const char *
68 swr_get_name(struct pipe_screen *screen)
69 {
70 static char buf[100];
71 util_snprintf(buf, sizeof(buf), "SWR (LLVM %u.%u, %u bits)",
72 HAVE_LLVM >> 8, HAVE_LLVM & 0xff,
73 lp_native_vector_width );
74 return buf;
75 }
76
77 static const char *
78 swr_get_vendor(struct pipe_screen *screen)
79 {
80 return "Intel Corporation";
81 }
82
83 static boolean
84 swr_is_format_supported(struct pipe_screen *_screen,
85 enum pipe_format format,
86 enum pipe_texture_target target,
87 unsigned sample_count,
88 unsigned bind)
89 {
90 struct swr_screen *screen = swr_screen(_screen);
91 struct sw_winsys *winsys = screen->winsys;
92 const struct util_format_description *format_desc;
93
94 assert(target == PIPE_BUFFER || target == PIPE_TEXTURE_1D
95 || target == PIPE_TEXTURE_1D_ARRAY
96 || target == PIPE_TEXTURE_2D
97 || target == PIPE_TEXTURE_2D_ARRAY
98 || target == PIPE_TEXTURE_RECT
99 || target == PIPE_TEXTURE_3D
100 || target == PIPE_TEXTURE_CUBE
101 || target == PIPE_TEXTURE_CUBE_ARRAY);
102
103 format_desc = util_format_description(format);
104 if (!format_desc)
105 return FALSE;
106
107 if ((sample_count > screen->msaa_max_count)
108 || !util_is_power_of_two(sample_count))
109 return FALSE;
110
111 if (bind & PIPE_BIND_DISPLAY_TARGET) {
112 if (!winsys->is_displaytarget_format_supported(winsys, bind, format))
113 return FALSE;
114 }
115
116 if (bind & PIPE_BIND_RENDER_TARGET) {
117 if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
118 return FALSE;
119
120 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
121 return FALSE;
122
123 /*
124 * Although possible, it is unnatural to render into compressed or YUV
125 * surfaces. So disable these here to avoid going into weird paths
126 * inside the state trackers.
127 */
128 if (format_desc->block.width != 1 || format_desc->block.height != 1)
129 return FALSE;
130 }
131
132 if (bind & PIPE_BIND_DEPTH_STENCIL) {
133 if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
134 return FALSE;
135
136 if (mesa_to_swr_format(format) == (SWR_FORMAT)-1)
137 return FALSE;
138 }
139
140 if (format_desc->layout == UTIL_FORMAT_LAYOUT_BPTC ||
141 format_desc->layout == UTIL_FORMAT_LAYOUT_ASTC) {
142 return FALSE;
143 }
144
145 if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
146 format != PIPE_FORMAT_ETC1_RGB8) {
147 return FALSE;
148 }
149
150 return TRUE;
151 }
152
153 static int
154 swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
155 {
156 switch (param) {
157 /* limits */
158 case PIPE_CAP_MAX_RENDER_TARGETS:
159 return PIPE_MAX_COLOR_BUFS;
160 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
161 return SWR_MAX_TEXTURE_2D_LEVELS;
162 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
163 return SWR_MAX_TEXTURE_3D_LEVELS;
164 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
165 return SWR_MAX_TEXTURE_CUBE_LEVELS;
166 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
167 return MAX_SO_STREAMS;
168 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
169 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
170 return MAX_ATTRIBUTES * 4;
171 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
172 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
173 return 1024;
174 case PIPE_CAP_MAX_VERTEX_STREAMS:
175 return 1;
176 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
177 return 2048;
178 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
179 return SWR_MAX_TEXTURE_ARRAY_LAYERS;
180 case PIPE_CAP_MIN_TEXEL_OFFSET:
181 return -8;
182 case PIPE_CAP_MAX_TEXEL_OFFSET:
183 return 7;
184 case PIPE_CAP_GLSL_FEATURE_LEVEL:
185 return 330;
186 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
187 return 16;
188 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
189 return 64;
190 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
191 return 65536;
192 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
193 return 0;
194 case PIPE_CAP_MAX_VIEWPORTS:
195 return 1;
196 case PIPE_CAP_ENDIANNESS:
197 return PIPE_ENDIAN_NATIVE;
198 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
199 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
200 return 0;
201
202 /* supported features */
203 case PIPE_CAP_NPOT_TEXTURES:
204 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
205 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
206 case PIPE_CAP_TWO_SIDED_STENCIL:
207 case PIPE_CAP_SM3:
208 case PIPE_CAP_POINT_SPRITE:
209 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
210 case PIPE_CAP_OCCLUSION_QUERY:
211 case PIPE_CAP_QUERY_TIME_ELAPSED:
212 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
213 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
214 case PIPE_CAP_TEXTURE_SHADOW_MAP:
215 case PIPE_CAP_TEXTURE_SWIZZLE:
216 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
217 case PIPE_CAP_INDEP_BLEND_ENABLE:
218 case PIPE_CAP_INDEP_BLEND_FUNC:
219 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
220 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
221 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
222 case PIPE_CAP_DEPTH_CLIP_DISABLE:
223 case PIPE_CAP_PRIMITIVE_RESTART:
224 case PIPE_CAP_TGSI_INSTANCEID:
225 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
226 case PIPE_CAP_START_INSTANCE:
227 case PIPE_CAP_SEAMLESS_CUBE_MAP:
228 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
229 case PIPE_CAP_CONDITIONAL_RENDER:
230 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
231 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
232 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
233 case PIPE_CAP_USER_VERTEX_BUFFERS:
234 case PIPE_CAP_USER_CONSTANT_BUFFERS:
235 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
236 case PIPE_CAP_QUERY_TIMESTAMP:
237 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
238 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
239 case PIPE_CAP_DRAW_INDIRECT:
240 case PIPE_CAP_UMA:
241 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
242 case PIPE_CAP_CLIP_HALFZ:
243 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
244 case PIPE_CAP_DEPTH_BOUNDS_TEST:
245 case PIPE_CAP_CLEAR_TEXTURE:
246 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
247 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
248 case PIPE_CAP_CULL_DISTANCE:
249 case PIPE_CAP_CUBE_MAP_ARRAY:
250 case PIPE_CAP_DOUBLES:
251 return 1;
252
253 /* MSAA support
254 * If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
255 * then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
256 case PIPE_CAP_TEXTURE_MULTISAMPLE:
257 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
258 return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
259 case PIPE_CAP_FAKE_SW_MSAA:
260 return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;
261
262 /* fetch jit change for 2-4GB buffers requires alignment */
263 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
264 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
265 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
266 return 1;
267
268 /* unsupported features */
269 case PIPE_CAP_ANISOTROPIC_FILTER:
270 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
271 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
272 case PIPE_CAP_SHADER_STENCIL_EXPORT:
273 case PIPE_CAP_TEXTURE_BARRIER:
274 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
275 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
276 case PIPE_CAP_COMPUTE:
277 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
278 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
279 case PIPE_CAP_TGSI_TEXCOORD:
280 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
281 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
282 case PIPE_CAP_TEXTURE_GATHER_SM5:
283 case PIPE_CAP_TEXTURE_QUERY_LOD:
284 case PIPE_CAP_SAMPLE_SHADING:
285 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
286 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
287 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
288 case PIPE_CAP_SAMPLER_VIEW_TARGET:
289 case PIPE_CAP_VERTEXID_NOBASE:
290 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
291 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
292 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
293 case PIPE_CAP_TGSI_TXQS:
294 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
295 case PIPE_CAP_SHAREABLE_SHADERS:
296 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
297 case PIPE_CAP_DRAW_PARAMETERS:
298 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
299 case PIPE_CAP_MULTI_DRAW_INDIRECT:
300 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
301 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
302 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
303 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
304 case PIPE_CAP_INVALIDATE_BUFFER:
305 case PIPE_CAP_GENERATE_MIPMAP:
306 case PIPE_CAP_STRING_MARKER:
307 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
308 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
309 case PIPE_CAP_QUERY_BUFFER_OBJECT:
310 case PIPE_CAP_QUERY_MEMORY_INFO:
311 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
312 case PIPE_CAP_PCI_GROUP:
313 case PIPE_CAP_PCI_BUS:
314 case PIPE_CAP_PCI_DEVICE:
315 case PIPE_CAP_PCI_FUNCTION:
316 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
317 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
318 case PIPE_CAP_TGSI_VOTE:
319 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
320 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
321 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
322 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
323 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
324 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
325 case PIPE_CAP_NATIVE_FENCE_FD:
326 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
327 case PIPE_CAP_TGSI_FS_FBFETCH:
328 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
329 case PIPE_CAP_INT64:
330 case PIPE_CAP_INT64_DIVMOD:
331 case PIPE_CAP_TGSI_TEX_TXF_LZ:
332 case PIPE_CAP_TGSI_CLOCK:
333 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
334 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
335 case PIPE_CAP_TGSI_BALLOT:
336 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
337 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
338 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
339 case PIPE_CAP_POST_DEPTH_COVERAGE:
340 case PIPE_CAP_BINDLESS_TEXTURE:
341 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
342 case PIPE_CAP_QUERY_SO_OVERFLOW:
343 case PIPE_CAP_MEMOBJ:
344 case PIPE_CAP_LOAD_CONSTBUF:
345 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
346 case PIPE_CAP_TILE_RASTER_ORDER:
347 return 0;
348
349 case PIPE_CAP_VENDOR_ID:
350 return 0xFFFFFFFF;
351 case PIPE_CAP_DEVICE_ID:
352 return 0xFFFFFFFF;
353 case PIPE_CAP_ACCELERATED:
354 return 0;
355 case PIPE_CAP_VIDEO_MEMORY: {
356 /* XXX: Do we want to return the full amount of system memory ? */
357 uint64_t system_memory;
358
359 if (!os_get_total_physical_memory(&system_memory))
360 return 0;
361
362 return (int)(system_memory >> 20);
363 }
364 }
365
366 /* should only get here on unhandled cases */
367 debug_printf("Unexpected PIPE_CAP %d query\n", param);
368 return 0;
369 }
370
371 static int
372 swr_get_shader_param(struct pipe_screen *screen,
373 enum pipe_shader_type shader,
374 enum pipe_shader_cap param)
375 {
376 if (shader == PIPE_SHADER_VERTEX ||
377 shader == PIPE_SHADER_FRAGMENT ||
378 shader == PIPE_SHADER_GEOMETRY)
379 return gallivm_get_shader_param(param);
380
381 // Todo: tesselation, compute
382 return 0;
383 }
384
385
386 static float
387 swr_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
388 {
389 switch (param) {
390 case PIPE_CAPF_MAX_LINE_WIDTH:
391 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
392 case PIPE_CAPF_MAX_POINT_WIDTH:
393 return 255.0; /* arbitrary */
394 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
395 return 0.0;
396 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
397 return 0.0;
398 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
399 return 16.0; /* arbitrary */
400 case PIPE_CAPF_GUARD_BAND_LEFT:
401 case PIPE_CAPF_GUARD_BAND_TOP:
402 case PIPE_CAPF_GUARD_BAND_RIGHT:
403 case PIPE_CAPF_GUARD_BAND_BOTTOM:
404 return 0.0;
405 }
406 /* should only get here on unhandled cases */
407 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
408 return 0.0;
409 }
410
411 SWR_FORMAT
412 mesa_to_swr_format(enum pipe_format format)
413 {
414 static const std::map<pipe_format,SWR_FORMAT> mesa2swr = {
415 /* depth / stencil */
416 {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
417 {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
418 {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
419 {PIPE_FORMAT_Z24X8_UNORM, R24_UNORM_X8_TYPELESS}, // z
420 {PIPE_FORMAT_Z32_FLOAT_S8X24_UINT, R32_FLOAT_X8X24_TYPELESS}, // z
421
422 /* alpha */
423 {PIPE_FORMAT_A8_UNORM, A8_UNORM},
424 {PIPE_FORMAT_A16_UNORM, A16_UNORM},
425 {PIPE_FORMAT_A16_FLOAT, A16_FLOAT},
426 {PIPE_FORMAT_A32_FLOAT, A32_FLOAT},
427
428 /* odd sizes, bgr */
429 {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
430 {PIPE_FORMAT_B5G6R5_SRGB, B5G6R5_UNORM_SRGB},
431 {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
432 {PIPE_FORMAT_B5G5R5X1_UNORM, B5G5R5X1_UNORM},
433 {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
434 {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
435 {PIPE_FORMAT_B8G8R8A8_SRGB, B8G8R8A8_UNORM_SRGB},
436 {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
437 {PIPE_FORMAT_B8G8R8X8_SRGB, B8G8R8X8_UNORM_SRGB},
438
439 /* rgb10a2 */
440 {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
441 {PIPE_FORMAT_R10G10B10A2_SNORM, R10G10B10A2_SNORM},
442 {PIPE_FORMAT_R10G10B10A2_USCALED, R10G10B10A2_USCALED},
443 {PIPE_FORMAT_R10G10B10A2_SSCALED, R10G10B10A2_SSCALED},
444 {PIPE_FORMAT_R10G10B10A2_UINT, R10G10B10A2_UINT},
445
446 /* rgb10x2 */
447 {PIPE_FORMAT_R10G10B10X2_USCALED, R10G10B10X2_USCALED},
448
449 /* bgr10a2 */
450 {PIPE_FORMAT_B10G10R10A2_UNORM, B10G10R10A2_UNORM},
451 {PIPE_FORMAT_B10G10R10A2_SNORM, B10G10R10A2_SNORM},
452 {PIPE_FORMAT_B10G10R10A2_USCALED, B10G10R10A2_USCALED},
453 {PIPE_FORMAT_B10G10R10A2_SSCALED, B10G10R10A2_SSCALED},
454 {PIPE_FORMAT_B10G10R10A2_UINT, B10G10R10A2_UINT},
455
456 /* bgr10x2 */
457 {PIPE_FORMAT_B10G10R10X2_UNORM, B10G10R10X2_UNORM},
458
459 /* r11g11b10 */
460 {PIPE_FORMAT_R11G11B10_FLOAT, R11G11B10_FLOAT},
461
462 /* 32 bits per component */
463 {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
464 {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
465 {PIPE_FORMAT_R32G32B32_FLOAT, R32G32B32_FLOAT},
466 {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
467 {PIPE_FORMAT_R32G32B32X32_FLOAT, R32G32B32X32_FLOAT},
468
469 {PIPE_FORMAT_R32_USCALED, R32_USCALED},
470 {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
471 {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
472 {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
473
474 {PIPE_FORMAT_R32_SSCALED, R32_SSCALED},
475 {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
476 {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
477 {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
478
479 {PIPE_FORMAT_R32_UINT, R32_UINT},
480 {PIPE_FORMAT_R32G32_UINT, R32G32_UINT},
481 {PIPE_FORMAT_R32G32B32_UINT, R32G32B32_UINT},
482 {PIPE_FORMAT_R32G32B32A32_UINT, R32G32B32A32_UINT},
483
484 {PIPE_FORMAT_R32_SINT, R32_SINT},
485 {PIPE_FORMAT_R32G32_SINT, R32G32_SINT},
486 {PIPE_FORMAT_R32G32B32_SINT, R32G32B32_SINT},
487 {PIPE_FORMAT_R32G32B32A32_SINT, R32G32B32A32_SINT},
488
489 /* 16 bits per component */
490 {PIPE_FORMAT_R16_UNORM, R16_UNORM},
491 {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
492 {PIPE_FORMAT_R16G16B16_UNORM, R16G16B16_UNORM},
493 {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
494 {PIPE_FORMAT_R16G16B16X16_UNORM, R16G16B16X16_UNORM},
495
496 {PIPE_FORMAT_R16_USCALED, R16_USCALED},
497 {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
498 {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
499 {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
500
501 {PIPE_FORMAT_R16_SNORM, R16_SNORM},
502 {PIPE_FORMAT_R16G16_SNORM, R16G16_SNORM},
503 {PIPE_FORMAT_R16G16B16_SNORM, R16G16B16_SNORM},
504 {PIPE_FORMAT_R16G16B16A16_SNORM, R16G16B16A16_SNORM},
505
506 {PIPE_FORMAT_R16_SSCALED, R16_SSCALED},
507 {PIPE_FORMAT_R16G16_SSCALED, R16G16_SSCALED},
508 {PIPE_FORMAT_R16G16B16_SSCALED, R16G16B16_SSCALED},
509 {PIPE_FORMAT_R16G16B16A16_SSCALED, R16G16B16A16_SSCALED},
510
511 {PIPE_FORMAT_R16_UINT, R16_UINT},
512 {PIPE_FORMAT_R16G16_UINT, R16G16_UINT},
513 {PIPE_FORMAT_R16G16B16_UINT, R16G16B16_UINT},
514 {PIPE_FORMAT_R16G16B16A16_UINT, R16G16B16A16_UINT},
515
516 {PIPE_FORMAT_R16_SINT, R16_SINT},
517 {PIPE_FORMAT_R16G16_SINT, R16G16_SINT},
518 {PIPE_FORMAT_R16G16B16_SINT, R16G16B16_SINT},
519 {PIPE_FORMAT_R16G16B16A16_SINT, R16G16B16A16_SINT},
520
521 {PIPE_FORMAT_R16_FLOAT, R16_FLOAT},
522 {PIPE_FORMAT_R16G16_FLOAT, R16G16_FLOAT},
523 {PIPE_FORMAT_R16G16B16_FLOAT, R16G16B16_FLOAT},
524 {PIPE_FORMAT_R16G16B16A16_FLOAT, R16G16B16A16_FLOAT},
525 {PIPE_FORMAT_R16G16B16X16_FLOAT, R16G16B16X16_FLOAT},
526
527 /* 8 bits per component */
528 {PIPE_FORMAT_R8_UNORM, R8_UNORM},
529 {PIPE_FORMAT_R8G8_UNORM, R8G8_UNORM},
530 {PIPE_FORMAT_R8G8B8_UNORM, R8G8B8_UNORM},
531 {PIPE_FORMAT_R8G8B8_SRGB, R8G8B8_UNORM_SRGB},
532 {PIPE_FORMAT_R8G8B8A8_UNORM, R8G8B8A8_UNORM},
533 {PIPE_FORMAT_R8G8B8A8_SRGB, R8G8B8A8_UNORM_SRGB},
534 {PIPE_FORMAT_R8G8B8X8_UNORM, R8G8B8X8_UNORM},
535 {PIPE_FORMAT_R8G8B8X8_SRGB, R8G8B8X8_UNORM_SRGB},
536
537 {PIPE_FORMAT_R8_USCALED, R8_USCALED},
538 {PIPE_FORMAT_R8G8_USCALED, R8G8_USCALED},
539 {PIPE_FORMAT_R8G8B8_USCALED, R8G8B8_USCALED},
540 {PIPE_FORMAT_R8G8B8A8_USCALED, R8G8B8A8_USCALED},
541
542 {PIPE_FORMAT_R8_SNORM, R8_SNORM},
543 {PIPE_FORMAT_R8G8_SNORM, R8G8_SNORM},
544 {PIPE_FORMAT_R8G8B8_SNORM, R8G8B8_SNORM},
545 {PIPE_FORMAT_R8G8B8A8_SNORM, R8G8B8A8_SNORM},
546
547 {PIPE_FORMAT_R8_SSCALED, R8_SSCALED},
548 {PIPE_FORMAT_R8G8_SSCALED, R8G8_SSCALED},
549 {PIPE_FORMAT_R8G8B8_SSCALED, R8G8B8_SSCALED},
550 {PIPE_FORMAT_R8G8B8A8_SSCALED, R8G8B8A8_SSCALED},
551
552 {PIPE_FORMAT_R8_UINT, R8_UINT},
553 {PIPE_FORMAT_R8G8_UINT, R8G8_UINT},
554 {PIPE_FORMAT_R8G8B8_UINT, R8G8B8_UINT},
555 {PIPE_FORMAT_R8G8B8A8_UINT, R8G8B8A8_UINT},
556
557 {PIPE_FORMAT_R8_SINT, R8_SINT},
558 {PIPE_FORMAT_R8G8_SINT, R8G8_SINT},
559 {PIPE_FORMAT_R8G8B8_SINT, R8G8B8_SINT},
560 {PIPE_FORMAT_R8G8B8A8_SINT, R8G8B8A8_SINT},
561
562 /* These formats are valid for vertex data, but should not be used
563 * for render targets.
564 */
565
566 {PIPE_FORMAT_R32_FIXED, R32_SFIXED},
567 {PIPE_FORMAT_R32G32_FIXED, R32G32_SFIXED},
568 {PIPE_FORMAT_R32G32B32_FIXED, R32G32B32_SFIXED},
569 {PIPE_FORMAT_R32G32B32A32_FIXED, R32G32B32A32_SFIXED},
570
571 {PIPE_FORMAT_R64_FLOAT, R64_FLOAT},
572 {PIPE_FORMAT_R64G64_FLOAT, R64G64_FLOAT},
573 {PIPE_FORMAT_R64G64B64_FLOAT, R64G64B64_FLOAT},
574 {PIPE_FORMAT_R64G64B64A64_FLOAT, R64G64B64A64_FLOAT},
575
576 /* These formats have entries in SWR but don't have Load/StoreTile
577 * implementations. That means these aren't renderable, and thus having
578 * a mapping entry here is detrimental.
579 */
580 /*
581
582 {PIPE_FORMAT_L8_UNORM, L8_UNORM},
583 {PIPE_FORMAT_I8_UNORM, I8_UNORM},
584 {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
585 {PIPE_FORMAT_L16_UNORM, L16_UNORM},
586 {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
587
588 {PIPE_FORMAT_L8_SRGB, L8_UNORM_SRGB},
589 {PIPE_FORMAT_L8A8_SRGB, L8A8_UNORM_SRGB},
590
591 {PIPE_FORMAT_DXT1_RGBA, BC1_UNORM},
592 {PIPE_FORMAT_DXT3_RGBA, BC2_UNORM},
593 {PIPE_FORMAT_DXT5_RGBA, BC3_UNORM},
594
595 {PIPE_FORMAT_DXT1_SRGBA, BC1_UNORM_SRGB},
596 {PIPE_FORMAT_DXT3_SRGBA, BC2_UNORM_SRGB},
597 {PIPE_FORMAT_DXT5_SRGBA, BC3_UNORM_SRGB},
598
599 {PIPE_FORMAT_RGTC1_UNORM, BC4_UNORM},
600 {PIPE_FORMAT_RGTC1_SNORM, BC4_SNORM},
601 {PIPE_FORMAT_RGTC2_UNORM, BC5_UNORM},
602 {PIPE_FORMAT_RGTC2_SNORM, BC5_SNORM},
603
604 {PIPE_FORMAT_L16A16_UNORM, L16A16_UNORM},
605 {PIPE_FORMAT_I16_UNORM, I16_UNORM},
606 {PIPE_FORMAT_L16_FLOAT, L16_FLOAT},
607 {PIPE_FORMAT_L16A16_FLOAT, L16A16_FLOAT},
608 {PIPE_FORMAT_I16_FLOAT, I16_FLOAT},
609 {PIPE_FORMAT_L32_FLOAT, L32_FLOAT},
610 {PIPE_FORMAT_L32A32_FLOAT, L32A32_FLOAT},
611 {PIPE_FORMAT_I32_FLOAT, I32_FLOAT},
612
613 {PIPE_FORMAT_I8_UINT, I8_UINT},
614 {PIPE_FORMAT_L8_UINT, L8_UINT},
615 {PIPE_FORMAT_L8A8_UINT, L8A8_UINT},
616
617 {PIPE_FORMAT_I8_SINT, I8_SINT},
618 {PIPE_FORMAT_L8_SINT, L8_SINT},
619 {PIPE_FORMAT_L8A8_SINT, L8A8_SINT},
620
621 */
622 };
623
624 auto it = mesa2swr.find(format);
625 if (it == mesa2swr.end())
626 return (SWR_FORMAT)-1;
627 else
628 return it->second;
629 }
630
631 static boolean
632 swr_displaytarget_layout(struct swr_screen *screen, struct swr_resource *res)
633 {
634 struct sw_winsys *winsys = screen->winsys;
635 struct sw_displaytarget *dt;
636
637 const unsigned width = align(res->swr.width, res->swr.halign);
638 const unsigned height = align(res->swr.height, res->swr.valign);
639
640 UINT stride;
641 dt = winsys->displaytarget_create(winsys,
642 res->base.bind,
643 res->base.format,
644 width, height,
645 64, NULL,
646 &stride);
647
648 if (dt == NULL)
649 return FALSE;
650
651 void *map = winsys->displaytarget_map(winsys, dt, 0);
652
653 res->display_target = dt;
654 res->swr.xpBaseAddress = (gfxptr_t)map;
655
656 /* Clear the display target surface */
657 if (map)
658 memset(map, 0, height * stride);
659
660 winsys->displaytarget_unmap(winsys, dt);
661
662 return TRUE;
663 }
664
665 static bool
666 swr_texture_layout(struct swr_screen *screen,
667 struct swr_resource *res,
668 boolean allocate)
669 {
670 struct pipe_resource *pt = &res->base;
671
672 pipe_format fmt = pt->format;
673 const struct util_format_description *desc = util_format_description(fmt);
674
675 res->has_depth = util_format_has_depth(desc);
676 res->has_stencil = util_format_has_stencil(desc);
677
678 if (res->has_stencil && !res->has_depth)
679 fmt = PIPE_FORMAT_R8_UINT;
680
681 /* We always use the SWR layout. For 2D and 3D textures this looks like:
682 *
683 * |<------- pitch ------->|
684 * +=======================+-------
685 * |Array 0 | ^
686 * | | |
687 * | Level 0 | |
688 * | | |
689 * | | qpitch
690 * +-----------+-----------+ |
691 * | | L2L2L2L2 | |
692 * | Level 1 | L3L3 | |
693 * | | L4 | v
694 * +===========+===========+-------
695 * |Array 1 |
696 * | |
697 * | Level 0 |
698 * | |
699 * | |
700 * +-----------+-----------+
701 * | | L2L2L2L2 |
702 * | Level 1 | L3L3 |
703 * | | L4 |
704 * +===========+===========+
705 *
706 * The overall width in bytes is known as the pitch, while the overall
707 * height in rows is the qpitch. Array slices are laid out logically below
708 * one another, qpitch rows apart. For 3D surfaces, the "level" values are
709 * just invalid for the higher array numbers (since depth is also
710 * minified). 1D and 1D array surfaces are stored effectively the same way,
711 * except that pitch never plays into it. All the levels are logically
712 * adjacent to each other on the X axis. The qpitch becomes the number of
713 * elements between array slices, while the pitch is unused.
714 *
715 * Each level's sizes are subject to the valign and halign settings of the
716 * surface. For compressed formats that swr is unaware of, we will use an
717 * appropriately-sized uncompressed format, and scale the widths/heights.
718 *
719 * This surface is stored inside res->swr. For depth/stencil textures,
720 * res->secondary will have an identically-laid-out but R8_UINT-formatted
721 * stencil tree. In the Z32F_S8 case, the primary surface still has 64-bpp
722 * texels, to simplify map/unmap logic which copies the stencil values
723 * in/out.
724 */
725
726 res->swr.width = pt->width0;
727 res->swr.height = pt->height0;
728 res->swr.type = swr_convert_target_type(pt->target);
729 res->swr.tileMode = SWR_TILE_NONE;
730 res->swr.format = mesa_to_swr_format(fmt);
731 res->swr.numSamples = std::max(1u, pt->nr_samples);
732
733 if (pt->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)) {
734 res->swr.halign = KNOB_MACROTILE_X_DIM;
735 res->swr.valign = KNOB_MACROTILE_Y_DIM;
736
737 /* If SWR_MSAA_FORCE_ENABLE is set, turn on MSAA and override requested
738 * surface sample count. */
739 if (screen->msaa_force_enable) {
740 res->swr.numSamples = screen->msaa_max_count;
741 fprintf(stderr,"swr_texture_layout: forcing sample count: %d\n",
742 res->swr.numSamples);
743 }
744 } else {
745 res->swr.halign = 1;
746 res->swr.valign = 1;
747 }
748
749 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt);
750 unsigned width = align(pt->width0, halign);
751 if (pt->target == PIPE_TEXTURE_1D || pt->target == PIPE_TEXTURE_1D_ARRAY) {
752 for (int level = 1; level <= pt->last_level; level++)
753 width += align(u_minify(pt->width0, level), halign);
754 res->swr.pitch = util_format_get_blocksize(fmt);
755 res->swr.qpitch = util_format_get_nblocksx(fmt, width);
756 } else {
757 // The pitch is the overall width of the texture in bytes. Most of the
758 // time this is the pitch of level 0 since all the other levels fit
759 // underneath it. However in some degenerate situations, the width of
760 // level1 + level2 may be larger. In that case, we use those
761 // widths. This can happen if, e.g. halign is 32, and the width of level
762 // 0 is 32 or less. In that case, the aligned levels 1 and 2 will also
763 // be 32 each, adding up to 64.
764 unsigned valign = res->swr.valign * util_format_get_blockheight(fmt);
765 if (pt->last_level > 1) {
766 width = std::max<uint32_t>(
767 width,
768 align(u_minify(pt->width0, 1), halign) +
769 align(u_minify(pt->width0, 2), halign));
770 }
771 res->swr.pitch = util_format_get_stride(fmt, width);
772
773 // The qpitch is controlled by either the height of the second LOD, or
774 // the combination of all the later LODs.
775 unsigned height = align(pt->height0, valign);
776 if (pt->last_level == 1) {
777 height += align(u_minify(pt->height0, 1), valign);
778 } else if (pt->last_level > 1) {
779 unsigned level1 = align(u_minify(pt->height0, 1), valign);
780 unsigned level2 = 0;
781 for (int level = 2; level <= pt->last_level; level++) {
782 level2 += align(u_minify(pt->height0, level), valign);
783 }
784 height += std::max(level1, level2);
785 }
786 res->swr.qpitch = util_format_get_nblocksy(fmt, height);
787 }
788
789 if (pt->target == PIPE_TEXTURE_3D)
790 res->swr.depth = pt->depth0;
791 else
792 res->swr.depth = pt->array_size;
793
794 // Fix up swr format if necessary so that LOD offset computation works
795 if (res->swr.format == (SWR_FORMAT)-1) {
796 switch (util_format_get_blocksize(fmt)) {
797 default:
798 unreachable("Unexpected format block size");
799 case 1: res->swr.format = R8_UINT; break;
800 case 2: res->swr.format = R16_UINT; break;
801 case 4: res->swr.format = R32_UINT; break;
802 case 8:
803 if (util_format_is_compressed(fmt))
804 res->swr.format = BC4_UNORM;
805 else
806 res->swr.format = R32G32_UINT;
807 break;
808 case 16:
809 if (util_format_is_compressed(fmt))
810 res->swr.format = BC5_UNORM;
811 else
812 res->swr.format = R32G32B32A32_UINT;
813 break;
814 }
815 }
816
817 for (int level = 0; level <= pt->last_level; level++) {
818 res->mip_offsets[level] =
819 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->swr);
820 }
821
822 size_t total_size = res->swr.depth * res->swr.qpitch * res->swr.pitch *
823 res->swr.numSamples;
824 if (total_size > SWR_MAX_TEXTURE_SIZE)
825 return false;
826
827 if (allocate) {
828 res->swr.xpBaseAddress = (gfxptr_t)AlignedMalloc(total_size, 64);
829
830 if (res->has_depth && res->has_stencil) {
831 res->secondary = res->swr;
832 res->secondary.format = R8_UINT;
833 res->secondary.pitch = res->swr.pitch / util_format_get_blocksize(fmt);
834
835 for (int level = 0; level <= pt->last_level; level++) {
836 res->secondary_mip_offsets[level] =
837 ComputeSurfaceOffset<false>(0, 0, 0, 0, 0, level, &res->secondary);
838 }
839
840 total_size = res->secondary.depth * res->secondary.qpitch *
841 res->secondary.pitch * res->secondary.numSamples;
842
843 res->secondary.xpBaseAddress = (gfxptr_t) AlignedMalloc(total_size, 64);
844 }
845 }
846
847 return true;
848 }
849
850 static boolean
851 swr_can_create_resource(struct pipe_screen *screen,
852 const struct pipe_resource *templat)
853 {
854 struct swr_resource res;
855 memset(&res, 0, sizeof(res));
856 res.base = *templat;
857 return swr_texture_layout(swr_screen(screen), &res, false);
858 }
859
860 /* Helper function that conditionally creates a single-sample resolve resource
861 * and attaches it to main multisample resource. */
862 static boolean
863 swr_create_resolve_resource(struct pipe_screen *_screen,
864 struct swr_resource *msaa_res)
865 {
866 struct swr_screen *screen = swr_screen(_screen);
867
868 /* If resource is multisample, create a single-sample resolve resource */
869 if (msaa_res->base.nr_samples > 1 || (screen->msaa_force_enable &&
870 !(msaa_res->base.flags & SWR_RESOURCE_FLAG_ALT_SURFACE))) {
871
872 /* Create a single-sample copy of the resource. Copy the original
873 * resource parameters and set flag to prevent recursion when re-calling
874 * resource_create */
875 struct pipe_resource alt_template = msaa_res->base;
876 alt_template.nr_samples = 0;
877 alt_template.flags |= SWR_RESOURCE_FLAG_ALT_SURFACE;
878
879 /* Note: Display_target is a special single-sample resource, only the
880 * display_target has been created already. */
881 if (msaa_res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
882 | PIPE_BIND_SHARED)) {
883 /* Allocate the multisample buffers. */
884 if (!swr_texture_layout(screen, msaa_res, true))
885 return false;
886
887 /* Alt resource will only be bound as PIPE_BIND_RENDER_TARGET
888 * remove the DISPLAY_TARGET, SCANOUT, and SHARED bindings */
889 alt_template.bind = PIPE_BIND_RENDER_TARGET;
890 }
891
892 /* Allocate single-sample resolve surface */
893 struct pipe_resource *alt;
894 alt = _screen->resource_create(_screen, &alt_template);
895 if (!alt)
896 return false;
897
898 /* Attach it to the multisample resource */
899 msaa_res->resolve_target = alt;
900
901 /* Hang resolve surface state off the multisample surface state to so
902 * StoreTiles knows where to resolve the surface. */
903 msaa_res->swr.xpAuxBaseAddress = (gfxptr_t)&swr_resource(alt)->swr;
904 }
905
906 return true; /* success */
907 }
908
909 static struct pipe_resource *
910 swr_resource_create(struct pipe_screen *_screen,
911 const struct pipe_resource *templat)
912 {
913 struct swr_screen *screen = swr_screen(_screen);
914 struct swr_resource *res = CALLOC_STRUCT(swr_resource);
915 if (!res)
916 return NULL;
917
918 res->base = *templat;
919 pipe_reference_init(&res->base.reference, 1);
920 res->base.screen = &screen->base;
921
922 if (swr_resource_is_texture(&res->base)) {
923 if (res->base.bind & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT
924 | PIPE_BIND_SHARED)) {
925 /* displayable surface
926 * first call swr_texture_layout without allocating to finish
927 * filling out the SWR_SURFACE_STATE in res */
928 swr_texture_layout(screen, res, false);
929 if (!swr_displaytarget_layout(screen, res))
930 goto fail;
931 } else {
932 /* texture map */
933 if (!swr_texture_layout(screen, res, true))
934 goto fail;
935 }
936
937 /* If resource was multisample, create resolve resource and attach
938 * it to multisample resource. */
939 if (!swr_create_resolve_resource(_screen, res))
940 goto fail;
941
942 } else {
943 /* other data (vertex buffer, const buffer, etc) */
944 assert(util_format_get_blocksize(templat->format) == 1);
945 assert(templat->height0 == 1);
946 assert(templat->depth0 == 1);
947 assert(templat->last_level == 0);
948
949 /* Easiest to just call swr_texture_layout, as it sets up
950 * SWR_SURFACE_STATE in res */
951 if (!swr_texture_layout(screen, res, true))
952 goto fail;
953 }
954
955 return &res->base;
956
957 fail:
958 FREE(res);
959 return NULL;
960 }
961
962 static void
963 swr_resource_destroy(struct pipe_screen *p_screen, struct pipe_resource *pt)
964 {
965 struct swr_screen *screen = swr_screen(p_screen);
966 struct swr_resource *spr = swr_resource(pt);
967
968 if (spr->display_target) {
969 /* If resource is display target, winsys manages the buffer and will
970 * free it on displaytarget_destroy. */
971 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
972
973 struct sw_winsys *winsys = screen->winsys;
974 winsys->displaytarget_destroy(winsys, spr->display_target);
975
976 if (spr->swr.numSamples > 1) {
977 /* Free an attached resolve resource */
978 struct swr_resource *alt = swr_resource(spr->resolve_target);
979 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
980
981 /* Free multisample buffer */
982 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
983 }
984 } else {
985 /* For regular resources, defer deletion */
986 swr_resource_unused(pt);
987
988 if (spr->swr.numSamples > 1) {
989 /* Free an attached resolve resource */
990 struct swr_resource *alt = swr_resource(spr->resolve_target);
991 swr_fence_work_free(screen->flush_fence, (void*)(alt->swr.xpBaseAddress), true);
992 }
993
994 swr_fence_work_free(screen->flush_fence, (void*)(spr->swr.xpBaseAddress), true);
995 swr_fence_work_free(screen->flush_fence,
996 (void*)(spr->secondary.xpBaseAddress), true);
997
998 /* If work queue grows too large, submit a fence to force queue to
999 * drain. This is mainly to decrease the amount of memory used by the
1000 * piglit streaming-texture-leak test */
1001 if (screen->pipe && swr_fence(screen->flush_fence)->work.count > 64)
1002 swr_fence_submit(swr_context(screen->pipe), screen->flush_fence);
1003 }
1004
1005 FREE(spr);
1006 }
1007
1008
1009 static void
1010 swr_flush_frontbuffer(struct pipe_screen *p_screen,
1011 struct pipe_resource *resource,
1012 unsigned level,
1013 unsigned layer,
1014 void *context_private,
1015 struct pipe_box *sub_box)
1016 {
1017 struct swr_screen *screen = swr_screen(p_screen);
1018 struct sw_winsys *winsys = screen->winsys;
1019 struct swr_resource *spr = swr_resource(resource);
1020 struct pipe_context *pipe = screen->pipe;
1021 struct swr_context *ctx = swr_context(pipe);
1022
1023 if (pipe) {
1024 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1025 swr_resource_unused(resource);
1026 ctx->api.pfnSwrEndFrame(ctx->swrContext);
1027 }
1028
1029 /* Multisample resolved into resolve_target at flush with store_resource */
1030 if (pipe && spr->swr.numSamples > 1) {
1031 struct pipe_resource *resolve_target = spr->resolve_target;
1032
1033 /* Once resolved, copy into display target */
1034 SWR_SURFACE_STATE *resolve = &swr_resource(resolve_target)->swr;
1035
1036 void *map = winsys->displaytarget_map(winsys, spr->display_target,
1037 PIPE_TRANSFER_WRITE);
1038 memcpy(map, (void*)(resolve->xpBaseAddress), resolve->pitch * resolve->height);
1039 winsys->displaytarget_unmap(winsys, spr->display_target);
1040 }
1041
1042 debug_assert(spr->display_target);
1043 if (spr->display_target)
1044 winsys->displaytarget_display(
1045 winsys, spr->display_target, context_private, sub_box);
1046 }
1047
1048
1049 static void
1050 swr_destroy_screen(struct pipe_screen *p_screen)
1051 {
1052 struct swr_screen *screen = swr_screen(p_screen);
1053 struct sw_winsys *winsys = screen->winsys;
1054
1055 fprintf(stderr, "SWR destroy screen!\n");
1056
1057 swr_fence_finish(p_screen, NULL, screen->flush_fence, 0);
1058 swr_fence_reference(p_screen, &screen->flush_fence, NULL);
1059
1060 JitDestroyContext(screen->hJitMgr);
1061 #if USE_SIMD16_SHADERS
1062 JitDestroyContext(screen->hJitMgr16);
1063 #endif
1064
1065 if (winsys->destroy)
1066 winsys->destroy(winsys);
1067
1068 FREE(screen);
1069 }
1070
1071
1072 static void
1073 swr_validate_env_options(struct swr_screen *screen)
1074 {
1075 /* The client_copy_limit sets a maximum on the amount of user-buffer memory
1076 * copied to scratch space on a draw. Past this, the draw will access
1077 * user-buffer directly and then block. This is faster than queuing many
1078 * large client draws. */
1079 screen->client_copy_limit = SWR_CLIENT_COPY_LIMIT;
1080 int client_copy_limit =
1081 debug_get_num_option("SWR_CLIENT_COPY_LIMIT", SWR_CLIENT_COPY_LIMIT);
1082 if (client_copy_limit > 0)
1083 screen->client_copy_limit = client_copy_limit;
1084
1085 /* XXX msaa under development, disable by default for now */
1086 screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */
1087
1088 /* validate env override values, within range and power of 2 */
1089 int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
1090 if (msaa_max_count != 1) {
1091 if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
1092 || !util_is_power_of_two(msaa_max_count)) {
1093 fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
1094 fprintf(stderr, "must be power of 2 between 1 and %d" \
1095 " (or 1 to disable msaa)\n",
1096 SWR_MAX_NUM_MULTISAMPLES);
1097 msaa_max_count = 1;
1098 }
1099
1100 fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
1101 if (msaa_max_count == 1)
1102 fprintf(stderr, "(msaa disabled)\n");
1103
1104 screen->msaa_max_count = msaa_max_count;
1105 }
1106
1107 screen->msaa_force_enable = debug_get_bool_option(
1108 "SWR_MSAA_FORCE_ENABLE", false);
1109 if (screen->msaa_force_enable)
1110 fprintf(stderr, "SWR_MSAA_FORCE_ENABLE: true\n");
1111 }
1112
1113
1114 PUBLIC
1115 struct pipe_screen *
1116 swr_create_screen_internal(struct sw_winsys *winsys)
1117 {
1118 struct swr_screen *screen = CALLOC_STRUCT(swr_screen);
1119
1120 if (!screen)
1121 return NULL;
1122
1123 if (!lp_build_init()) {
1124 FREE(screen);
1125 return NULL;
1126 }
1127
1128 screen->winsys = winsys;
1129 screen->base.get_name = swr_get_name;
1130 screen->base.get_vendor = swr_get_vendor;
1131 screen->base.is_format_supported = swr_is_format_supported;
1132 screen->base.context_create = swr_create_context;
1133 screen->base.can_create_resource = swr_can_create_resource;
1134
1135 screen->base.destroy = swr_destroy_screen;
1136 screen->base.get_param = swr_get_param;
1137 screen->base.get_shader_param = swr_get_shader_param;
1138 screen->base.get_paramf = swr_get_paramf;
1139
1140 screen->base.resource_create = swr_resource_create;
1141 screen->base.resource_destroy = swr_resource_destroy;
1142
1143 screen->base.flush_frontbuffer = swr_flush_frontbuffer;
1144
1145 // Pass in "" for architecture for run-time determination
1146 screen->hJitMgr = JitCreateContext(KNOB_SIMD_WIDTH, "", "swr");
1147 #if USE_SIMD16_SHADERS
1148 screen->hJitMgr16 = JitCreateContext(16, "", "swr");
1149 #endif
1150
1151 swr_fence_init(&screen->base);
1152
1153 swr_validate_env_options(screen);
1154
1155 return &screen->base;
1156 }
1157