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swr: Enable MSAA in OpenSWR software renderer
[mesa.git] / src / gallium / drivers / swr / swr_state.cpp
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 // llvm redefines DEBUG
25 #pragma push_macro("DEBUG")
26 #undef DEBUG
27 #include "JitManager.h"
28 #pragma pop_macro("DEBUG")
29
30 #include "common/os.h"
31 #include "jit_api.h"
32 #include "gen_state_llvm.h"
33 #include "core/multisample.h"
34
35 #include "gallivm/lp_bld_tgsi.h"
36 #include "util/u_format.h"
37
38 #include "util/u_memory.h"
39 #include "util/u_inlines.h"
40 #include "util/u_helpers.h"
41 #include "util/u_framebuffer.h"
42 #include "util/u_viewport.h"
43
44 #include "swr_state.h"
45 #include "swr_context.h"
46 #include "gen_swr_context_llvm.h"
47 #include "swr_screen.h"
48 #include "swr_resource.h"
49 #include "swr_tex_sample.h"
50 #include "swr_scratch.h"
51 #include "swr_shader.h"
52 #include "swr_fence.h"
53
54 /* These should be pulled out into separate files as necessary
55 * Just initializing everything here to get going. */
56
57 static void *
58 swr_create_blend_state(struct pipe_context *pipe,
59 const struct pipe_blend_state *blend)
60 {
61 struct swr_blend_state *state = CALLOC_STRUCT(swr_blend_state);
62
63 memcpy(&state->pipe, blend, sizeof(*blend));
64
65 struct pipe_blend_state *pipe_blend = &state->pipe;
66
67 for (int target = 0;
68 target < std::min(SWR_NUM_RENDERTARGETS, PIPE_MAX_COLOR_BUFS);
69 target++) {
70
71 struct pipe_rt_blend_state *rt_blend = &pipe_blend->rt[target];
72 SWR_RENDER_TARGET_BLEND_STATE &blendState =
73 state->blendState.renderTarget[target];
74 RENDER_TARGET_BLEND_COMPILE_STATE &compileState =
75 state->compileState[target];
76
77 if (target != 0 && !pipe_blend->independent_blend_enable) {
78 memcpy(&compileState,
79 &state->compileState[0],
80 sizeof(RENDER_TARGET_BLEND_COMPILE_STATE));
81 continue;
82 }
83
84 compileState.blendEnable = rt_blend->blend_enable;
85 if (compileState.blendEnable) {
86 compileState.sourceAlphaBlendFactor =
87 swr_convert_blend_factor(rt_blend->alpha_src_factor);
88 compileState.destAlphaBlendFactor =
89 swr_convert_blend_factor(rt_blend->alpha_dst_factor);
90 compileState.sourceBlendFactor =
91 swr_convert_blend_factor(rt_blend->rgb_src_factor);
92 compileState.destBlendFactor =
93 swr_convert_blend_factor(rt_blend->rgb_dst_factor);
94
95 compileState.colorBlendFunc =
96 swr_convert_blend_func(rt_blend->rgb_func);
97 compileState.alphaBlendFunc =
98 swr_convert_blend_func(rt_blend->alpha_func);
99 }
100 compileState.logicOpEnable = state->pipe.logicop_enable;
101 if (compileState.logicOpEnable) {
102 compileState.logicOpFunc =
103 swr_convert_logic_op(state->pipe.logicop_func);
104 }
105
106 blendState.writeDisableRed =
107 (rt_blend->colormask & PIPE_MASK_R) ? 0 : 1;
108 blendState.writeDisableGreen =
109 (rt_blend->colormask & PIPE_MASK_G) ? 0 : 1;
110 blendState.writeDisableBlue =
111 (rt_blend->colormask & PIPE_MASK_B) ? 0 : 1;
112 blendState.writeDisableAlpha =
113 (rt_blend->colormask & PIPE_MASK_A) ? 0 : 1;
114
115 if (rt_blend->colormask == 0)
116 compileState.blendEnable = false;
117 }
118
119 return state;
120 }
121
122 static void
123 swr_bind_blend_state(struct pipe_context *pipe, void *blend)
124 {
125 struct swr_context *ctx = swr_context(pipe);
126
127 if (ctx->blend == blend)
128 return;
129
130 ctx->blend = (swr_blend_state *)blend;
131
132 ctx->dirty |= SWR_NEW_BLEND;
133 }
134
135 static void
136 swr_delete_blend_state(struct pipe_context *pipe, void *blend)
137 {
138 FREE(blend);
139 }
140
141 static void
142 swr_set_blend_color(struct pipe_context *pipe,
143 const struct pipe_blend_color *color)
144 {
145 struct swr_context *ctx = swr_context(pipe);
146
147 ctx->blend_color = *color;
148
149 ctx->dirty |= SWR_NEW_BLEND;
150 }
151
152 static void
153 swr_set_stencil_ref(struct pipe_context *pipe,
154 const struct pipe_stencil_ref *ref)
155 {
156 struct swr_context *ctx = swr_context(pipe);
157
158 ctx->stencil_ref = *ref;
159
160 ctx->dirty |= SWR_NEW_DEPTH_STENCIL_ALPHA;
161 }
162
163 static void *
164 swr_create_depth_stencil_state(
165 struct pipe_context *pipe,
166 const struct pipe_depth_stencil_alpha_state *depth_stencil)
167 {
168 struct pipe_depth_stencil_alpha_state *state;
169
170 state = (pipe_depth_stencil_alpha_state *)mem_dup(depth_stencil,
171 sizeof *depth_stencil);
172
173 return state;
174 }
175
176 static void
177 swr_bind_depth_stencil_state(struct pipe_context *pipe, void *depth_stencil)
178 {
179 struct swr_context *ctx = swr_context(pipe);
180
181 if (ctx->depth_stencil == (pipe_depth_stencil_alpha_state *)depth_stencil)
182 return;
183
184 ctx->depth_stencil = (pipe_depth_stencil_alpha_state *)depth_stencil;
185
186 ctx->dirty |= SWR_NEW_DEPTH_STENCIL_ALPHA;
187 }
188
189 static void
190 swr_delete_depth_stencil_state(struct pipe_context *pipe, void *depth)
191 {
192 FREE(depth);
193 }
194
195
196 static void *
197 swr_create_rasterizer_state(struct pipe_context *pipe,
198 const struct pipe_rasterizer_state *rast)
199 {
200 struct pipe_rasterizer_state *state;
201 state = (pipe_rasterizer_state *)mem_dup(rast, sizeof *rast);
202
203 return state;
204 }
205
206 static void
207 swr_bind_rasterizer_state(struct pipe_context *pipe, void *handle)
208 {
209 struct swr_context *ctx = swr_context(pipe);
210 const struct pipe_rasterizer_state *rasterizer =
211 (const struct pipe_rasterizer_state *)handle;
212
213 if (ctx->rasterizer == (pipe_rasterizer_state *)rasterizer)
214 return;
215
216 ctx->rasterizer = (pipe_rasterizer_state *)rasterizer;
217
218 ctx->dirty |= SWR_NEW_RASTERIZER;
219 }
220
221 static void
222 swr_delete_rasterizer_state(struct pipe_context *pipe, void *rasterizer)
223 {
224 FREE(rasterizer);
225 }
226
227
228 static void *
229 swr_create_sampler_state(struct pipe_context *pipe,
230 const struct pipe_sampler_state *sampler)
231 {
232 struct pipe_sampler_state *state =
233 (pipe_sampler_state *)mem_dup(sampler, sizeof *sampler);
234
235 return state;
236 }
237
238 static void
239 swr_bind_sampler_states(struct pipe_context *pipe,
240 enum pipe_shader_type shader,
241 unsigned start,
242 unsigned num,
243 void **samplers)
244 {
245 struct swr_context *ctx = swr_context(pipe);
246 unsigned i;
247
248 assert(shader < PIPE_SHADER_TYPES);
249 assert(start + num <= ARRAY_SIZE(ctx->samplers[shader]));
250
251 /* set the new samplers */
252 ctx->num_samplers[shader] = num;
253 for (i = 0; i < num; i++) {
254 ctx->samplers[shader][start + i] = (pipe_sampler_state *)samplers[i];
255 }
256
257 ctx->dirty |= SWR_NEW_SAMPLER;
258 }
259
260 static void
261 swr_delete_sampler_state(struct pipe_context *pipe, void *sampler)
262 {
263 FREE(sampler);
264 }
265
266
267 static struct pipe_sampler_view *
268 swr_create_sampler_view(struct pipe_context *pipe,
269 struct pipe_resource *texture,
270 const struct pipe_sampler_view *templ)
271 {
272 struct pipe_sampler_view *view = CALLOC_STRUCT(pipe_sampler_view);
273
274 if (view) {
275 *view = *templ;
276 view->reference.count = 1;
277 view->texture = NULL;
278 pipe_resource_reference(&view->texture, texture);
279 view->context = pipe;
280 }
281
282 return view;
283 }
284
285 static void
286 swr_set_sampler_views(struct pipe_context *pipe,
287 enum pipe_shader_type shader,
288 unsigned start,
289 unsigned num,
290 struct pipe_sampler_view **views)
291 {
292 struct swr_context *ctx = swr_context(pipe);
293 uint i;
294
295 assert(num <= PIPE_MAX_SHADER_SAMPLER_VIEWS);
296
297 assert(shader < PIPE_SHADER_TYPES);
298 assert(start + num <= ARRAY_SIZE(ctx->sampler_views[shader]));
299
300 /* set the new sampler views */
301 ctx->num_sampler_views[shader] = num;
302 for (i = 0; i < num; i++) {
303 /* Note: we're using pipe_sampler_view_release() here to work around
304 * a possible crash when the old view belongs to another context that
305 * was already destroyed.
306 */
307 pipe_sampler_view_release(pipe, &ctx->sampler_views[shader][start + i]);
308 pipe_sampler_view_reference(&ctx->sampler_views[shader][start + i],
309 views[i]);
310 }
311
312 ctx->dirty |= SWR_NEW_SAMPLER_VIEW;
313 }
314
315 static void
316 swr_sampler_view_destroy(struct pipe_context *pipe,
317 struct pipe_sampler_view *view)
318 {
319 pipe_resource_reference(&view->texture, NULL);
320 FREE(view);
321 }
322
323 static void *
324 swr_create_vs_state(struct pipe_context *pipe,
325 const struct pipe_shader_state *vs)
326 {
327 struct swr_vertex_shader *swr_vs = new swr_vertex_shader;
328 if (!swr_vs)
329 return NULL;
330
331 swr_vs->pipe.tokens = tgsi_dup_tokens(vs->tokens);
332 swr_vs->pipe.stream_output = vs->stream_output;
333
334 lp_build_tgsi_info(vs->tokens, &swr_vs->info);
335
336 swr_vs->soState = {0};
337
338 if (swr_vs->pipe.stream_output.num_outputs) {
339 pipe_stream_output_info *stream_output = &swr_vs->pipe.stream_output;
340
341 swr_vs->soState.soEnable = true;
342 // soState.rasterizerDisable set on state dirty
343 // soState.streamToRasterizer not used
344
345 for (uint32_t i = 0; i < stream_output->num_outputs; i++) {
346 swr_vs->soState.streamMasks[stream_output->output[i].stream] |=
347 1 << (stream_output->output[i].register_index - 1);
348 }
349 for (uint32_t i = 0; i < MAX_SO_STREAMS; i++) {
350 swr_vs->soState.streamNumEntries[i] =
351 _mm_popcnt_u32(swr_vs->soState.streamMasks[i]);
352 }
353 }
354
355 return swr_vs;
356 }
357
358 static void
359 swr_bind_vs_state(struct pipe_context *pipe, void *vs)
360 {
361 struct swr_context *ctx = swr_context(pipe);
362
363 if (ctx->vs == vs)
364 return;
365
366 ctx->vs = (swr_vertex_shader *)vs;
367 ctx->dirty |= SWR_NEW_VS;
368 }
369
370 static void
371 swr_delete_vs_state(struct pipe_context *pipe, void *vs)
372 {
373 struct swr_vertex_shader *swr_vs = (swr_vertex_shader *)vs;
374 FREE((void *)swr_vs->pipe.tokens);
375 struct swr_screen *screen = swr_screen(pipe->screen);
376
377 /* Defer deletion of vs state */
378 swr_fence_work_delete_vs(screen->flush_fence, swr_vs);
379 }
380
381 static void *
382 swr_create_fs_state(struct pipe_context *pipe,
383 const struct pipe_shader_state *fs)
384 {
385 struct swr_fragment_shader *swr_fs = new swr_fragment_shader;
386 if (!swr_fs)
387 return NULL;
388
389 swr_fs->pipe.tokens = tgsi_dup_tokens(fs->tokens);
390
391 lp_build_tgsi_info(fs->tokens, &swr_fs->info);
392
393 return swr_fs;
394 }
395
396
397 static void
398 swr_bind_fs_state(struct pipe_context *pipe, void *fs)
399 {
400 struct swr_context *ctx = swr_context(pipe);
401
402 if (ctx->fs == fs)
403 return;
404
405 ctx->fs = (swr_fragment_shader *)fs;
406 ctx->dirty |= SWR_NEW_FS;
407 }
408
409 static void
410 swr_delete_fs_state(struct pipe_context *pipe, void *fs)
411 {
412 struct swr_fragment_shader *swr_fs = (swr_fragment_shader *)fs;
413 FREE((void *)swr_fs->pipe.tokens);
414 struct swr_screen *screen = swr_screen(pipe->screen);
415
416 /* Defer deleton of fs state */
417 swr_fence_work_delete_fs(screen->flush_fence, swr_fs);
418 }
419
420 static void *
421 swr_create_gs_state(struct pipe_context *pipe,
422 const struct pipe_shader_state *gs)
423 {
424 struct swr_geometry_shader *swr_gs = new swr_geometry_shader;
425 if (!swr_gs)
426 return NULL;
427
428 swr_gs->pipe.tokens = tgsi_dup_tokens(gs->tokens);
429
430 lp_build_tgsi_info(gs->tokens, &swr_gs->info);
431
432 return swr_gs;
433 }
434
435
436 static void
437 swr_bind_gs_state(struct pipe_context *pipe, void *gs)
438 {
439 struct swr_context *ctx = swr_context(pipe);
440
441 if (ctx->gs == gs)
442 return;
443
444 ctx->gs = (swr_geometry_shader *)gs;
445 ctx->dirty |= SWR_NEW_GS;
446 }
447
448 static void
449 swr_delete_gs_state(struct pipe_context *pipe, void *gs)
450 {
451 struct swr_geometry_shader *swr_gs = (swr_geometry_shader *)gs;
452 FREE((void *)swr_gs->pipe.tokens);
453 struct swr_screen *screen = swr_screen(pipe->screen);
454
455 /* Defer deleton of fs state */
456 swr_fence_work_delete_gs(screen->flush_fence, swr_gs);
457 }
458
459 static void
460 swr_set_constant_buffer(struct pipe_context *pipe,
461 enum pipe_shader_type shader,
462 uint index,
463 const struct pipe_constant_buffer *cb)
464 {
465 struct swr_context *ctx = swr_context(pipe);
466 struct pipe_resource *constants = cb ? cb->buffer : NULL;
467
468 assert(shader < PIPE_SHADER_TYPES);
469 assert(index < ARRAY_SIZE(ctx->constants[shader]));
470
471 /* note: reference counting */
472 util_copy_constant_buffer(&ctx->constants[shader][index], cb);
473
474 if (shader == PIPE_SHADER_VERTEX) {
475 ctx->dirty |= SWR_NEW_VSCONSTANTS;
476 } else if (shader == PIPE_SHADER_FRAGMENT) {
477 ctx->dirty |= SWR_NEW_FSCONSTANTS;
478 } else if (shader == PIPE_SHADER_GEOMETRY) {
479 ctx->dirty |= SWR_NEW_GSCONSTANTS;
480 }
481
482 if (cb && cb->user_buffer) {
483 pipe_resource_reference(&constants, NULL);
484 }
485 }
486
487
488 static void *
489 swr_create_vertex_elements_state(struct pipe_context *pipe,
490 unsigned num_elements,
491 const struct pipe_vertex_element *attribs)
492 {
493 struct swr_vertex_element_state *velems;
494 assert(num_elements <= PIPE_MAX_ATTRIBS);
495 velems = new swr_vertex_element_state;
496 if (velems) {
497 velems->fsState.bVertexIDOffsetEnable = true;
498 velems->fsState.numAttribs = num_elements;
499 for (unsigned i = 0; i < num_elements; i++) {
500 // XXX: we should do this keyed on the VS usage info
501
502 const struct util_format_description *desc =
503 util_format_description(attribs[i].src_format);
504
505 velems->fsState.layout[i].AlignedByteOffset = attribs[i].src_offset;
506 velems->fsState.layout[i].Format =
507 mesa_to_swr_format(attribs[i].src_format);
508 velems->fsState.layout[i].StreamIndex =
509 attribs[i].vertex_buffer_index;
510 velems->fsState.layout[i].InstanceEnable =
511 attribs[i].instance_divisor != 0;
512 velems->fsState.layout[i].ComponentControl0 =
513 desc->channel[0].type != UTIL_FORMAT_TYPE_VOID
514 ? ComponentControl::StoreSrc
515 : ComponentControl::Store0;
516 velems->fsState.layout[i].ComponentControl1 =
517 desc->channel[1].type != UTIL_FORMAT_TYPE_VOID
518 ? ComponentControl::StoreSrc
519 : ComponentControl::Store0;
520 velems->fsState.layout[i].ComponentControl2 =
521 desc->channel[2].type != UTIL_FORMAT_TYPE_VOID
522 ? ComponentControl::StoreSrc
523 : ComponentControl::Store0;
524 velems->fsState.layout[i].ComponentControl3 =
525 desc->channel[3].type != UTIL_FORMAT_TYPE_VOID
526 ? ComponentControl::StoreSrc
527 : ComponentControl::Store1Fp;
528 velems->fsState.layout[i].ComponentPacking = ComponentEnable::XYZW;
529 velems->fsState.layout[i].InstanceDataStepRate =
530 attribs[i].instance_divisor;
531
532 /* Calculate the pitch of each stream */
533 const SWR_FORMAT_INFO &swr_desc = GetFormatInfo(
534 mesa_to_swr_format(attribs[i].src_format));
535 velems->stream_pitch[attribs[i].vertex_buffer_index] += swr_desc.Bpp;
536
537 if (attribs[i].instance_divisor != 0) {
538 velems->instanced_bufs |= 1U << attribs[i].vertex_buffer_index;
539 uint32_t *min_instance_div =
540 &velems->min_instance_div[attribs[i].vertex_buffer_index];
541 if (!*min_instance_div ||
542 attribs[i].instance_divisor < *min_instance_div)
543 *min_instance_div = attribs[i].instance_divisor;
544 }
545 }
546 }
547
548 return velems;
549 }
550
551 static void
552 swr_bind_vertex_elements_state(struct pipe_context *pipe, void *velems)
553 {
554 struct swr_context *ctx = swr_context(pipe);
555 struct swr_vertex_element_state *swr_velems =
556 (struct swr_vertex_element_state *)velems;
557
558 ctx->velems = swr_velems;
559 ctx->dirty |= SWR_NEW_VERTEX;
560 }
561
562 static void
563 swr_delete_vertex_elements_state(struct pipe_context *pipe, void *velems)
564 {
565 struct swr_vertex_element_state *swr_velems =
566 (struct swr_vertex_element_state *) velems;
567 /* XXX Need to destroy fetch shader? */
568 delete swr_velems;
569 }
570
571
572 static void
573 swr_set_vertex_buffers(struct pipe_context *pipe,
574 unsigned start_slot,
575 unsigned num_elements,
576 const struct pipe_vertex_buffer *buffers)
577 {
578 struct swr_context *ctx = swr_context(pipe);
579
580 assert(num_elements <= PIPE_MAX_ATTRIBS);
581
582 util_set_vertex_buffers_count(ctx->vertex_buffer,
583 &ctx->num_vertex_buffers,
584 buffers,
585 start_slot,
586 num_elements);
587
588 ctx->dirty |= SWR_NEW_VERTEX;
589 }
590
591
592 static void
593 swr_set_index_buffer(struct pipe_context *pipe,
594 const struct pipe_index_buffer *ib)
595 {
596 struct swr_context *ctx = swr_context(pipe);
597
598 if (ib)
599 memcpy(&ctx->index_buffer, ib, sizeof(ctx->index_buffer));
600 else
601 memset(&ctx->index_buffer, 0, sizeof(ctx->index_buffer));
602
603 ctx->dirty |= SWR_NEW_VERTEX;
604 }
605
606 static void
607 swr_set_polygon_stipple(struct pipe_context *pipe,
608 const struct pipe_poly_stipple *stipple)
609 {
610 struct swr_context *ctx = swr_context(pipe);
611
612 ctx->poly_stipple = *stipple; /* struct copy */
613 ctx->dirty |= SWR_NEW_STIPPLE;
614 }
615
616 static void
617 swr_set_clip_state(struct pipe_context *pipe,
618 const struct pipe_clip_state *clip)
619 {
620 struct swr_context *ctx = swr_context(pipe);
621
622 ctx->clip = *clip;
623 /* XXX Unimplemented, but prevents crash */
624
625 ctx->dirty |= SWR_NEW_CLIP;
626 }
627
628
629 static void
630 swr_set_scissor_states(struct pipe_context *pipe,
631 unsigned start_slot,
632 unsigned num_viewports,
633 const struct pipe_scissor_state *scissor)
634 {
635 struct swr_context *ctx = swr_context(pipe);
636
637 ctx->scissor = *scissor;
638 ctx->swr_scissor.xmin = scissor->minx;
639 ctx->swr_scissor.xmax = scissor->maxx;
640 ctx->swr_scissor.ymin = scissor->miny;
641 ctx->swr_scissor.ymax = scissor->maxy;
642 ctx->dirty |= SWR_NEW_SCISSOR;
643 }
644
645 static void
646 swr_set_viewport_states(struct pipe_context *pipe,
647 unsigned start_slot,
648 unsigned num_viewports,
649 const struct pipe_viewport_state *vpt)
650 {
651 struct swr_context *ctx = swr_context(pipe);
652
653 ctx->viewport = *vpt;
654 ctx->dirty |= SWR_NEW_VIEWPORT;
655 }
656
657
658 static void
659 swr_set_framebuffer_state(struct pipe_context *pipe,
660 const struct pipe_framebuffer_state *fb)
661 {
662 struct swr_context *ctx = swr_context(pipe);
663
664 boolean changed = !util_framebuffer_state_equal(&ctx->framebuffer, fb);
665
666 assert(fb->width <= KNOB_GUARDBAND_WIDTH);
667 assert(fb->height <= KNOB_GUARDBAND_HEIGHT);
668
669 if (changed) {
670 util_copy_framebuffer_state(&ctx->framebuffer, fb);
671
672 /* 0 and 1 both indicate no msaa. Core doesn't understand 0 samples */
673 ctx->framebuffer.samples = std::max((ubyte)1, ctx->framebuffer.samples);
674
675 ctx->dirty |= SWR_NEW_FRAMEBUFFER;
676 }
677 }
678
679
680 static void
681 swr_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
682 {
683 struct swr_context *ctx = swr_context(pipe);
684
685 if (sample_mask != ctx->sample_mask) {
686 ctx->sample_mask = sample_mask;
687 ctx->dirty |= SWR_NEW_RASTERIZER;
688 }
689 }
690
691 /*
692 * MSAA fixed sample position table
693 * used by update_derived and get_sample_position
694 * (integer locations on a 16x16 grid)
695 */
696 static const uint8_t swr_sample_positions[][2] =
697 { /* 1x*/ { 8, 8},
698 /* 2x*/ {12,12},{ 4, 4},
699 /* 4x*/ { 6, 2},{14, 6},{ 2,10},{10,14},
700 /* 8x*/ { 9, 5},{ 7,11},{13, 9},{ 5, 3},
701 { 3,13},{ 1, 7},{11,15},{15, 1},
702 /*16x*/ { 9, 9},{ 7, 5},{ 5,10},{12, 7},
703 { 3, 6},{10,13},{13,11},{11, 3},
704 { 6,14},{ 8, 1},{ 4, 2},{ 2,12},
705 { 0, 8},{15, 4},{14,15},{ 1, 0} };
706
707 static void
708 swr_get_sample_position(struct pipe_context *pipe,
709 unsigned sample_count, unsigned sample_index,
710 float *out_value)
711 {
712 /* validate sample_count */
713 sample_count = GetNumSamples(GetSampleCount(sample_count));
714
715 const uint8_t *sample = swr_sample_positions[sample_count-1 + sample_index];
716 out_value[0] = sample[0] / 16.0f;
717 out_value[1] = sample[1] / 16.0f;
718 }
719
720
721 /*
722 * Update resource in-use status
723 * All resources bound to color or depth targets marked as WRITE resources.
724 * VBO Vertex/index buffers and texture views marked as READ resources.
725 */
726 void
727 swr_update_resource_status(struct pipe_context *pipe,
728 const struct pipe_draw_info *p_draw_info)
729 {
730 struct swr_context *ctx = swr_context(pipe);
731 struct pipe_framebuffer_state *fb = &ctx->framebuffer;
732
733 /* colorbuffer targets */
734 if (fb->nr_cbufs)
735 for (uint32_t i = 0; i < fb->nr_cbufs; ++i)
736 if (fb->cbufs[i])
737 swr_resource_write(fb->cbufs[i]->texture);
738
739 /* depth/stencil target */
740 if (fb->zsbuf)
741 swr_resource_write(fb->zsbuf->texture);
742
743 /* VBO vertex buffers */
744 for (uint32_t i = 0; i < ctx->num_vertex_buffers; i++) {
745 struct pipe_vertex_buffer *vb = &ctx->vertex_buffer[i];
746 if (!vb->user_buffer)
747 swr_resource_read(vb->buffer);
748 }
749
750 /* VBO index buffer */
751 if (p_draw_info && p_draw_info->indexed) {
752 struct pipe_index_buffer *ib = &ctx->index_buffer;
753 if (!ib->user_buffer)
754 swr_resource_read(ib->buffer);
755 }
756
757 /* transform feedback buffers */
758 for (uint32_t i = 0; i < ctx->num_so_targets; i++) {
759 struct pipe_stream_output_target *target = ctx->so_targets[i];
760 if (target && target->buffer)
761 swr_resource_write(target->buffer);
762 }
763
764 /* texture sampler views */
765 for (uint32_t j : {PIPE_SHADER_VERTEX, PIPE_SHADER_FRAGMENT}) {
766 for (uint32_t i = 0; i < ctx->num_sampler_views[j]; i++) {
767 struct pipe_sampler_view *view = ctx->sampler_views[j][i];
768 if (view)
769 swr_resource_read(view->texture);
770 }
771 }
772
773 /* constant buffers */
774 for (uint32_t j : {PIPE_SHADER_VERTEX, PIPE_SHADER_FRAGMENT}) {
775 for (uint32_t i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
776 struct pipe_constant_buffer *cb = &ctx->constants[j][i];
777 if (cb->buffer)
778 swr_resource_read(cb->buffer);
779 }
780 }
781 }
782
783 static void
784 swr_update_texture_state(struct swr_context *ctx,
785 enum pipe_shader_type shader_type,
786 unsigned num_sampler_views,
787 swr_jit_texture *textures)
788 {
789 for (unsigned i = 0; i < num_sampler_views; i++) {
790 struct pipe_sampler_view *view =
791 ctx->sampler_views[shader_type][i];
792 struct swr_jit_texture *jit_tex = &textures[i];
793
794 memset(jit_tex, 0, sizeof(*jit_tex));
795 if (view) {
796 struct pipe_resource *res = view->texture;
797 struct swr_resource *swr_res = swr_resource(res);
798 SWR_SURFACE_STATE *swr = &swr_res->swr;
799 size_t *mip_offsets = swr_res->mip_offsets;
800 if (swr_res->has_depth && swr_res->has_stencil &&
801 !util_format_has_depth(util_format_description(view->format))) {
802 swr = &swr_res->secondary;
803 mip_offsets = swr_res->secondary_mip_offsets;
804 }
805
806 jit_tex->width = res->width0;
807 jit_tex->height = res->height0;
808 jit_tex->base_ptr = swr->pBaseAddress;
809 if (view->target != PIPE_BUFFER) {
810 jit_tex->first_level = view->u.tex.first_level;
811 jit_tex->last_level = view->u.tex.last_level;
812 if (view->target == PIPE_TEXTURE_3D)
813 jit_tex->depth = res->depth0;
814 else
815 jit_tex->depth =
816 view->u.tex.last_layer - view->u.tex.first_layer + 1;
817 jit_tex->base_ptr += view->u.tex.first_layer *
818 swr->qpitch * swr->pitch;
819 } else {
820 unsigned view_blocksize = util_format_get_blocksize(view->format);
821 jit_tex->base_ptr += view->u.buf.offset;
822 jit_tex->width = view->u.buf.size / view_blocksize;
823 jit_tex->depth = 1;
824 }
825
826 for (unsigned level = jit_tex->first_level;
827 level <= jit_tex->last_level;
828 level++) {
829 jit_tex->row_stride[level] = swr->pitch;
830 jit_tex->img_stride[level] = swr->qpitch * swr->pitch;
831 jit_tex->mip_offsets[level] = mip_offsets[level];
832 }
833 }
834 }
835 }
836
837 static void
838 swr_update_sampler_state(struct swr_context *ctx,
839 enum pipe_shader_type shader_type,
840 unsigned num_samplers,
841 swr_jit_sampler *samplers)
842 {
843 for (unsigned i = 0; i < num_samplers; i++) {
844 const struct pipe_sampler_state *sampler =
845 ctx->samplers[shader_type][i];
846
847 if (sampler) {
848 samplers[i].min_lod = sampler->min_lod;
849 samplers[i].max_lod = sampler->max_lod;
850 samplers[i].lod_bias = sampler->lod_bias;
851 COPY_4V(samplers[i].border_color, sampler->border_color.f);
852 }
853 }
854 }
855
856 static void
857 swr_update_constants(struct swr_context *ctx, enum pipe_shader_type shaderType)
858 {
859 swr_draw_context *pDC = &ctx->swrDC;
860
861 const float **constant;
862 uint32_t *num_constants;
863 struct swr_scratch_space *scratch;
864
865 switch (shaderType) {
866 case PIPE_SHADER_VERTEX:
867 constant = pDC->constantVS;
868 num_constants = pDC->num_constantsVS;
869 scratch = &ctx->scratch->vs_constants;
870 break;
871 case PIPE_SHADER_FRAGMENT:
872 constant = pDC->constantFS;
873 num_constants = pDC->num_constantsFS;
874 scratch = &ctx->scratch->fs_constants;
875 break;
876 case PIPE_SHADER_GEOMETRY:
877 constant = pDC->constantGS;
878 num_constants = pDC->num_constantsGS;
879 scratch = &ctx->scratch->gs_constants;
880 break;
881 default:
882 debug_printf("Unsupported shader type constants\n");
883 return;
884 }
885
886 for (UINT i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
887 const pipe_constant_buffer *cb = &ctx->constants[shaderType][i];
888 num_constants[i] = cb->buffer_size;
889 if (cb->buffer) {
890 constant[i] =
891 (const float *)(swr_resource_data(cb->buffer) +
892 cb->buffer_offset);
893 } else {
894 /* Need to copy these constants to scratch space */
895 if (cb->user_buffer && cb->buffer_size) {
896 const void *ptr =
897 ((const uint8_t *)cb->user_buffer + cb->buffer_offset);
898 uint32_t size = AlignUp(cb->buffer_size, 4);
899 ptr = swr_copy_to_scratch_space(ctx, scratch, ptr, size);
900 constant[i] = (const float *)ptr;
901 }
902 }
903 }
904 }
905
906 static bool
907 swr_change_rt(struct swr_context *ctx,
908 unsigned attachment,
909 const struct pipe_surface *sf)
910 {
911 swr_draw_context *pDC = &ctx->swrDC;
912 struct SWR_SURFACE_STATE *rt = &pDC->renderTargets[attachment];
913
914 /* Do nothing if the render target hasn't changed */
915 if ((!sf || !sf->texture) && rt->pBaseAddress == nullptr)
916 return false;
917
918 /* Deal with disabling RT up front */
919 if (!sf || !sf->texture) {
920 /* If detaching attachment, mark tiles as RESOLVED so core
921 * won't try to load from non-existent target. */
922 swr_store_render_target(&ctx->pipe, attachment, SWR_TILE_RESOLVED);
923 *rt = {0};
924 return true;
925 }
926
927 const struct swr_resource *swr = swr_resource(sf->texture);
928 const SWR_SURFACE_STATE *swr_surface = &swr->swr;
929 SWR_FORMAT fmt = mesa_to_swr_format(sf->format);
930
931 if (attachment == SWR_ATTACHMENT_STENCIL && swr->secondary.pBaseAddress) {
932 swr_surface = &swr->secondary;
933 fmt = swr_surface->format;
934 }
935
936 if (rt->pBaseAddress == swr_surface->pBaseAddress &&
937 rt->format == fmt &&
938 rt->lod == sf->u.tex.level &&
939 rt->arrayIndex == sf->u.tex.first_layer)
940 return false;
941
942 bool need_fence = false;
943
944 /* StoreTile for changed target */
945 if (rt->pBaseAddress) {
946 /* If changing attachment to a new target, mark tiles as
947 * INVALID so they are reloaded from surface. */
948 swr_store_render_target(&ctx->pipe, attachment, SWR_TILE_INVALID);
949 need_fence = true;
950 }
951
952 /* Make new attachment */
953 *rt = *swr_surface;
954 rt->format = fmt;
955 rt->lod = sf->u.tex.level;
956 rt->arrayIndex = sf->u.tex.first_layer;
957
958 return need_fence;
959 }
960
961 static inline void
962 swr_user_vbuf_range(const struct pipe_draw_info *info,
963 const struct swr_vertex_element_state *velems,
964 const struct pipe_vertex_buffer *vb,
965 uint32_t i,
966 uint32_t *totelems,
967 uint32_t *base,
968 uint32_t *size)
969 {
970 /* FIXME: The size is too large - we don't access the full extra stride. */
971 unsigned elems;
972 if (velems->instanced_bufs & (1U << i)) {
973 elems = info->instance_count / velems->min_instance_div[i] + 1;
974 *totelems = info->start_instance + elems;
975 *base = info->start_instance * vb->stride;
976 *size = elems * vb->stride;
977 } else if (vb->stride) {
978 elems = info->max_index - info->min_index + 1;
979 *totelems = info->max_index + 1;
980 *base = info->min_index * vb->stride;
981 *size = elems * vb->stride;
982 } else {
983 *totelems = 1;
984 *base = 0;
985 *size = velems->stream_pitch[i];
986 }
987 }
988
989 void
990 swr_update_derived(struct pipe_context *pipe,
991 const struct pipe_draw_info *p_draw_info)
992 {
993 struct swr_context *ctx = swr_context(pipe);
994 struct swr_screen *screen = swr_screen(pipe->screen);
995
996 /* When called from swr_clear (p_draw_info = null), set any null
997 * state-objects to the dummy state objects to prevent nullptr dereference
998 * in validation below.
999 *
1000 * Important that this remains static for zero initialization. These
1001 * aren't meant to be proper state objects, just empty structs. They will
1002 * not be written to.
1003 *
1004 * Shaders can't be part of the union since they contain std::unordered_map
1005 */
1006 static struct {
1007 union {
1008 struct pipe_rasterizer_state rasterizer;
1009 struct pipe_depth_stencil_alpha_state depth_stencil;
1010 struct swr_blend_state blend;
1011 } state;
1012 struct swr_vertex_shader vs;
1013 struct swr_fragment_shader fs;
1014 } swr_dummy;
1015
1016 if (!p_draw_info) {
1017 if (!ctx->rasterizer)
1018 ctx->rasterizer = &swr_dummy.state.rasterizer;
1019 if (!ctx->depth_stencil)
1020 ctx->depth_stencil = &swr_dummy.state.depth_stencil;
1021 if (!ctx->blend)
1022 ctx->blend = &swr_dummy.state.blend;
1023 if (!ctx->vs)
1024 ctx->vs = &swr_dummy.vs;
1025 if (!ctx->fs)
1026 ctx->fs = &swr_dummy.fs;
1027 }
1028
1029 /* Update screen->pipe to current pipe context. */
1030 if (screen->pipe != pipe)
1031 screen->pipe = pipe;
1032
1033 /* Any state that requires dirty flags to be re-triggered sets this mask */
1034 /* For example, user_buffer vertex and index buffers. */
1035 unsigned post_update_dirty_flags = 0;
1036
1037 /* Render Targets */
1038 if (ctx->dirty & SWR_NEW_FRAMEBUFFER) {
1039 struct pipe_framebuffer_state *fb = &ctx->framebuffer;
1040 const struct util_format_description *desc = NULL;
1041 bool need_fence = false;
1042
1043 /* colorbuffer targets */
1044 if (fb->nr_cbufs) {
1045 for (unsigned i = 0; i < fb->nr_cbufs; ++i)
1046 need_fence |= swr_change_rt(
1047 ctx, SWR_ATTACHMENT_COLOR0 + i, fb->cbufs[i]);
1048 }
1049 for (unsigned i = fb->nr_cbufs; i < SWR_NUM_RENDERTARGETS; ++i)
1050 need_fence |= swr_change_rt(ctx, SWR_ATTACHMENT_COLOR0 + i, NULL);
1051
1052 /* depth/stencil target */
1053 if (fb->zsbuf)
1054 desc = util_format_description(fb->zsbuf->format);
1055 if (fb->zsbuf && util_format_has_depth(desc))
1056 need_fence |= swr_change_rt(ctx, SWR_ATTACHMENT_DEPTH, fb->zsbuf);
1057 else
1058 need_fence |= swr_change_rt(ctx, SWR_ATTACHMENT_DEPTH, NULL);
1059
1060 if (fb->zsbuf && util_format_has_stencil(desc))
1061 need_fence |= swr_change_rt(ctx, SWR_ATTACHMENT_STENCIL, fb->zsbuf);
1062 else
1063 need_fence |= swr_change_rt(ctx, SWR_ATTACHMENT_STENCIL, NULL);
1064
1065 /* This fence ensures any attachment changes are resolved before the
1066 * next draw */
1067 if (need_fence)
1068 swr_fence_submit(ctx, screen->flush_fence);
1069 }
1070
1071 /* Raster state */
1072 if (ctx->dirty & (SWR_NEW_RASTERIZER |
1073 SWR_NEW_VS | // clipping
1074 SWR_NEW_FRAMEBUFFER)) {
1075 pipe_rasterizer_state *rasterizer = ctx->rasterizer;
1076 pipe_framebuffer_state *fb = &ctx->framebuffer;
1077
1078 SWR_RASTSTATE *rastState = &ctx->derived.rastState;
1079 rastState->cullMode = swr_convert_cull_mode(rasterizer->cull_face);
1080 rastState->frontWinding = rasterizer->front_ccw
1081 ? SWR_FRONTWINDING_CCW
1082 : SWR_FRONTWINDING_CW;
1083 rastState->scissorEnable = rasterizer->scissor;
1084 rastState->pointSize = rasterizer->point_size > 0.0f
1085 ? rasterizer->point_size
1086 : 1.0f;
1087 rastState->lineWidth = rasterizer->line_width > 0.0f
1088 ? rasterizer->line_width
1089 : 1.0f;
1090
1091 rastState->pointParam = rasterizer->point_size_per_vertex;
1092
1093 rastState->pointSpriteEnable = rasterizer->sprite_coord_enable;
1094 rastState->pointSpriteTopOrigin =
1095 rasterizer->sprite_coord_mode == PIPE_SPRITE_COORD_UPPER_LEFT;
1096
1097 /* If SWR_MSAA_FORCE_ENABLE is set, turn msaa on */
1098 if (screen->msaa_force_enable && !rasterizer->multisample) {
1099 /* Force enable and use the value the surface was created with */
1100 rasterizer->multisample = true;
1101 fb->samples = swr_resource(fb->cbufs[0]->texture)->swr.numSamples;
1102 fprintf(stderr,"msaa force enable: %d samples\n", fb->samples);
1103 }
1104
1105 rastState->sampleCount = GetSampleCount(fb->samples);
1106 rastState->forcedSampleCount = false;
1107 rastState->bIsCenterPattern = !rasterizer->multisample;
1108 rastState->pixelLocation = SWR_PIXEL_LOCATION_CENTER;
1109
1110 /* Only initialize sample positions if msaa is enabled */
1111 if (rasterizer->multisample) {
1112 for (uint32_t i = 0; i < fb->samples; i++) {
1113 const uint8_t *sample = swr_sample_positions[fb->samples-1 + i];
1114 rastState->samplePositions.SetXi(i, sample[0] << 4);
1115 rastState->samplePositions.SetYi(i, sample[1] << 4);
1116 rastState->samplePositions.SetX (i, sample[0] / 16.0f);
1117 rastState->samplePositions.SetY (i, sample[1] / 16.0f);
1118 }
1119 rastState->samplePositions.PrecalcSampleData(fb->samples);
1120 }
1121
1122 bool do_offset = false;
1123 switch (rasterizer->fill_front) {
1124 case PIPE_POLYGON_MODE_FILL:
1125 do_offset = rasterizer->offset_tri;
1126 break;
1127 case PIPE_POLYGON_MODE_LINE:
1128 do_offset = rasterizer->offset_line;
1129 break;
1130 case PIPE_POLYGON_MODE_POINT:
1131 do_offset = rasterizer->offset_point;
1132 break;
1133 }
1134
1135 if (do_offset) {
1136 rastState->depthBias = rasterizer->offset_units;
1137 rastState->slopeScaledDepthBias = rasterizer->offset_scale;
1138 rastState->depthBiasClamp = rasterizer->offset_clamp;
1139 } else {
1140 rastState->depthBias = 0;
1141 rastState->slopeScaledDepthBias = 0;
1142 rastState->depthBiasClamp = 0;
1143 }
1144 struct pipe_surface *zb = fb->zsbuf;
1145 if (zb && swr_resource(zb->texture)->has_depth)
1146 rastState->depthFormat = swr_resource(zb->texture)->swr.format;
1147
1148 rastState->depthClipEnable = rasterizer->depth_clip;
1149 rastState->clipHalfZ = rasterizer->clip_halfz;
1150
1151 rastState->clipDistanceMask =
1152 ctx->vs->info.base.num_written_clipdistance ?
1153 ctx->vs->info.base.clipdist_writemask & rasterizer->clip_plane_enable :
1154 rasterizer->clip_plane_enable;
1155
1156 rastState->cullDistanceMask =
1157 ctx->vs->info.base.culldist_writemask << ctx->vs->info.base.num_written_clipdistance;
1158
1159 SwrSetRastState(ctx->swrContext, rastState);
1160 }
1161
1162 /* Scissor */
1163 if (ctx->dirty & SWR_NEW_SCISSOR) {
1164 SwrSetScissorRects(ctx->swrContext, 1, &ctx->swr_scissor);
1165 }
1166
1167 /* Viewport */
1168 if (ctx->dirty & (SWR_NEW_VIEWPORT | SWR_NEW_FRAMEBUFFER
1169 | SWR_NEW_RASTERIZER)) {
1170 pipe_viewport_state *state = &ctx->viewport;
1171 pipe_framebuffer_state *fb = &ctx->framebuffer;
1172 pipe_rasterizer_state *rasterizer = ctx->rasterizer;
1173
1174 SWR_VIEWPORT *vp = &ctx->derived.vp;
1175 SWR_VIEWPORT_MATRICES *vpm = &ctx->derived.vpm;
1176
1177 vp->x = state->translate[0] - state->scale[0];
1178 vp->width = 2 * state->scale[0];
1179 vp->y = state->translate[1] - fabs(state->scale[1]);
1180 vp->height = 2 * fabs(state->scale[1]);
1181 util_viewport_zmin_zmax(state, rasterizer->clip_halfz,
1182 &vp->minZ, &vp->maxZ);
1183
1184 vpm->m00[0] = state->scale[0];
1185 vpm->m11[0] = state->scale[1];
1186 vpm->m22[0] = state->scale[2];
1187 vpm->m30[0] = state->translate[0];
1188 vpm->m31[0] = state->translate[1];
1189 vpm->m32[0] = state->translate[2];
1190
1191 /* Now that the matrix is calculated, clip the view coords to screen
1192 * size. OpenGL allows for -ve x,y in the viewport. */
1193 if (vp->x < 0.0f) {
1194 vp->width += vp->x;
1195 vp->x = 0.0f;
1196 }
1197 if (vp->y < 0.0f) {
1198 vp->height += vp->y;
1199 vp->y = 0.0f;
1200 }
1201 vp->width = std::min(vp->width, (float)fb->width - vp->x);
1202 vp->height = std::min(vp->height, (float)fb->height - vp->y);
1203
1204 SwrSetViewports(ctx->swrContext, 1, vp, vpm);
1205 }
1206
1207 /* Set vertex & index buffers */
1208 /* (using draw info if called by swr_draw_vbo) */
1209 if (ctx->dirty & SWR_NEW_VERTEX) {
1210 uint32_t scratch_total;
1211 uint8_t *scratch = NULL;
1212
1213 /* If being called by swr_draw_vbo, copy draw details */
1214 struct pipe_draw_info info = {0};
1215 if (p_draw_info)
1216 info = *p_draw_info;
1217
1218 /* We must get all the scratch space in one go */
1219 scratch_total = 0;
1220 for (UINT i = 0; i < ctx->num_vertex_buffers; i++) {
1221 struct pipe_vertex_buffer *vb = &ctx->vertex_buffer[i];
1222
1223 if (!vb->user_buffer)
1224 continue;
1225
1226 uint32_t elems, base, size;
1227 swr_user_vbuf_range(&info, ctx->velems, vb, i, &elems, &base, &size);
1228 scratch_total += AlignUp(size, 4);
1229 }
1230
1231 if (scratch_total) {
1232 scratch = (uint8_t *)swr_copy_to_scratch_space(
1233 ctx, &ctx->scratch->vertex_buffer, NULL, scratch_total);
1234 }
1235
1236 /* vertex buffers */
1237 SWR_VERTEX_BUFFER_STATE swrVertexBuffers[PIPE_MAX_ATTRIBS];
1238 for (UINT i = 0; i < ctx->num_vertex_buffers; i++) {
1239 uint32_t size, pitch, elems, partial_inbounds;
1240 uint32_t min_vertex_index;
1241 const uint8_t *p_data;
1242 struct pipe_vertex_buffer *vb = &ctx->vertex_buffer[i];
1243
1244 pitch = vb->stride;
1245 if (!vb->user_buffer) {
1246 /* VBO
1247 * size is based on buffer->width0 rather than info.max_index
1248 * to prevent having to validate VBO on each draw */
1249 size = vb->buffer->width0;
1250 elems = size / pitch;
1251 partial_inbounds = size % pitch;
1252 min_vertex_index = 0;
1253
1254 p_data = swr_resource_data(vb->buffer) + vb->buffer_offset;
1255 } else {
1256 /* Client buffer
1257 * client memory is one-time use, re-trigger SWR_NEW_VERTEX to
1258 * revalidate on each draw */
1259 post_update_dirty_flags |= SWR_NEW_VERTEX;
1260
1261 uint32_t base;
1262 swr_user_vbuf_range(&info, ctx->velems, vb, i, &elems, &base, &size);
1263 partial_inbounds = 0;
1264 min_vertex_index = info.min_index;
1265
1266 /* Copy only needed vertices to scratch space */
1267 size = AlignUp(size, 4);
1268 const void *ptr = (const uint8_t *) vb->user_buffer + base;
1269 memcpy(scratch, ptr, size);
1270 ptr = scratch;
1271 scratch += size;
1272 p_data = (const uint8_t *)ptr - base;
1273 }
1274
1275 swrVertexBuffers[i] = {0};
1276 swrVertexBuffers[i].index = i;
1277 swrVertexBuffers[i].pitch = pitch;
1278 swrVertexBuffers[i].pData = p_data;
1279 swrVertexBuffers[i].size = size;
1280 swrVertexBuffers[i].minVertex = min_vertex_index;
1281 swrVertexBuffers[i].maxVertex = elems;
1282 swrVertexBuffers[i].partialInboundsSize = partial_inbounds;
1283 }
1284
1285 SwrSetVertexBuffers(
1286 ctx->swrContext, ctx->num_vertex_buffers, swrVertexBuffers);
1287
1288 /* index buffer, if required (info passed in by swr_draw_vbo) */
1289 SWR_FORMAT index_type = R32_UINT; /* Default for non-indexed draws */
1290 if (info.indexed) {
1291 const uint8_t *p_data;
1292 uint32_t size, pitch;
1293 struct pipe_index_buffer *ib = &ctx->index_buffer;
1294
1295 pitch = ib->index_size ? ib->index_size : sizeof(uint32_t);
1296 index_type = swr_convert_index_type(pitch);
1297
1298 if (!ib->user_buffer) {
1299 /* VBO
1300 * size is based on buffer->width0 rather than info.count
1301 * to prevent having to validate VBO on each draw */
1302 size = ib->buffer->width0;
1303 p_data = swr_resource_data(ib->buffer) + ib->offset;
1304 } else {
1305 /* Client buffer
1306 * client memory is one-time use, re-trigger SWR_NEW_VERTEX to
1307 * revalidate on each draw */
1308 post_update_dirty_flags |= SWR_NEW_VERTEX;
1309
1310 size = info.count * pitch;
1311 size = AlignUp(size, 4);
1312
1313 /* Copy indices to scratch space */
1314 const void *ptr = ib->user_buffer;
1315 ptr = swr_copy_to_scratch_space(
1316 ctx, &ctx->scratch->index_buffer, ptr, size);
1317 p_data = (const uint8_t *)ptr;
1318 }
1319
1320 SWR_INDEX_BUFFER_STATE swrIndexBuffer;
1321 swrIndexBuffer.format = swr_convert_index_type(ib->index_size);
1322 swrIndexBuffer.pIndices = p_data;
1323 swrIndexBuffer.size = size;
1324
1325 SwrSetIndexBuffer(ctx->swrContext, &swrIndexBuffer);
1326 }
1327
1328 struct swr_vertex_element_state *velems = ctx->velems;
1329 if (velems && velems->fsState.indexType != index_type) {
1330 velems->fsFunc = NULL;
1331 velems->fsState.indexType = index_type;
1332 }
1333 }
1334
1335 /* GeometryShader */
1336 if (ctx->dirty & (SWR_NEW_GS |
1337 SWR_NEW_VS |
1338 SWR_NEW_SAMPLER |
1339 SWR_NEW_SAMPLER_VIEW)) {
1340 if (ctx->gs) {
1341 swr_jit_gs_key key;
1342 swr_generate_gs_key(key, ctx, ctx->gs);
1343 auto search = ctx->gs->map.find(key);
1344 PFN_GS_FUNC func;
1345 if (search != ctx->gs->map.end()) {
1346 func = search->second->shader;
1347 } else {
1348 func = swr_compile_gs(ctx, key);
1349 }
1350 SwrSetGsFunc(ctx->swrContext, func);
1351
1352 /* JIT sampler state */
1353 if (ctx->dirty & SWR_NEW_SAMPLER) {
1354 swr_update_sampler_state(ctx,
1355 PIPE_SHADER_GEOMETRY,
1356 key.nr_samplers,
1357 ctx->swrDC.samplersGS);
1358 }
1359
1360 /* JIT sampler view state */
1361 if (ctx->dirty & (SWR_NEW_SAMPLER_VIEW | SWR_NEW_FRAMEBUFFER)) {
1362 swr_update_texture_state(ctx,
1363 PIPE_SHADER_GEOMETRY,
1364 key.nr_sampler_views,
1365 ctx->swrDC.texturesGS);
1366 }
1367
1368 SwrSetGsState(ctx->swrContext, &ctx->gs->gsState);
1369 } else {
1370 SWR_GS_STATE state = { 0 };
1371 SwrSetGsState(ctx->swrContext, &state);
1372 SwrSetGsFunc(ctx->swrContext, NULL);
1373 }
1374 }
1375
1376 /* VertexShader */
1377 if (ctx->dirty & (SWR_NEW_VS |
1378 SWR_NEW_RASTERIZER | // for clip planes
1379 SWR_NEW_SAMPLER |
1380 SWR_NEW_SAMPLER_VIEW |
1381 SWR_NEW_FRAMEBUFFER)) {
1382 swr_jit_vs_key key;
1383 swr_generate_vs_key(key, ctx, ctx->vs);
1384 auto search = ctx->vs->map.find(key);
1385 PFN_VERTEX_FUNC func;
1386 if (search != ctx->vs->map.end()) {
1387 func = search->second->shader;
1388 } else {
1389 func = swr_compile_vs(ctx, key);
1390 }
1391 SwrSetVertexFunc(ctx->swrContext, func);
1392
1393 /* JIT sampler state */
1394 if (ctx->dirty & SWR_NEW_SAMPLER) {
1395 swr_update_sampler_state(ctx,
1396 PIPE_SHADER_VERTEX,
1397 key.nr_samplers,
1398 ctx->swrDC.samplersVS);
1399 }
1400
1401 /* JIT sampler view state */
1402 if (ctx->dirty & (SWR_NEW_SAMPLER_VIEW | SWR_NEW_FRAMEBUFFER)) {
1403 swr_update_texture_state(ctx,
1404 PIPE_SHADER_VERTEX,
1405 key.nr_sampler_views,
1406 ctx->swrDC.texturesVS);
1407 }
1408 }
1409
1410 /* FragmentShader */
1411 if (ctx->dirty & (SWR_NEW_FS |
1412 SWR_NEW_VS |
1413 SWR_NEW_GS |
1414 SWR_NEW_RASTERIZER |
1415 SWR_NEW_SAMPLER |
1416 SWR_NEW_SAMPLER_VIEW |
1417 SWR_NEW_FRAMEBUFFER)) {
1418 swr_jit_fs_key key;
1419 swr_generate_fs_key(key, ctx, ctx->fs);
1420 auto search = ctx->fs->map.find(key);
1421 PFN_PIXEL_KERNEL func;
1422 if (search != ctx->fs->map.end()) {
1423 func = search->second->shader;
1424 } else {
1425 func = swr_compile_fs(ctx, key);
1426 }
1427 SWR_PS_STATE psState = {0};
1428 psState.pfnPixelShader = func;
1429 psState.killsPixel = ctx->fs->info.base.uses_kill;
1430 psState.inputCoverage = SWR_INPUT_COVERAGE_NORMAL;
1431 psState.writesODepth = ctx->fs->info.base.writes_z;
1432 psState.usesSourceDepth = ctx->fs->info.base.reads_z;
1433 psState.shadingRate = SWR_SHADING_RATE_PIXEL;
1434 psState.numRenderTargets = ctx->framebuffer.nr_cbufs;
1435 psState.posOffset = SWR_PS_POSITION_SAMPLE_NONE;
1436 uint32_t barycentricsMask = 0;
1437 #if 0
1438 // when we switch to mesa-master
1439 if (ctx->fs->info.base.uses_persp_center ||
1440 ctx->fs->info.base.uses_linear_center)
1441 barycentricsMask |= SWR_BARYCENTRIC_PER_PIXEL_MASK;
1442 if (ctx->fs->info.base.uses_persp_centroid ||
1443 ctx->fs->info.base.uses_linear_centroid)
1444 barycentricsMask |= SWR_BARYCENTRIC_CENTROID_MASK;
1445 if (ctx->fs->info.base.uses_persp_sample ||
1446 ctx->fs->info.base.uses_linear_sample)
1447 barycentricsMask |= SWR_BARYCENTRIC_PER_SAMPLE_MASK;
1448 #else
1449 for (unsigned i = 0; i < ctx->fs->info.base.num_inputs; i++) {
1450 switch (ctx->fs->info.base.input_interpolate_loc[i]) {
1451 case TGSI_INTERPOLATE_LOC_CENTER:
1452 barycentricsMask |= SWR_BARYCENTRIC_PER_PIXEL_MASK;
1453 break;
1454 case TGSI_INTERPOLATE_LOC_CENTROID:
1455 barycentricsMask |= SWR_BARYCENTRIC_CENTROID_MASK;
1456 break;
1457 case TGSI_INTERPOLATE_LOC_SAMPLE:
1458 barycentricsMask |= SWR_BARYCENTRIC_PER_SAMPLE_MASK;
1459 break;
1460 }
1461 }
1462 #endif
1463 psState.barycentricsMask = barycentricsMask;
1464 psState.usesUAV = false; // XXX
1465 psState.forceEarlyZ = false;
1466 SwrSetPixelShaderState(ctx->swrContext, &psState);
1467
1468 /* JIT sampler state */
1469 if (ctx->dirty & (SWR_NEW_SAMPLER |
1470 SWR_NEW_FS)) {
1471 swr_update_sampler_state(ctx,
1472 PIPE_SHADER_FRAGMENT,
1473 key.nr_samplers,
1474 ctx->swrDC.samplersFS);
1475 }
1476
1477 /* JIT sampler view state */
1478 if (ctx->dirty & (SWR_NEW_SAMPLER_VIEW |
1479 SWR_NEW_FRAMEBUFFER |
1480 SWR_NEW_FS)) {
1481 swr_update_texture_state(ctx,
1482 PIPE_SHADER_FRAGMENT,
1483 key.nr_sampler_views,
1484 ctx->swrDC.texturesFS);
1485 }
1486 }
1487
1488
1489 /* VertexShader Constants */
1490 if (ctx->dirty & SWR_NEW_VSCONSTANTS) {
1491 swr_update_constants(ctx, PIPE_SHADER_VERTEX);
1492 }
1493
1494 /* FragmentShader Constants */
1495 if (ctx->dirty & SWR_NEW_FSCONSTANTS) {
1496 swr_update_constants(ctx, PIPE_SHADER_FRAGMENT);
1497 }
1498
1499 /* GeometryShader Constants */
1500 if (ctx->dirty & SWR_NEW_GSCONSTANTS) {
1501 swr_update_constants(ctx, PIPE_SHADER_GEOMETRY);
1502 }
1503
1504 /* Depth/stencil state */
1505 if (ctx->dirty & (SWR_NEW_DEPTH_STENCIL_ALPHA | SWR_NEW_FRAMEBUFFER)) {
1506 struct pipe_depth_state *depth = &(ctx->depth_stencil->depth);
1507 struct pipe_stencil_state *stencil = ctx->depth_stencil->stencil;
1508 SWR_DEPTH_STENCIL_STATE depthStencilState = {{0}};
1509 SWR_DEPTH_BOUNDS_STATE depthBoundsState = {0};
1510
1511 /* XXX, incomplete. Need to flesh out stencil & alpha test state
1512 struct pipe_stencil_state *front_stencil =
1513 ctx->depth_stencil.stencil[0];
1514 struct pipe_stencil_state *back_stencil = ctx->depth_stencil.stencil[1];
1515 struct pipe_alpha_state alpha;
1516 */
1517 if (stencil[0].enabled) {
1518 depthStencilState.stencilWriteEnable = 1;
1519 depthStencilState.stencilTestEnable = 1;
1520 depthStencilState.stencilTestFunc =
1521 swr_convert_depth_func(stencil[0].func);
1522
1523 depthStencilState.stencilPassDepthPassOp =
1524 swr_convert_stencil_op(stencil[0].zpass_op);
1525 depthStencilState.stencilPassDepthFailOp =
1526 swr_convert_stencil_op(stencil[0].zfail_op);
1527 depthStencilState.stencilFailOp =
1528 swr_convert_stencil_op(stencil[0].fail_op);
1529 depthStencilState.stencilWriteMask = stencil[0].writemask;
1530 depthStencilState.stencilTestMask = stencil[0].valuemask;
1531 depthStencilState.stencilRefValue = ctx->stencil_ref.ref_value[0];
1532 }
1533 if (stencil[1].enabled) {
1534 depthStencilState.doubleSidedStencilTestEnable = 1;
1535
1536 depthStencilState.backfaceStencilTestFunc =
1537 swr_convert_depth_func(stencil[1].func);
1538
1539 depthStencilState.backfaceStencilPassDepthPassOp =
1540 swr_convert_stencil_op(stencil[1].zpass_op);
1541 depthStencilState.backfaceStencilPassDepthFailOp =
1542 swr_convert_stencil_op(stencil[1].zfail_op);
1543 depthStencilState.backfaceStencilFailOp =
1544 swr_convert_stencil_op(stencil[1].fail_op);
1545 depthStencilState.backfaceStencilWriteMask = stencil[1].writemask;
1546 depthStencilState.backfaceStencilTestMask = stencil[1].valuemask;
1547
1548 depthStencilState.backfaceStencilRefValue =
1549 ctx->stencil_ref.ref_value[1];
1550 }
1551
1552 depthStencilState.depthTestEnable = depth->enabled;
1553 depthStencilState.depthTestFunc = swr_convert_depth_func(depth->func);
1554 depthStencilState.depthWriteEnable = depth->writemask;
1555 SwrSetDepthStencilState(ctx->swrContext, &depthStencilState);
1556
1557 depthBoundsState.depthBoundsTestEnable = depth->bounds_test;
1558 depthBoundsState.depthBoundsTestMinValue = depth->bounds_min;
1559 depthBoundsState.depthBoundsTestMaxValue = depth->bounds_max;
1560 SwrSetDepthBoundsState(ctx->swrContext, &depthBoundsState);
1561 }
1562
1563 /* Blend State */
1564 if (ctx->dirty & (SWR_NEW_BLEND |
1565 SWR_NEW_RASTERIZER |
1566 SWR_NEW_FRAMEBUFFER |
1567 SWR_NEW_DEPTH_STENCIL_ALPHA)) {
1568 struct pipe_framebuffer_state *fb = &ctx->framebuffer;
1569
1570 SWR_BLEND_STATE blendState;
1571 memcpy(&blendState, &ctx->blend->blendState, sizeof(blendState));
1572 blendState.constantColor[0] = ctx->blend_color.color[0];
1573 blendState.constantColor[1] = ctx->blend_color.color[1];
1574 blendState.constantColor[2] = ctx->blend_color.color[2];
1575 blendState.constantColor[3] = ctx->blend_color.color[3];
1576 blendState.alphaTestReference =
1577 *((uint32_t*)&ctx->depth_stencil->alpha.ref_value);
1578
1579 blendState.sampleMask = ctx->sample_mask;
1580 blendState.sampleCount = GetSampleCount(fb->samples);
1581
1582 /* If there are no color buffers bound, disable writes on RT0
1583 * and skip loop */
1584 if (fb->nr_cbufs == 0) {
1585 blendState.renderTarget[0].writeDisableRed = 1;
1586 blendState.renderTarget[0].writeDisableGreen = 1;
1587 blendState.renderTarget[0].writeDisableBlue = 1;
1588 blendState.renderTarget[0].writeDisableAlpha = 1;
1589 SwrSetBlendFunc(ctx->swrContext, 0, NULL);
1590 }
1591 else
1592 for (int target = 0;
1593 target < std::min(SWR_NUM_RENDERTARGETS,
1594 PIPE_MAX_COLOR_BUFS);
1595 target++) {
1596 if (!fb->cbufs[target])
1597 continue;
1598
1599 struct swr_resource *colorBuffer =
1600 swr_resource(fb->cbufs[target]->texture);
1601
1602 BLEND_COMPILE_STATE compileState;
1603 memset(&compileState, 0, sizeof(compileState));
1604 compileState.format = colorBuffer->swr.format;
1605 memcpy(&compileState.blendState,
1606 &ctx->blend->compileState[target],
1607 sizeof(compileState.blendState));
1608
1609 const SWR_FORMAT_INFO& info = GetFormatInfo(compileState.format);
1610 if (compileState.blendState.logicOpEnable &&
1611 ((info.type[0] == SWR_TYPE_FLOAT) || info.isSRGB)) {
1612 compileState.blendState.logicOpEnable = false;
1613 }
1614
1615 if (info.type[0] == SWR_TYPE_SINT || info.type[0] == SWR_TYPE_UINT)
1616 compileState.blendState.blendEnable = false;
1617
1618 if (compileState.blendState.blendEnable == false &&
1619 compileState.blendState.logicOpEnable == false &&
1620 ctx->depth_stencil->alpha.enabled == 0) {
1621 SwrSetBlendFunc(ctx->swrContext, target, NULL);
1622 continue;
1623 }
1624
1625 compileState.desc.alphaTestEnable =
1626 ctx->depth_stencil->alpha.enabled;
1627 compileState.desc.independentAlphaBlendEnable =
1628 (compileState.blendState.sourceBlendFactor !=
1629 compileState.blendState.sourceAlphaBlendFactor) ||
1630 (compileState.blendState.destBlendFactor !=
1631 compileState.blendState.destAlphaBlendFactor) ||
1632 (compileState.blendState.colorBlendFunc !=
1633 compileState.blendState.alphaBlendFunc);
1634 compileState.desc.alphaToCoverageEnable =
1635 ctx->blend->pipe.alpha_to_coverage;
1636 compileState.desc.sampleMaskEnable = (blendState.sampleMask != 0);
1637 compileState.desc.numSamples = fb->samples;
1638
1639 compileState.alphaTestFunction =
1640 swr_convert_depth_func(ctx->depth_stencil->alpha.func);
1641 compileState.alphaTestFormat = ALPHA_TEST_FLOAT32; // xxx
1642
1643 compileState.Canonicalize();
1644
1645 PFN_BLEND_JIT_FUNC func = NULL;
1646 auto search = ctx->blendJIT->find(compileState);
1647 if (search != ctx->blendJIT->end()) {
1648 func = search->second;
1649 } else {
1650 HANDLE hJitMgr = screen->hJitMgr;
1651 func = JitCompileBlend(hJitMgr, compileState);
1652 debug_printf("BLEND shader %p\n", func);
1653 assert(func && "Error: BlendShader = NULL");
1654
1655 ctx->blendJIT->insert(std::make_pair(compileState, func));
1656 }
1657 SwrSetBlendFunc(ctx->swrContext, target, func);
1658 }
1659
1660 SwrSetBlendState(ctx->swrContext, &blendState);
1661 }
1662
1663 if (ctx->dirty & SWR_NEW_STIPPLE) {
1664 /* XXX What to do with this one??? SWR doesn't stipple */
1665 }
1666
1667 if (ctx->dirty & (SWR_NEW_VS | SWR_NEW_SO | SWR_NEW_RASTERIZER)) {
1668 ctx->vs->soState.rasterizerDisable =
1669 ctx->rasterizer->rasterizer_discard;
1670 SwrSetSoState(ctx->swrContext, &ctx->vs->soState);
1671
1672 pipe_stream_output_info *stream_output = &ctx->vs->pipe.stream_output;
1673
1674 for (uint32_t i = 0; i < ctx->num_so_targets; i++) {
1675 SWR_STREAMOUT_BUFFER buffer = {0};
1676 if (!ctx->so_targets[i])
1677 continue;
1678 buffer.enable = true;
1679 buffer.pBuffer =
1680 (uint32_t *)(swr_resource_data(ctx->so_targets[i]->buffer) +
1681 ctx->so_targets[i]->buffer_offset);
1682 buffer.bufferSize = ctx->so_targets[i]->buffer_size >> 2;
1683 buffer.pitch = stream_output->stride[i];
1684 buffer.streamOffset = 0;
1685
1686 SwrSetSoBuffers(ctx->swrContext, &buffer, i);
1687 }
1688 }
1689
1690 if (ctx->dirty & (SWR_NEW_CLIP | SWR_NEW_RASTERIZER | SWR_NEW_VS)) {
1691 // shader exporting clip distances overrides all user clip planes
1692 if (ctx->rasterizer->clip_plane_enable &&
1693 !ctx->vs->info.base.num_written_clipdistance)
1694 {
1695 swr_draw_context *pDC = &ctx->swrDC;
1696 memcpy(pDC->userClipPlanes,
1697 ctx->clip.ucp,
1698 sizeof(pDC->userClipPlanes));
1699 }
1700 }
1701
1702 // set up backend state
1703 SWR_BACKEND_STATE backendState = {0};
1704 backendState.numAttributes =
1705 ((ctx->gs ? ctx->gs->info.base.num_outputs : ctx->vs->info.base.num_outputs) - 1) +
1706 (ctx->rasterizer->sprite_coord_enable ? 1 : 0);
1707 backendState.numAttributes = std::min((size_t)backendState.numAttributes,
1708 sizeof(backendState.numComponents));
1709 for (unsigned i = 0; i < backendState.numAttributes; i++)
1710 backendState.numComponents[i] = 4;
1711 backendState.constantInterpolationMask = ctx->fs->constantMask |
1712 (ctx->rasterizer->flatshade ? ctx->fs->flatConstantMask : 0);
1713 backendState.pointSpriteTexCoordMask = ctx->fs->pointSpriteMask;
1714
1715 SwrSetBackendState(ctx->swrContext, &backendState);
1716
1717 /* Ensure that any in-progress attachment change StoreTiles finish */
1718 if (swr_is_fence_pending(screen->flush_fence))
1719 swr_fence_finish(pipe->screen, NULL, screen->flush_fence, 0);
1720
1721 /* Finally, update the in-use status of all resources involved in draw */
1722 swr_update_resource_status(pipe, p_draw_info);
1723
1724 ctx->dirty = post_update_dirty_flags;
1725 }
1726
1727
1728 static struct pipe_stream_output_target *
1729 swr_create_so_target(struct pipe_context *pipe,
1730 struct pipe_resource *buffer,
1731 unsigned buffer_offset,
1732 unsigned buffer_size)
1733 {
1734 struct pipe_stream_output_target *target;
1735
1736 target = CALLOC_STRUCT(pipe_stream_output_target);
1737 if (!target)
1738 return NULL;
1739
1740 target->context = pipe;
1741 target->reference.count = 1;
1742 pipe_resource_reference(&target->buffer, buffer);
1743 target->buffer_offset = buffer_offset;
1744 target->buffer_size = buffer_size;
1745 return target;
1746 }
1747
1748 static void
1749 swr_destroy_so_target(struct pipe_context *pipe,
1750 struct pipe_stream_output_target *target)
1751 {
1752 pipe_resource_reference(&target->buffer, NULL);
1753 FREE(target);
1754 }
1755
1756 static void
1757 swr_set_so_targets(struct pipe_context *pipe,
1758 unsigned num_targets,
1759 struct pipe_stream_output_target **targets,
1760 const unsigned *offsets)
1761 {
1762 struct swr_context *swr = swr_context(pipe);
1763 uint32_t i;
1764
1765 assert(num_targets <= MAX_SO_STREAMS);
1766
1767 for (i = 0; i < num_targets; i++) {
1768 pipe_so_target_reference(
1769 (struct pipe_stream_output_target **)&swr->so_targets[i],
1770 targets[i]);
1771 }
1772
1773 for (/* fall-through */; i < swr->num_so_targets; i++) {
1774 pipe_so_target_reference(
1775 (struct pipe_stream_output_target **)&swr->so_targets[i], NULL);
1776 }
1777
1778 swr->num_so_targets = num_targets;
1779
1780 swr->dirty |= SWR_NEW_SO;
1781 }
1782
1783
1784 void
1785 swr_state_init(struct pipe_context *pipe)
1786 {
1787 pipe->create_blend_state = swr_create_blend_state;
1788 pipe->bind_blend_state = swr_bind_blend_state;
1789 pipe->delete_blend_state = swr_delete_blend_state;
1790
1791 pipe->create_depth_stencil_alpha_state = swr_create_depth_stencil_state;
1792 pipe->bind_depth_stencil_alpha_state = swr_bind_depth_stencil_state;
1793 pipe->delete_depth_stencil_alpha_state = swr_delete_depth_stencil_state;
1794
1795 pipe->create_rasterizer_state = swr_create_rasterizer_state;
1796 pipe->bind_rasterizer_state = swr_bind_rasterizer_state;
1797 pipe->delete_rasterizer_state = swr_delete_rasterizer_state;
1798
1799 pipe->create_sampler_state = swr_create_sampler_state;
1800 pipe->bind_sampler_states = swr_bind_sampler_states;
1801 pipe->delete_sampler_state = swr_delete_sampler_state;
1802
1803 pipe->create_sampler_view = swr_create_sampler_view;
1804 pipe->set_sampler_views = swr_set_sampler_views;
1805 pipe->sampler_view_destroy = swr_sampler_view_destroy;
1806
1807 pipe->create_vs_state = swr_create_vs_state;
1808 pipe->bind_vs_state = swr_bind_vs_state;
1809 pipe->delete_vs_state = swr_delete_vs_state;
1810
1811 pipe->create_fs_state = swr_create_fs_state;
1812 pipe->bind_fs_state = swr_bind_fs_state;
1813 pipe->delete_fs_state = swr_delete_fs_state;
1814
1815 pipe->create_gs_state = swr_create_gs_state;
1816 pipe->bind_gs_state = swr_bind_gs_state;
1817 pipe->delete_gs_state = swr_delete_gs_state;
1818
1819 pipe->set_constant_buffer = swr_set_constant_buffer;
1820
1821 pipe->create_vertex_elements_state = swr_create_vertex_elements_state;
1822 pipe->bind_vertex_elements_state = swr_bind_vertex_elements_state;
1823 pipe->delete_vertex_elements_state = swr_delete_vertex_elements_state;
1824
1825 pipe->set_vertex_buffers = swr_set_vertex_buffers;
1826 pipe->set_index_buffer = swr_set_index_buffer;
1827
1828 pipe->set_polygon_stipple = swr_set_polygon_stipple;
1829 pipe->set_clip_state = swr_set_clip_state;
1830 pipe->set_scissor_states = swr_set_scissor_states;
1831 pipe->set_viewport_states = swr_set_viewport_states;
1832
1833 pipe->set_framebuffer_state = swr_set_framebuffer_state;
1834
1835 pipe->set_blend_color = swr_set_blend_color;
1836 pipe->set_stencil_ref = swr_set_stencil_ref;
1837
1838 pipe->set_sample_mask = swr_set_sample_mask;
1839 pipe->get_sample_position = swr_get_sample_position;
1840
1841 pipe->create_stream_output_target = swr_create_so_target;
1842 pipe->stream_output_target_destroy = swr_destroy_so_target;
1843 pipe->set_stream_output_targets = swr_set_so_targets;
1844 }