a2b4d808aa3534d24a3597d14aadb80e506c0d39
[mesa.git] / src / gallium / drivers / swr / swr_state.h
1 /****************************************************************************
2 * Copyright (C) 2015 Intel Corporation. All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 ***************************************************************************/
23
24 #ifndef SWR_STATE_H
25 #define SWR_STATE_H
26
27 #include "pipe/p_defines.h"
28 #include "tgsi/tgsi_scan.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_dump.h"
31 #include "gallivm/lp_bld_tgsi.h"
32 #include "util/u_hash.h"
33 #include "api.h"
34 #include "swr_tex_sample.h"
35 #include "swr_shader.h"
36 #include <unordered_map>
37
38 /* skeleton */
39 struct swr_vertex_shader {
40 struct pipe_shader_state pipe;
41 struct lp_tgsi_info info;
42 unsigned linkageMask;
43 PFN_VERTEX_FUNC func;
44 SWR_STREAMOUT_STATE soState;
45 PFN_SO_FUNC soFunc[PIPE_PRIM_MAX];
46 };
47
48 struct swr_fragment_shader {
49 struct pipe_shader_state pipe;
50 struct lp_tgsi_info info;
51 uint32_t constantMask;
52 uint32_t pointSpriteMask;
53 std::unordered_map<swr_jit_key, PFN_PIXEL_KERNEL> map;
54 };
55
56 /* Vertex element state */
57 struct swr_vertex_element_state {
58 FETCH_COMPILE_STATE fsState;
59 PFN_FETCH_FUNC fsFunc;
60 uint32_t stream_pitch[PIPE_MAX_ATTRIBS];
61 };
62
63 struct swr_blend_state {
64 struct pipe_blend_state pipe;
65 SWR_BLEND_STATE blendState;
66 RENDER_TARGET_BLEND_COMPILE_STATE compileState[PIPE_MAX_COLOR_BUFS];
67 };
68
69 /*
70 * Derived SWR API DrawState
71 * For convenience of making simple changes without re-deriving state.
72 */
73 struct swr_derived_state {
74 SWR_RASTSTATE rastState;
75 SWR_VIEWPORT vp;
76 SWR_VIEWPORT_MATRIX vpm;
77 };
78
79 void swr_update_derived(struct swr_context *,
80 const struct pipe_draw_info * = nullptr);
81
82 /*
83 * Conversion functions: Convert mesa state defines to SWR.
84 */
85
86 static INLINE SWR_LOGIC_OP
87 swr_convert_logic_op(const UINT op)
88 {
89 switch (op) {
90 case PIPE_LOGICOP_CLEAR:
91 return LOGICOP_CLEAR;
92 case PIPE_LOGICOP_NOR:
93 return LOGICOP_NOR;
94 case PIPE_LOGICOP_AND_INVERTED:
95 return LOGICOP_CLEAR;
96 case PIPE_LOGICOP_COPY_INVERTED:
97 return LOGICOP_COPY_INVERTED;
98 case PIPE_LOGICOP_AND_REVERSE:
99 return LOGICOP_AND_REVERSE;
100 case PIPE_LOGICOP_INVERT:
101 return LOGICOP_INVERT;
102 case PIPE_LOGICOP_XOR:
103 return LOGICOP_XOR;
104 case PIPE_LOGICOP_NAND:
105 return LOGICOP_NAND;
106 case PIPE_LOGICOP_AND:
107 return LOGICOP_AND;
108 case PIPE_LOGICOP_EQUIV:
109 return LOGICOP_EQUIV;
110 case PIPE_LOGICOP_NOOP:
111 return LOGICOP_NOOP;
112 case PIPE_LOGICOP_OR_INVERTED:
113 return LOGICOP_OR_INVERTED;
114 case PIPE_LOGICOP_COPY:
115 return LOGICOP_COPY;
116 case PIPE_LOGICOP_OR_REVERSE:
117 return LOGICOP_OR_REVERSE;
118 case PIPE_LOGICOP_OR:
119 return LOGICOP_OR;
120 case PIPE_LOGICOP_SET:
121 return LOGICOP_SET;
122 default:
123 assert(0 && "Unsupported logic op");
124 return LOGICOP_NOOP;
125 }
126 }
127
128 static INLINE SWR_STENCILOP
129 swr_convert_stencil_op(const UINT op)
130 {
131 switch (op) {
132 case PIPE_STENCIL_OP_KEEP:
133 return STENCILOP_KEEP;
134 case PIPE_STENCIL_OP_ZERO:
135 return STENCILOP_ZERO;
136 case PIPE_STENCIL_OP_REPLACE:
137 return STENCILOP_REPLACE;
138 case PIPE_STENCIL_OP_INCR:
139 return STENCILOP_INCRSAT;
140 case PIPE_STENCIL_OP_DECR:
141 return STENCILOP_DECRSAT;
142 case PIPE_STENCIL_OP_INCR_WRAP:
143 return STENCILOP_INCR;
144 case PIPE_STENCIL_OP_DECR_WRAP:
145 return STENCILOP_DECR;
146 case PIPE_STENCIL_OP_INVERT:
147 return STENCILOP_INVERT;
148 default:
149 assert(0 && "Unsupported stencil op");
150 return STENCILOP_KEEP;
151 }
152 }
153
154 static INLINE SWR_FORMAT
155 swr_convert_index_type(const UINT index_size)
156 {
157 switch (index_size) {
158 case sizeof(unsigned char):
159 return R8_UINT;
160 case sizeof(unsigned short):
161 return R16_UINT;
162 case sizeof(unsigned int):
163 return R32_UINT;
164 default:
165 assert(0 && "Unsupported index type");
166 return R32_UINT;
167 }
168 }
169
170
171 static INLINE SWR_ZFUNCTION
172 swr_convert_depth_func(const UINT pipe_func)
173 {
174 switch (pipe_func) {
175 case PIPE_FUNC_NEVER:
176 return ZFUNC_NEVER;
177 case PIPE_FUNC_LESS:
178 return ZFUNC_LT;
179 case PIPE_FUNC_EQUAL:
180 return ZFUNC_EQ;
181 case PIPE_FUNC_LEQUAL:
182 return ZFUNC_LE;
183 case PIPE_FUNC_GREATER:
184 return ZFUNC_GT;
185 case PIPE_FUNC_NOTEQUAL:
186 return ZFUNC_NE;
187 case PIPE_FUNC_GEQUAL:
188 return ZFUNC_GE;
189 case PIPE_FUNC_ALWAYS:
190 return ZFUNC_ALWAYS;
191 default:
192 assert(0 && "Unsupported depth func");
193 return ZFUNC_ALWAYS;
194 }
195 }
196
197
198 static INLINE SWR_CULLMODE
199 swr_convert_cull_mode(const UINT cull_face)
200 {
201 switch (cull_face) {
202 case PIPE_FACE_NONE:
203 return SWR_CULLMODE_NONE;
204 case PIPE_FACE_FRONT:
205 return SWR_CULLMODE_FRONT;
206 case PIPE_FACE_BACK:
207 return SWR_CULLMODE_BACK;
208 case PIPE_FACE_FRONT_AND_BACK:
209 return SWR_CULLMODE_BOTH;
210 default:
211 assert(0 && "Invalid cull mode");
212 return SWR_CULLMODE_NONE;
213 }
214 }
215
216 static INLINE SWR_BLEND_OP
217 swr_convert_blend_func(const UINT blend_func)
218 {
219 switch (blend_func) {
220 case PIPE_BLEND_ADD:
221 return BLENDOP_ADD;
222 case PIPE_BLEND_SUBTRACT:
223 return BLENDOP_SUBTRACT;
224 case PIPE_BLEND_REVERSE_SUBTRACT:
225 return BLENDOP_REVSUBTRACT;
226 case PIPE_BLEND_MIN:
227 return BLENDOP_MIN;
228 case PIPE_BLEND_MAX:
229 return BLENDOP_MAX;
230 default:
231 assert(0 && "Invalid blend func");
232 return BLENDOP_ADD;
233 }
234 }
235
236 static INLINE SWR_BLEND_FACTOR
237 swr_convert_blend_factor(const UINT blend_factor)
238 {
239 switch (blend_factor) {
240 case PIPE_BLENDFACTOR_ONE:
241 return BLENDFACTOR_ONE;
242 case PIPE_BLENDFACTOR_SRC_COLOR:
243 return BLENDFACTOR_SRC_COLOR;
244 case PIPE_BLENDFACTOR_SRC_ALPHA:
245 return BLENDFACTOR_SRC_ALPHA;
246 case PIPE_BLENDFACTOR_DST_ALPHA:
247 return BLENDFACTOR_DST_ALPHA;
248 case PIPE_BLENDFACTOR_DST_COLOR:
249 return BLENDFACTOR_DST_COLOR;
250 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
251 return BLENDFACTOR_SRC_ALPHA_SATURATE;
252 case PIPE_BLENDFACTOR_CONST_COLOR:
253 return BLENDFACTOR_CONST_COLOR;
254 case PIPE_BLENDFACTOR_CONST_ALPHA:
255 return BLENDFACTOR_CONST_ALPHA;
256 case PIPE_BLENDFACTOR_SRC1_COLOR:
257 return BLENDFACTOR_SRC1_COLOR;
258 case PIPE_BLENDFACTOR_SRC1_ALPHA:
259 return BLENDFACTOR_SRC1_ALPHA;
260 case PIPE_BLENDFACTOR_ZERO:
261 return BLENDFACTOR_ZERO;
262 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
263 return BLENDFACTOR_INV_SRC_COLOR;
264 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
265 return BLENDFACTOR_INV_SRC_ALPHA;
266 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
267 return BLENDFACTOR_INV_DST_ALPHA;
268 case PIPE_BLENDFACTOR_INV_DST_COLOR:
269 return BLENDFACTOR_INV_DST_COLOR;
270 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
271 return BLENDFACTOR_INV_CONST_COLOR;
272 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
273 return BLENDFACTOR_INV_CONST_ALPHA;
274 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
275 return BLENDFACTOR_INV_SRC1_COLOR;
276 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
277 return BLENDFACTOR_INV_SRC1_ALPHA;
278 default:
279 assert(0 && "Invalid blend factor");
280 return BLENDFACTOR_ONE;
281 }
282 }
283
284 static INLINE enum SWR_SURFACE_TYPE
285 swr_convert_target_type(const enum pipe_texture_target target)
286 {
287 switch (target) {
288 case PIPE_BUFFER:
289 return SURFACE_BUFFER;
290 case PIPE_TEXTURE_1D:
291 case PIPE_TEXTURE_1D_ARRAY:
292 return SURFACE_1D;
293 case PIPE_TEXTURE_2D:
294 case PIPE_TEXTURE_2D_ARRAY:
295 case PIPE_TEXTURE_RECT:
296 return SURFACE_2D;
297 case PIPE_TEXTURE_3D:
298 return SURFACE_3D;
299 case PIPE_TEXTURE_CUBE:
300 case PIPE_TEXTURE_CUBE_ARRAY:
301 return SURFACE_CUBE;
302 default:
303 assert(0);
304 return SURFACE_NULL;
305 }
306 }
307 #endif