2 * Copyright © 2015-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/u_format.h"
25 #include "util/u_surface.h"
26 #include "util/u_blitter.h"
27 #include "v3d_context.h"
28 #include "v3d_tiling.h"
31 static struct pipe_surface
*
32 v3d_get_blit_surface(struct pipe_context
*pctx
,
33 struct pipe_resource
*prsc
, unsigned level
)
35 struct pipe_surface tmpl
;
37 memset(&tmpl
, 0, sizeof(tmpl
));
38 tmpl
.format
= prsc
->format
;
39 tmpl
.u
.tex
.level
= level
;
40 tmpl
.u
.tex
.first_layer
= 0;
41 tmpl
.u
.tex
.last_layer
= 0;
43 return pctx
->create_surface(pctx
, prsc
, &tmpl
);
47 is_tile_unaligned(unsigned size
, unsigned tile_size
)
49 return size
& (tile_size
- 1);
53 v3d_tile_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*info
)
55 struct v3d_context
*v3d
= v3d_context(pctx
);
56 bool msaa
= (info
->src
.resource
->nr_samples
> 1 ||
57 info
->dst
.resource
->nr_samples
> 1);
58 int tile_width
= msaa
? 32 : 64;
59 int tile_height
= msaa
? 32 : 64;
61 if (util_format_is_depth_or_stencil(info
->dst
.resource
->format
))
64 if (info
->scissor_enable
)
67 if ((info
->mask
& PIPE_MASK_RGBA
) == 0)
70 if (info
->dst
.box
.x
!= info
->src
.box
.x
||
71 info
->dst
.box
.y
!= info
->src
.box
.y
||
72 info
->dst
.box
.width
!= info
->src
.box
.width
||
73 info
->dst
.box
.height
!= info
->src
.box
.height
) {
77 int dst_surface_width
= u_minify(info
->dst
.resource
->width0
,
79 int dst_surface_height
= u_minify(info
->dst
.resource
->height0
,
81 if (is_tile_unaligned(info
->dst
.box
.x
, tile_width
) ||
82 is_tile_unaligned(info
->dst
.box
.y
, tile_height
) ||
83 (is_tile_unaligned(info
->dst
.box
.width
, tile_width
) &&
84 info
->dst
.box
.x
+ info
->dst
.box
.width
!= dst_surface_width
) ||
85 (is_tile_unaligned(info
->dst
.box
.height
, tile_height
) &&
86 info
->dst
.box
.y
+ info
->dst
.box
.height
!= dst_surface_height
)) {
90 /* VC5_PACKET_LOAD_TILE_BUFFER_GENERAL uses the
91 * VC5_PACKET_TILE_RENDERING_MODE_CONFIG's width (determined by our
92 * destination surface) to determine the stride. This may be wrong
93 * when reading from texture miplevels > 0, which are stored in
94 * POT-sized areas. For MSAA, the tile addresses are computed
95 * explicitly by the RCL, but still use the destination width to
96 * determine the stride (which could be fixed by explicitly supplying
99 struct v3d_resource
*rsc
= v3d_resource(info
->src
.resource
);
103 if (info
->src
.resource
->nr_samples
> 1)
104 stride
= align(dst_surface_width
, 32) * 4 * rsc
->cpp
;
105 /* XXX else if (rsc->slices[info->src.level].tiling == VC5_TILING_FORMAT_T)
106 stride = align(dst_surface_width * rsc->cpp, 128); */
108 stride
= align(dst_surface_width
* rsc
->cpp
, 16);
110 if (stride
!= rsc
->slices
[info
->src
.level
].stride
)
113 if (info
->dst
.resource
->format
!= info
->src
.resource
->format
)
117 fprintf(stderr
, "RCL blit from %d,%d to %d,%d (%d,%d)\n",
123 info
->dst
.box
.height
);
126 struct pipe_surface
*dst_surf
=
127 v3d_get_blit_surface(pctx
, info
->dst
.resource
, info
->dst
.level
);
128 struct pipe_surface
*src_surf
=
129 v3d_get_blit_surface(pctx
, info
->src
.resource
, info
->src
.level
);
131 v3d_flush_jobs_reading_resource(v3d
, info
->src
.resource
);
133 struct v3d_job
*job
= v3d_get_job(v3d
, dst_surf
, NULL
);
134 pipe_surface_reference(&job
->color_read
, src_surf
);
136 /* If we're resolving from MSAA to single sample, we still need to run
137 * the engine in MSAA mode for the load.
139 if (!job
->msaa
&& info
->src
.resource
->nr_samples
> 1) {
141 job
->tile_width
= 32;
142 job
->tile_height
= 32;
145 job
->draw_min_x
= info
->dst
.box
.x
;
146 job
->draw_min_y
= info
->dst
.box
.y
;
147 job
->draw_max_x
= info
->dst
.box
.x
+ info
->dst
.box
.width
;
148 job
->draw_max_y
= info
->dst
.box
.y
+ info
->dst
.box
.height
;
149 job
->draw_width
= dst_surf
->width
;
150 job
->draw_height
= dst_surf
->height
;
152 job
->tile_width
= tile_width
;
153 job
->tile_height
= tile_height
;
155 job
->needs_flush
= true;
156 job
->resolve
|= PIPE_CLEAR_COLOR
;
158 v3d_job_submit(v3d
, job
);
160 pipe_surface_reference(&dst_surf
, NULL
);
161 pipe_surface_reference(&src_surf
, NULL
);
168 v3d_blitter_save(struct v3d_context
*v3d
)
170 util_blitter_save_fragment_constant_buffer_slot(v3d
->blitter
,
171 v3d
->constbuf
[PIPE_SHADER_FRAGMENT
].cb
);
172 util_blitter_save_vertex_buffer_slot(v3d
->blitter
, v3d
->vertexbuf
.vb
);
173 util_blitter_save_vertex_elements(v3d
->blitter
, v3d
->vtx
);
174 util_blitter_save_vertex_shader(v3d
->blitter
, v3d
->prog
.bind_vs
);
175 util_blitter_save_so_targets(v3d
->blitter
, v3d
->streamout
.num_targets
,
176 v3d
->streamout
.targets
);
177 util_blitter_save_rasterizer(v3d
->blitter
, v3d
->rasterizer
);
178 util_blitter_save_viewport(v3d
->blitter
, &v3d
->viewport
);
179 util_blitter_save_scissor(v3d
->blitter
, &v3d
->scissor
);
180 util_blitter_save_fragment_shader(v3d
->blitter
, v3d
->prog
.bind_fs
);
181 util_blitter_save_blend(v3d
->blitter
, v3d
->blend
);
182 util_blitter_save_depth_stencil_alpha(v3d
->blitter
, v3d
->zsa
);
183 util_blitter_save_stencil_ref(v3d
->blitter
, &v3d
->stencil_ref
);
184 util_blitter_save_sample_mask(v3d
->blitter
, v3d
->sample_mask
);
185 util_blitter_save_framebuffer(v3d
->blitter
, &v3d
->framebuffer
);
186 util_blitter_save_fragment_sampler_states(v3d
->blitter
,
187 v3d
->tex
[PIPE_SHADER_FRAGMENT
].num_samplers
,
188 (void **)v3d
->tex
[PIPE_SHADER_FRAGMENT
].samplers
);
189 util_blitter_save_fragment_sampler_views(v3d
->blitter
,
190 v3d
->tex
[PIPE_SHADER_FRAGMENT
].num_textures
,
191 v3d
->tex
[PIPE_SHADER_FRAGMENT
].textures
);
192 util_blitter_save_so_targets(v3d
->blitter
, v3d
->streamout
.num_targets
,
193 v3d
->streamout
.targets
);
197 v3d_render_blit(struct pipe_context
*ctx
, struct pipe_blit_info
*info
)
199 struct v3d_context
*v3d
= v3d_context(ctx
);
200 struct v3d_resource
*src
= v3d_resource(info
->src
.resource
);
201 struct pipe_resource
*tiled
= NULL
;
204 struct pipe_box box
= {
207 .width
= u_minify(info
->src
.resource
->width0
,
209 .height
= u_minify(info
->src
.resource
->height0
,
213 struct pipe_resource tmpl
= {
214 .target
= info
->src
.resource
->target
,
215 .format
= info
->src
.resource
->format
,
217 .height0
= box
.height
,
221 tiled
= ctx
->screen
->resource_create(ctx
->screen
, &tmpl
);
223 fprintf(stderr
, "Failed to create tiled blit temp\n");
226 ctx
->resource_copy_region(ctx
,
229 info
->src
.resource
, info
->src
.level
,
232 info
->src
.resource
= tiled
;
235 if (!util_blitter_is_blit_supported(v3d
->blitter
, info
)) {
236 fprintf(stderr
, "blit unsupported %s -> %s\n",
237 util_format_short_name(info
->src
.resource
->format
),
238 util_format_short_name(info
->dst
.resource
->format
));
242 v3d_blitter_save(v3d
);
243 util_blitter_blit(v3d
->blitter
, info
);
245 pipe_resource_reference(&tiled
, NULL
);
250 /* Implement stencil blits by reinterpreting the stencil data as an RGBA8888
254 v3d_stencil_blit(struct pipe_context
*ctx
, const struct pipe_blit_info
*info
)
256 struct v3d_context
*v3d
= v3d_context(ctx
);
257 struct v3d_resource
*src
= v3d_resource(info
->src
.resource
);
258 struct v3d_resource
*dst
= v3d_resource(info
->dst
.resource
);
259 enum pipe_format src_format
, dst_format
;
261 if (src
->separate_stencil
) {
262 src
= src
->separate_stencil
;
263 src_format
= PIPE_FORMAT_R8_UNORM
;
265 src_format
= PIPE_FORMAT_RGBA8888_UNORM
;
268 if (dst
->separate_stencil
) {
269 dst
= dst
->separate_stencil
;
270 dst_format
= PIPE_FORMAT_R8_UNORM
;
272 dst_format
= PIPE_FORMAT_RGBA8888_UNORM
;
275 /* Initialize the surface. */
276 struct pipe_surface dst_tmpl
= {
278 .level
= info
->dst
.level
,
279 .first_layer
= info
->dst
.box
.z
,
280 .last_layer
= info
->dst
.box
.z
,
282 .format
= dst_format
,
284 struct pipe_surface
*dst_surf
=
285 ctx
->create_surface(ctx
, &dst
->base
, &dst_tmpl
);
287 /* Initialize the sampler view. */
288 struct pipe_sampler_view src_tmpl
= {
289 .target
= src
->base
.target
,
290 .format
= src_format
,
292 .first_level
= info
->src
.level
,
293 .last_level
= info
->src
.level
,
295 .last_layer
= (PIPE_TEXTURE_3D
?
296 u_minify(src
->base
.depth0
,
297 info
->src
.level
) - 1 :
298 src
->base
.array_size
- 1),
300 .swizzle_r
= PIPE_SWIZZLE_X
,
301 .swizzle_g
= PIPE_SWIZZLE_Y
,
302 .swizzle_b
= PIPE_SWIZZLE_Z
,
303 .swizzle_a
= PIPE_SWIZZLE_W
,
305 struct pipe_sampler_view
*src_view
=
306 ctx
->create_sampler_view(ctx
, &src
->base
, &src_tmpl
);
308 v3d_blitter_save(v3d
);
309 util_blitter_blit_generic(v3d
->blitter
, dst_surf
, &info
->dst
.box
,
310 src_view
, &info
->src
.box
,
311 src
->base
.width0
, src
->base
.height0
,
313 PIPE_TEX_FILTER_NEAREST
,
314 info
->scissor_enable
? &info
->scissor
: NULL
,
317 pipe_surface_reference(&dst_surf
, NULL
);
318 pipe_sampler_view_reference(&src_view
, NULL
);
321 /* Disable level 0 write, just write following mipmaps */
322 #define V3D_TFU_IOA_DIMTW (1 << 0)
323 #define V3D_TFU_IOA_FORMAT_SHIFT 3
324 #define V3D_TFU_IOA_FORMAT_LINEARTILE 3
325 #define V3D_TFU_IOA_FORMAT_UBLINEAR_1_COLUMN 4
326 #define V3D_TFU_IOA_FORMAT_UBLINEAR_2_COLUMN 5
327 #define V3D_TFU_IOA_FORMAT_UIF_NO_XOR 6
328 #define V3D_TFU_IOA_FORMAT_UIF_XOR 7
330 #define V3D_TFU_ICFG_NUMMM_SHIFT 5
331 #define V3D_TFU_ICFG_TTYPE_SHIFT 9
333 #define V3D_TFU_ICFG_FORMAT_SHIFT 18
334 #define V3D_TFU_ICFG_FORMAT_RASTER 0
335 #define V3D_TFU_ICFG_FORMAT_SAND_128 1
336 #define V3D_TFU_ICFG_FORMAT_SAND_256 2
337 #define V3D_TFU_ICFG_FORMAT_LINEARTILE 11
338 #define V3D_TFU_ICFG_FORMAT_UBLINEAR_1_COLUMN 12
339 #define V3D_TFU_ICFG_FORMAT_UBLINEAR_2_COLUMN 13
340 #define V3D_TFU_ICFG_FORMAT_UIF_NO_XOR 14
341 #define V3D_TFU_ICFG_FORMAT_UIF_XOR 15
344 v3d_generate_mipmap(struct pipe_context
*pctx
,
345 struct pipe_resource
*prsc
,
346 enum pipe_format format
,
347 unsigned int base_level
,
348 unsigned int last_level
,
349 unsigned int first_layer
,
350 unsigned int last_layer
)
352 struct v3d_context
*v3d
= v3d_context(pctx
);
353 struct v3d_screen
*screen
= v3d
->screen
;
354 struct v3d_resource
*rsc
= v3d_resource(prsc
);
355 struct v3d_resource_slice
*base_slice
= &rsc
->slices
[base_level
];
356 int width
= u_minify(prsc
->width0
, base_level
);
357 int height
= u_minify(prsc
->height0
, base_level
);
358 uint32_t tex_format
= v3d_get_tex_format(&screen
->devinfo
,
361 if (!v3d_tfu_supports_tex_format(&screen
->devinfo
, tex_format
))
364 if (prsc
->target
!= PIPE_TEXTURE_2D
)
366 /* Since we don't support array or 3D textures, there should be only
369 int layer
= first_layer
;
370 assert(first_layer
== last_layer
);
372 /* Can't write to raster. */
373 if (base_slice
->tiling
== VC5_TILING_RASTER
)
376 v3d_flush_jobs_reading_resource(v3d
, prsc
);
378 struct drm_v3d_submit_tfu tfu
= {
379 .ios
= (height
<< 16) | width
,
380 .bo_handles
= { rsc
->bo
->handle
},
381 .in_sync
= v3d
->out_sync
,
382 .out_sync
= v3d
->out_sync
,
384 uint32_t offset
= (rsc
->bo
->offset
+
385 v3d_layer_offset(prsc
, base_level
, layer
));
387 tfu
.icfg
|= ((V3D_TFU_ICFG_FORMAT_LINEARTILE
+
388 (base_slice
->tiling
- VC5_TILING_LINEARTILE
)) <<
389 V3D_TFU_ICFG_FORMAT_SHIFT
);
392 tfu
.ioa
|= V3D_TFU_IOA_DIMTW
;
393 tfu
.ioa
|= ((V3D_TFU_IOA_FORMAT_LINEARTILE
+
394 (base_slice
->tiling
- VC5_TILING_LINEARTILE
)) <<
395 V3D_TFU_IOA_FORMAT_SHIFT
);
397 tfu
.icfg
|= tex_format
<< V3D_TFU_ICFG_TTYPE_SHIFT
;
398 tfu
.icfg
|= (last_level
- base_level
) << V3D_TFU_ICFG_NUMMM_SHIFT
;
400 switch (base_slice
->tiling
) {
401 case VC5_TILING_UIF_NO_XOR
:
402 case VC5_TILING_UIF_XOR
:
403 tfu
.iis
|= (base_slice
->padded_height
/
404 (2 * v3d_utile_height(rsc
->cpp
)));
406 case VC5_TILING_RASTER
:
407 tfu
.iis
|= base_slice
->stride
/ rsc
->cpp
;
409 case VC5_TILING_LINEARTILE
:
410 case VC5_TILING_UBLINEAR_1_COLUMN
:
411 case VC5_TILING_UBLINEAR_2_COLUMN
:
415 int ret
= v3d_ioctl(screen
->fd
, DRM_IOCTL_V3D_SUBMIT_TFU
, &tfu
);
417 fprintf(stderr
, "Failed to submit TFU job: %d\n", ret
);
424 /* Optimal hardware path for blitting pixels.
425 * Scaling, format conversion, up- and downsampling (resolve) are allowed.
428 v3d_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
430 struct pipe_blit_info info
= *blit_info
;
432 if (info
.mask
& PIPE_MASK_S
) {
433 v3d_stencil_blit(pctx
, blit_info
);
434 info
.mask
&= ~PIPE_MASK_S
;
438 if (v3d_tile_blit(pctx
, blit_info
))
442 v3d_render_blit(pctx
, &info
);