2 * Copyright © 2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/format/u_format.h"
25 #include "v3d_context.h"
26 #include "v3d_tiling.h"
27 #include "broadcom/common/v3d_macros.h"
28 #include "broadcom/cle/v3dx_pack.h"
30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 | \
35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
37 /* The HW queues up the load until the tile coordinates show up, but can only
38 * track one at a time. If we need to do more than one load, then we need to
39 * flush out the previous load by emitting the tile coordinates and doing a
43 flush_last_load(struct v3d_cl
*cl
)
45 if (V3D_VERSION
>= 40)
48 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
49 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
50 store
.buffer_to_store
= NONE
;
55 load_general(struct v3d_cl
*cl
, struct pipe_surface
*psurf
, int buffer
,
56 int layer
, uint32_t pipe_bit
, uint32_t *loads_pending
)
58 struct v3d_surface
*surf
= v3d_surface(psurf
);
59 bool separate_stencil
= surf
->separate_stencil
&& buffer
== STENCIL
;
60 if (separate_stencil
) {
61 psurf
= surf
->separate_stencil
;
62 surf
= v3d_surface(psurf
);
65 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
67 uint32_t layer_offset
=
68 v3d_layer_offset(&rsc
->base
, psurf
->u
.tex
.level
,
69 psurf
->u
.tex
.first_layer
+ layer
);
70 cl_emit(cl
, LOAD_TILE_BUFFER_GENERAL
, load
) {
71 load
.buffer_to_load
= buffer
;
72 load
.address
= cl_address(rsc
->bo
, layer_offset
);
75 load
.memory_format
= surf
->tiling
;
77 load
.input_image_format
= V3D_OUTPUT_IMAGE_FORMAT_S8
;
79 load
.input_image_format
= surf
->format
;
80 load
.r_b_swap
= surf
->swap_rb
;
82 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
83 surf
->tiling
== VC5_TILING_UIF_XOR
) {
84 load
.height_in_ub_or_stride
=
85 surf
->padded_height_of_output_image_in_uif_blocks
;
86 } else if (surf
->tiling
== VC5_TILING_RASTER
) {
87 struct v3d_resource_slice
*slice
=
88 &rsc
->slices
[psurf
->u
.tex
.level
];
89 load
.height_in_ub_or_stride
= slice
->stride
;
92 if (psurf
->texture
->nr_samples
> 1)
93 load
.decimate_mode
= V3D_DECIMATE_MODE_ALL_SAMPLES
;
95 load
.decimate_mode
= V3D_DECIMATE_MODE_SAMPLE_0
;
97 #else /* V3D_VERSION < 40 */
98 /* Can't do raw ZSTENCIL loads -- need to load/store them to
99 * separate buffers for Z and stencil.
101 assert(buffer
!= ZSTENCIL
);
102 load
.raw_mode
= true;
103 load
.padded_height_of_output_image_in_uif_blocks
=
104 surf
->padded_height_of_output_image_in_uif_blocks
;
105 #endif /* V3D_VERSION < 40 */
108 *loads_pending
&= ~pipe_bit
;
114 store_general(struct v3d_job
*job
,
115 struct v3d_cl
*cl
, struct pipe_surface
*psurf
,
116 int layer
, int buffer
, int pipe_bit
,
117 uint32_t *stores_pending
, bool general_color_clear
)
119 struct v3d_surface
*surf
= v3d_surface(psurf
);
120 bool separate_stencil
= surf
->separate_stencil
&& buffer
== STENCIL
;
121 if (separate_stencil
) {
122 psurf
= surf
->separate_stencil
;
123 surf
= v3d_surface(psurf
);
126 *stores_pending
&= ~pipe_bit
;
127 bool last_store
= !(*stores_pending
);
129 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
133 uint32_t layer_offset
=
134 v3d_layer_offset(&rsc
->base
, psurf
->u
.tex
.level
,
135 psurf
->u
.tex
.first_layer
+ layer
);
136 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
137 store
.buffer_to_store
= buffer
;
138 store
.address
= cl_address(rsc
->bo
, layer_offset
);
140 #if V3D_VERSION >= 40
141 store
.clear_buffer_being_stored
= false;
143 if (separate_stencil
)
144 store
.output_image_format
= V3D_OUTPUT_IMAGE_FORMAT_S8
;
146 store
.output_image_format
= surf
->format
;
148 store
.r_b_swap
= surf
->swap_rb
;
149 store
.memory_format
= surf
->tiling
;
151 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
152 surf
->tiling
== VC5_TILING_UIF_XOR
) {
153 store
.height_in_ub_or_stride
=
154 surf
->padded_height_of_output_image_in_uif_blocks
;
155 } else if (surf
->tiling
== VC5_TILING_RASTER
) {
156 struct v3d_resource_slice
*slice
=
157 &rsc
->slices
[psurf
->u
.tex
.level
];
158 store
.height_in_ub_or_stride
= slice
->stride
;
161 if (psurf
->texture
->nr_samples
> 1)
162 store
.decimate_mode
= V3D_DECIMATE_MODE_ALL_SAMPLES
;
164 store
.decimate_mode
= V3D_DECIMATE_MODE_SAMPLE_0
;
166 #else /* V3D_VERSION < 40 */
167 /* Can't do raw ZSTENCIL stores -- need to load/store them to
168 * separate buffers for Z and stencil.
170 assert(buffer
!= ZSTENCIL
);
171 store
.raw_mode
= true;
173 store
.disable_color_buffers_clear_on_write
= true;
174 store
.disable_z_buffer_clear_on_write
= true;
175 store
.disable_stencil_buffer_clear_on_write
= true;
177 store
.disable_color_buffers_clear_on_write
=
178 !(((pipe_bit
& PIPE_CLEAR_COLOR_BUFFERS
) &&
179 general_color_clear
&&
180 (job
->clear
& pipe_bit
)));
181 store
.disable_z_buffer_clear_on_write
=
182 !(job
->clear
& PIPE_CLEAR_DEPTH
);
183 store
.disable_stencil_buffer_clear_on_write
=
184 !(job
->clear
& PIPE_CLEAR_STENCIL
);
186 store
.padded_height_of_output_image_in_uif_blocks
=
187 surf
->padded_height_of_output_image_in_uif_blocks
;
188 #endif /* V3D_VERSION < 40 */
191 /* There must be a TILE_COORDINATES_IMPLICIT between each store. */
192 if (V3D_VERSION
< 40 && !last_store
) {
193 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
198 zs_buffer_from_pipe_bits(int pipe_clear_bits
)
200 switch (pipe_clear_bits
& PIPE_CLEAR_DEPTHSTENCIL
) {
201 case PIPE_CLEAR_DEPTHSTENCIL
:
203 case PIPE_CLEAR_DEPTH
:
205 case PIPE_CLEAR_STENCIL
:
213 v3d_rcl_emit_loads(struct v3d_job
*job
, struct v3d_cl
*cl
, int layer
)
215 uint32_t loads_pending
= job
->load
;
217 for (int i
= 0; i
< V3D_MAX_DRAW_BUFFERS
; i
++) {
218 uint32_t bit
= PIPE_CLEAR_COLOR0
<< i
;
219 if (!(loads_pending
& bit
))
222 struct pipe_surface
*psurf
= job
->cbufs
[i
];
223 if (!psurf
|| (V3D_VERSION
< 40 &&
224 psurf
->texture
->nr_samples
<= 1)) {
228 load_general(cl
, psurf
, RENDER_TARGET_0
+ i
, layer
,
229 bit
, &loads_pending
);
232 if ((loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
) &&
233 (V3D_VERSION
>= 40 ||
234 (job
->zsbuf
&& job
->zsbuf
->texture
->nr_samples
> 1))) {
235 struct v3d_resource
*rsc
= v3d_resource(job
->zsbuf
->texture
);
237 if (rsc
->separate_stencil
&&
238 (loads_pending
& PIPE_CLEAR_STENCIL
)) {
239 load_general(cl
, job
->zsbuf
,
245 if (loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
) {
246 load_general(cl
, job
->zsbuf
,
247 zs_buffer_from_pipe_bits(loads_pending
),
249 loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
,
255 /* The initial reload will be queued until we get the
259 cl_emit(cl
, RELOAD_TILE_COLOR_BUFFER
, load
) {
260 load
.disable_color_buffer_load
=
262 PIPE_CLEAR_COLOR_BUFFERS
) >>
263 PIPE_FIRST_COLOR_BUFFER_BIT
;
265 loads_pending
& PIPE_CLEAR_DEPTH
;
266 load
.enable_stencil_load
=
267 loads_pending
& PIPE_CLEAR_STENCIL
;
270 #else /* V3D_VERSION >= 40 */
271 assert(!loads_pending
);
272 cl_emit(cl
, END_OF_LOADS
, end
);
277 v3d_rcl_emit_stores(struct v3d_job
*job
, struct v3d_cl
*cl
, int layer
)
280 UNUSED
bool needs_color_clear
= job
->clear
& PIPE_CLEAR_COLOR_BUFFERS
;
281 UNUSED
bool needs_z_clear
= job
->clear
& PIPE_CLEAR_DEPTH
;
282 UNUSED
bool needs_s_clear
= job
->clear
& PIPE_CLEAR_STENCIL
;
284 /* For clearing color in a TLB general on V3D 3.3:
286 * - NONE buffer store clears all TLB color buffers.
287 * - color buffer store clears just the TLB color buffer being stored.
288 * - Z/S buffers store may not clear the TLB color buffer.
290 * And on V3D 4.1, we only have one flag for "clear the buffer being
291 * stored" in the general packet, and a separate packet to clear all
294 * As a result, we only bother flagging TLB color clears in a general
295 * packet when we don't have to emit a separate packet to clear all
298 bool general_color_clear
= (needs_color_clear
&&
299 (job
->clear
& PIPE_CLEAR_COLOR_BUFFERS
) ==
300 (job
->store
& PIPE_CLEAR_COLOR_BUFFERS
));
302 bool general_color_clear
= false;
305 uint32_t stores_pending
= job
->store
;
307 /* For V3D 4.1, use general stores for all TLB stores.
309 * For V3D 3.3, we only use general stores to do raw stores for any
310 * MSAA surfaces. These output UIF tiled images where each 4x MSAA
311 * pixel is a 2x2 quad, and the format will be that of the
312 * internal_type/internal_bpp, rather than the format from GL's
313 * perspective. Non-MSAA surfaces will use
314 * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
316 for (int i
= 0; i
< V3D_MAX_DRAW_BUFFERS
; i
++) {
317 uint32_t bit
= PIPE_CLEAR_COLOR0
<< i
;
318 if (!(job
->store
& bit
))
321 struct pipe_surface
*psurf
= job
->cbufs
[i
];
323 (V3D_VERSION
< 40 && psurf
->texture
->nr_samples
<= 1)) {
327 store_general(job
, cl
, psurf
, layer
, RENDER_TARGET_0
+ i
, bit
,
328 &stores_pending
, general_color_clear
);
331 if (job
->store
& PIPE_CLEAR_DEPTHSTENCIL
&& job
->zsbuf
&&
332 !(V3D_VERSION
< 40 && job
->zsbuf
->texture
->nr_samples
<= 1)) {
333 struct v3d_resource
*rsc
= v3d_resource(job
->zsbuf
->texture
);
334 if (rsc
->separate_stencil
) {
335 if (job
->store
& PIPE_CLEAR_DEPTH
) {
336 store_general(job
, cl
, job
->zsbuf
, layer
,
339 general_color_clear
);
342 if (job
->store
& PIPE_CLEAR_STENCIL
) {
343 store_general(job
, cl
, job
->zsbuf
, layer
,
344 STENCIL
, PIPE_CLEAR_STENCIL
,
346 general_color_clear
);
349 store_general(job
, cl
, job
->zsbuf
, layer
,
350 zs_buffer_from_pipe_bits(job
->store
),
351 job
->store
& PIPE_CLEAR_DEPTHSTENCIL
,
352 &stores_pending
, general_color_clear
);
357 if (stores_pending
) {
358 cl_emit(cl
, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED
, store
) {
360 store
.disable_color_buffer_write
=
362 PIPE_FIRST_COLOR_BUFFER_BIT
) & 0xf;
363 store
.enable_z_write
= stores_pending
& PIPE_CLEAR_DEPTH
;
364 store
.enable_stencil_write
= stores_pending
& PIPE_CLEAR_STENCIL
;
366 /* Note that when set this will clear all of the color
369 store
.disable_color_buffers_clear_on_write
=
371 store
.disable_z_buffer_clear_on_write
=
373 store
.disable_stencil_buffer_clear_on_write
=
376 } else if (needs_color_clear
&& !general_color_clear
) {
377 /* If we didn't do our color clears in the general packet,
378 * then emit a packet to clear all the TLB color buffers now.
380 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
381 store
.buffer_to_store
= NONE
;
384 #else /* V3D_VERSION >= 40 */
385 /* If we're emitting an RCL with GL_ARB_framebuffer_no_attachments,
386 * we still need to emit some sort of store.
389 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
390 store
.buffer_to_store
= NONE
;
394 assert(!stores_pending
);
396 /* GFXH-1461/GFXH-1689: The per-buffer store command's clear
397 * buffer bit is broken for depth/stencil. In addition, the
398 * clear packet's Z/S bit is broken, but the RTs bit ends up
402 cl_emit(cl
, CLEAR_TILE_BUFFERS
, clear
) {
403 clear
.clear_z_stencil_buffer
= true;
404 clear
.clear_all_render_targets
= true;
407 #endif /* V3D_VERSION >= 40 */
411 v3d_rcl_emit_generic_per_tile_list(struct v3d_job
*job
, int layer
)
413 /* Emit the generic list in our indirect state -- the rcl will just
414 * have pointers into it.
416 struct v3d_cl
*cl
= &job
->indirect
;
417 v3d_cl_ensure_space(cl
, 200, 1);
418 struct v3d_cl_reloc tile_list_start
= cl_get_address(cl
);
420 if (V3D_VERSION
>= 40) {
421 /* V3D 4.x only requires a single tile coordinates, and
422 * END_OF_LOADS switches us between loading and rendering.
424 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
427 v3d_rcl_emit_loads(job
, cl
, layer
);
429 if (V3D_VERSION
< 40) {
430 /* Tile Coordinates triggers the last reload and sets where
431 * the stores go. There must be one per store packet.
433 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
436 /* The binner starts out writing tiles assuming that the initial mode
437 * is triangles, so make sure that's the case.
439 cl_emit(cl
, PRIM_LIST_FORMAT
, fmt
) {
440 fmt
.primitive_type
= LIST_TRIANGLES
;
443 cl_emit(cl
, BRANCH_TO_IMPLICIT_TILE_LIST
, branch
);
445 v3d_rcl_emit_stores(job
, cl
, layer
);
447 #if V3D_VERSION >= 40
448 cl_emit(cl
, END_OF_TILE_MARKER
, end
);
451 cl_emit(cl
, RETURN_FROM_SUB_LIST
, ret
);
453 cl_emit(&job
->rcl
, START_ADDRESS_OF_GENERIC_TILE_LIST
, branch
) {
454 branch
.start
= tile_list_start
;
455 branch
.end
= cl_get_address(cl
);
459 #if V3D_VERSION >= 40
461 v3d_setup_render_target(struct v3d_job
*job
, int cbuf
,
462 uint32_t *rt_bpp
, uint32_t *rt_type
, uint32_t *rt_clamp
)
464 if (!job
->cbufs
[cbuf
])
467 struct v3d_surface
*surf
= v3d_surface(job
->cbufs
[cbuf
]);
468 *rt_bpp
= surf
->internal_bpp
;
469 *rt_type
= surf
->internal_type
;
470 *rt_clamp
= V3D_RENDER_TARGET_CLAMP_NONE
;
473 #else /* V3D_VERSION < 40 */
476 v3d_emit_z_stencil_config(struct v3d_job
*job
, struct v3d_surface
*surf
,
477 struct v3d_resource
*rsc
, bool is_separate_stencil
)
479 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_Z_STENCIL
, zs
) {
480 zs
.address
= cl_address(rsc
->bo
, surf
->offset
);
482 if (!is_separate_stencil
) {
483 zs
.internal_type
= surf
->internal_type
;
484 zs
.output_image_format
= surf
->format
;
486 zs
.z_stencil_id
= 1; /* Separate stencil */
489 zs
.padded_height_of_output_image_in_uif_blocks
=
490 surf
->padded_height_of_output_image_in_uif_blocks
;
492 assert(surf
->tiling
!= VC5_TILING_RASTER
);
493 zs
.memory_format
= surf
->tiling
;
496 if (job
->store
& (is_separate_stencil
?
498 PIPE_CLEAR_DEPTHSTENCIL
)) {
502 #endif /* V3D_VERSION < 40 */
504 #define div_round_up(a, b) (((a) + (b) - 1) / b)
507 emit_render_layer(struct v3d_job
*job
, uint32_t layer
)
509 uint32_t supertile_w
= 1, supertile_h
= 1;
511 /* If doing multicore binning, we would need to initialize each
512 * core's tile list here.
514 uint32_t tile_alloc_offset
=
515 layer
* job
->draw_tiles_x
* job
->draw_tiles_y
* 64;
516 cl_emit(&job
->rcl
, MULTICORE_RENDERING_TILE_LIST_SET_BASE
, list
) {
517 list
.address
= cl_address(job
->tile_alloc
, tile_alloc_offset
);
520 cl_emit(&job
->rcl
, MULTICORE_RENDERING_SUPERTILE_CFG
, config
) {
521 uint32_t frame_w_in_supertiles
, frame_h_in_supertiles
;
522 const uint32_t max_supertiles
= 256;
524 /* Size up our supertiles until we get under the limit. */
526 frame_w_in_supertiles
= div_round_up(job
->draw_tiles_x
,
528 frame_h_in_supertiles
= div_round_up(job
->draw_tiles_y
,
530 if (frame_w_in_supertiles
*
531 frame_h_in_supertiles
< max_supertiles
) {
535 if (supertile_w
< supertile_h
)
541 config
.number_of_bin_tile_lists
= 1;
542 config
.total_frame_width_in_tiles
= job
->draw_tiles_x
;
543 config
.total_frame_height_in_tiles
= job
->draw_tiles_y
;
545 config
.supertile_width_in_tiles
= supertile_w
;
546 config
.supertile_height_in_tiles
= supertile_h
;
548 config
.total_frame_width_in_supertiles
= frame_w_in_supertiles
;
549 config
.total_frame_height_in_supertiles
= frame_h_in_supertiles
;
552 /* Start by clearing the tile buffer. */
553 cl_emit(&job
->rcl
, TILE_COORDINATES
, coords
) {
554 coords
.tile_column_number
= 0;
555 coords
.tile_row_number
= 0;
558 /* Emit an initial clear of the tile buffers. This is necessary
559 * for any buffers that should be cleared (since clearing
560 * normally happens at the *end* of the generic tile list), but
561 * it's also nice to clear everything so the first tile doesn't
562 * inherit any contents from some previous frame.
564 * Also, implement the GFXH-1742 workaround. There's a race in
565 * the HW between the RCL updating the TLB's internal type/size
566 * and thespawning of the QPU instances using the TLB's current
567 * internal type/size. To make sure the QPUs get the right
568 * state, we need 1 dummy store in between internal type/size
569 * changes on V3D 3.x, and 2 dummy stores on 4.x.
572 cl_emit(&job
->rcl
, STORE_TILE_BUFFER_GENERAL
, store
) {
573 store
.buffer_to_store
= NONE
;
576 for (int i
= 0; i
< 2; i
++) {
578 cl_emit(&job
->rcl
, TILE_COORDINATES
, coords
);
579 cl_emit(&job
->rcl
, END_OF_LOADS
, end
);
580 cl_emit(&job
->rcl
, STORE_TILE_BUFFER_GENERAL
, store
) {
581 store
.buffer_to_store
= NONE
;
584 cl_emit(&job
->rcl
, CLEAR_TILE_BUFFERS
, clear
) {
585 clear
.clear_z_stencil_buffer
= true;
586 clear
.clear_all_render_targets
= true;
589 cl_emit(&job
->rcl
, END_OF_TILE_MARKER
, end
);
593 cl_emit(&job
->rcl
, FLUSH_VCD_CACHE
, flush
);
595 v3d_rcl_emit_generic_per_tile_list(job
, layer
);
597 /* XXX perf: We should expose GL_MESA_tile_raster_order to
598 * improve X11 performance, but we should use Morton order
599 * otherwise to improve cache locality.
601 uint32_t supertile_w_in_pixels
= job
->tile_width
* supertile_w
;
602 uint32_t supertile_h_in_pixels
= job
->tile_height
* supertile_h
;
603 uint32_t min_x_supertile
= job
->draw_min_x
/ supertile_w_in_pixels
;
604 uint32_t min_y_supertile
= job
->draw_min_y
/ supertile_h_in_pixels
;
606 uint32_t max_x_supertile
= 0;
607 uint32_t max_y_supertile
= 0;
608 if (job
->draw_max_x
!= 0 && job
->draw_max_y
!= 0) {
609 max_x_supertile
= (job
->draw_max_x
- 1) / supertile_w_in_pixels
;
610 max_y_supertile
= (job
->draw_max_y
- 1) / supertile_h_in_pixels
;
613 for (int y
= min_y_supertile
; y
<= max_y_supertile
; y
++) {
614 for (int x
= min_x_supertile
; x
<= max_x_supertile
; x
++) {
615 cl_emit(&job
->rcl
, SUPERTILE_COORDINATES
, coords
) {
616 coords
.column_number_in_supertiles
= x
;
617 coords
.row_number_in_supertiles
= y
;
624 v3dX(emit_rcl
)(struct v3d_job
*job
)
626 /* The RCL list should be empty. */
627 assert(!job
->rcl
.bo
);
629 v3d_cl_ensure_space_with_branch(&job
->rcl
, 200 +
630 MAX2(job
->num_layers
, 1) * 256 *
631 cl_packet_length(SUPERTILE_COORDINATES
));
632 job
->submit
.rcl_start
= job
->rcl
.bo
->offset
;
633 v3d_job_add_bo(job
, job
->rcl
.bo
);
636 for (int i
= 0; i
< V3D_MAX_DRAW_BUFFERS
; i
++) {
641 /* Comon config must be the first TILE_RENDERING_MODE_CFG
642 * and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
643 * optional updates to the previous HW state.
645 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_COMMON
, config
) {
647 config
.enable_z_store
= job
->store
& PIPE_CLEAR_DEPTH
;
648 config
.enable_stencil_store
= job
->store
& PIPE_CLEAR_STENCIL
;
649 #else /* V3D_VERSION >= 40 */
651 struct v3d_surface
*surf
= v3d_surface(job
->zsbuf
);
652 config
.internal_depth_type
= surf
->internal_type
;
654 #endif /* V3D_VERSION >= 40 */
656 /* XXX: Early D/S clear */
658 switch (job
->first_ez_state
) {
659 case VC5_EZ_UNDECIDED
:
661 config
.early_z_disable
= false;
662 config
.early_z_test_and_update_direction
=
663 EARLY_Z_DIRECTION_LT_LE
;
666 config
.early_z_disable
= false;
667 config
.early_z_test_and_update_direction
=
668 EARLY_Z_DIRECTION_GT_GE
;
670 case VC5_EZ_DISABLED
:
671 config
.early_z_disable
= true;
674 config
.image_width_pixels
= job
->draw_width
;
675 config
.image_height_pixels
= job
->draw_height
;
677 config
.number_of_render_targets
= MAX2(nr_cbufs
, 1);
679 config
.multisample_mode_4x
= job
->msaa
;
681 config
.maximum_bpp_of_all_render_targets
= job
->internal_bpp
;
684 for (int i
= 0; i
< nr_cbufs
; i
++) {
685 struct pipe_surface
*psurf
= job
->cbufs
[i
];
688 struct v3d_surface
*surf
= v3d_surface(psurf
);
689 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
691 UNUSED
uint32_t config_pad
= 0;
692 uint32_t clear_pad
= 0;
694 /* XXX: Set the pad for raster. */
695 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
696 surf
->tiling
== VC5_TILING_UIF_XOR
) {
697 int uif_block_height
= v3d_utile_height(rsc
->cpp
) * 2;
698 uint32_t implicit_padded_height
= (align(job
->draw_height
, uif_block_height
) /
700 if (surf
->padded_height_of_output_image_in_uif_blocks
-
701 implicit_padded_height
< 15) {
702 config_pad
= (surf
->padded_height_of_output_image_in_uif_blocks
-
703 implicit_padded_height
);
706 clear_pad
= surf
->padded_height_of_output_image_in_uif_blocks
;
711 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_COLOR
, rt
) {
712 rt
.address
= cl_address(rsc
->bo
, surf
->offset
);
713 rt
.internal_type
= surf
->internal_type
;
714 rt
.output_image_format
= surf
->format
;
715 rt
.memory_format
= surf
->tiling
;
716 rt
.internal_bpp
= surf
->internal_bpp
;
717 rt
.render_target_number
= i
;
720 if (job
->store
& PIPE_CLEAR_COLOR0
<< i
)
723 #endif /* V3D_VERSION < 40 */
725 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1
,
727 clear
.clear_color_low_32_bits
= job
->clear_color
[i
][0];
728 clear
.clear_color_next_24_bits
= job
->clear_color
[i
][1] & 0xffffff;
729 clear
.render_target_number
= i
;
732 if (surf
->internal_bpp
>= V3D_INTERNAL_BPP_64
) {
733 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2
,
735 clear
.clear_color_mid_low_32_bits
=
736 ((job
->clear_color
[i
][1] >> 24) |
737 (job
->clear_color
[i
][2] << 8));
738 clear
.clear_color_mid_high_24_bits
=
739 ((job
->clear_color
[i
][2] >> 24) |
740 ((job
->clear_color
[i
][3] & 0xffff) << 8));
741 clear
.render_target_number
= i
;
745 if (surf
->internal_bpp
>= V3D_INTERNAL_BPP_128
|| clear_pad
) {
746 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3
,
748 clear
.uif_padded_height_in_uif_blocks
= clear_pad
;
749 clear
.clear_color_high_16_bits
= job
->clear_color
[i
][3] >> 16;
750 clear
.render_target_number
= i
;
755 #if V3D_VERSION >= 40
756 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_COLOR
, rt
) {
757 v3d_setup_render_target(job
, 0,
758 &rt
.render_target_0_internal_bpp
,
759 &rt
.render_target_0_internal_type
,
760 &rt
.render_target_0_clamp
);
761 v3d_setup_render_target(job
, 1,
762 &rt
.render_target_1_internal_bpp
,
763 &rt
.render_target_1_internal_type
,
764 &rt
.render_target_1_clamp
);
765 v3d_setup_render_target(job
, 2,
766 &rt
.render_target_2_internal_bpp
,
767 &rt
.render_target_2_internal_type
,
768 &rt
.render_target_2_clamp
);
769 v3d_setup_render_target(job
, 3,
770 &rt
.render_target_3_internal_bpp
,
771 &rt
.render_target_3_internal_type
,
772 &rt
.render_target_3_clamp
);
777 /* TODO: Don't bother emitting if we don't load/clear Z/S. */
779 struct pipe_surface
*psurf
= job
->zsbuf
;
780 struct v3d_surface
*surf
= v3d_surface(psurf
);
781 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
783 v3d_emit_z_stencil_config(job
, surf
, rsc
, false);
785 /* Emit the separate stencil packet if we have a resource for
786 * it. The HW will only load/store this buffer if the
787 * Z/Stencil config doesn't have stencil in its format.
789 if (surf
->separate_stencil
) {
790 v3d_emit_z_stencil_config(job
,
791 v3d_surface(surf
->separate_stencil
),
792 rsc
->separate_stencil
, true);
795 #endif /* V3D_VERSION < 40 */
797 /* Ends rendering mode config. */
798 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES
,
800 clear
.z_clear_value
= job
->clear_z
;
801 clear
.stencil_clear_value
= job
->clear_s
;
804 /* Always set initial block size before the first branch, which needs
805 * to match the value from binning mode config.
807 cl_emit(&job
->rcl
, TILE_LIST_INITIAL_BLOCK_SIZE
, init
) {
808 init
.use_auto_chained_tile_lists
= true;
809 init
.size_of_first_block_in_chained_tile_lists
=
810 TILE_ALLOCATION_BLOCK_SIZE_64B
;
813 /* ARB_framebuffer_no_attachments allows rendering to happen even when
814 * the framebuffer has no attachments, the idea being that fragment
815 * shaders can still do image load/store, ssbo, etc without having to
816 * write to actual attachments, so always run at least one iteration
819 assert(job
->num_layers
> 0 || (job
->load
== 0 && job
->store
== 0));
820 for (int layer
= 0; layer
< MAX2(1, job
->num_layers
); layer
++)
821 emit_render_layer(job
, layer
);
823 cl_emit(&job
->rcl
, END_OF_RENDERING
, end
);