2 * Copyright © 2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/u_format.h"
25 #include "v3d_context.h"
26 #include "v3d_tiling.h"
27 #include "broadcom/common/v3d_macros.h"
28 #include "broadcom/cle/v3dx_pack.h"
30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 | \
35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
37 /* The HW queues up the load until the tile coordinates show up, but can only
38 * track one at a time. If we need to do more than one load, then we need to
39 * flush out the previous load by emitting the tile coordinates and doing a
43 flush_last_load(struct v3d_cl
*cl
)
45 if (V3D_VERSION
>= 40)
48 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
49 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
50 store
.buffer_to_store
= NONE
;
55 load_general(struct v3d_cl
*cl
, struct pipe_surface
*psurf
, int buffer
,
56 uint32_t pipe_bit
, uint32_t *loads_pending
)
58 struct v3d_surface
*surf
= v3d_surface(psurf
);
59 bool separate_stencil
= surf
->separate_stencil
&& buffer
== STENCIL
;
60 if (separate_stencil
) {
61 psurf
= surf
->separate_stencil
;
62 surf
= v3d_surface(psurf
);
65 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
67 cl_emit(cl
, LOAD_TILE_BUFFER_GENERAL
, load
) {
68 load
.buffer_to_load
= buffer
;
69 load
.address
= cl_address(rsc
->bo
, surf
->offset
);
72 load
.memory_format
= surf
->tiling
;
74 load
.input_image_format
= V3D_OUTPUT_IMAGE_FORMAT_S8
;
76 load
.input_image_format
= surf
->format
;
78 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
79 surf
->tiling
== VC5_TILING_UIF_XOR
) {
80 load
.height_in_ub_or_stride
=
81 surf
->padded_height_of_output_image_in_uif_blocks
;
82 } else if (surf
->tiling
== VC5_TILING_RASTER
) {
83 struct v3d_resource_slice
*slice
=
84 &rsc
->slices
[psurf
->u
.tex
.level
];
85 load
.height_in_ub_or_stride
= slice
->stride
;
88 if (psurf
->texture
->nr_samples
> 1)
89 load
.decimate_mode
= V3D_DECIMATE_MODE_ALL_SAMPLES
;
91 load
.decimate_mode
= V3D_DECIMATE_MODE_SAMPLE_0
;
93 #else /* V3D_VERSION < 40 */
94 /* Can't do raw ZSTENCIL loads -- need to load/store them to
95 * separate buffers for Z and stencil.
97 assert(buffer
!= ZSTENCIL
);
99 load
.padded_height_of_output_image_in_uif_blocks
=
100 surf
->padded_height_of_output_image_in_uif_blocks
;
101 #endif /* V3D_VERSION < 40 */
104 *loads_pending
&= ~pipe_bit
;
110 store_general(struct v3d_job
*job
,
111 struct v3d_cl
*cl
, struct pipe_surface
*psurf
, int buffer
,
112 int pipe_bit
, uint32_t *stores_pending
, bool general_color_clear
)
114 struct v3d_surface
*surf
= v3d_surface(psurf
);
115 bool separate_stencil
= surf
->separate_stencil
&& buffer
== STENCIL
;
116 if (separate_stencil
) {
117 psurf
= surf
->separate_stencil
;
118 surf
= v3d_surface(psurf
);
121 *stores_pending
&= ~pipe_bit
;
122 bool last_store
= !(*stores_pending
);
124 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
128 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
129 store
.buffer_to_store
= buffer
;
130 store
.address
= cl_address(rsc
->bo
, surf
->offset
);
132 #if V3D_VERSION >= 40
133 store
.clear_buffer_being_stored
=
134 ((job
->cleared
& pipe_bit
) &&
135 (general_color_clear
||
136 !(pipe_bit
& PIPE_CLEAR_COLOR_BUFFERS
)));
138 if (separate_stencil
)
139 store
.output_image_format
= V3D_OUTPUT_IMAGE_FORMAT_S8
;
141 store
.output_image_format
= surf
->format
;
143 store
.memory_format
= surf
->tiling
;
145 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
146 surf
->tiling
== VC5_TILING_UIF_XOR
) {
147 store
.height_in_ub_or_stride
=
148 surf
->padded_height_of_output_image_in_uif_blocks
;
149 } else if (surf
->tiling
== VC5_TILING_RASTER
) {
150 struct v3d_resource_slice
*slice
=
151 &rsc
->slices
[psurf
->u
.tex
.level
];
152 store
.height_in_ub_or_stride
= slice
->stride
;
155 if (psurf
->texture
->nr_samples
> 1)
156 store
.decimate_mode
= V3D_DECIMATE_MODE_ALL_SAMPLES
;
158 store
.decimate_mode
= V3D_DECIMATE_MODE_SAMPLE_0
;
160 #else /* V3D_VERSION < 40 */
161 /* Can't do raw ZSTENCIL stores -- need to load/store them to
162 * separate buffers for Z and stencil.
164 assert(buffer
!= ZSTENCIL
);
165 store
.raw_mode
= true;
167 store
.disable_colour_buffers_clear_on_write
= true;
168 store
.disable_z_buffer_clear_on_write
= true;
169 store
.disable_stencil_buffer_clear_on_write
= true;
171 store
.disable_colour_buffers_clear_on_write
=
172 !(((pipe_bit
& PIPE_CLEAR_COLOR_BUFFERS
) &&
173 general_color_clear
&&
174 (job
->cleared
& pipe_bit
)));
175 store
.disable_z_buffer_clear_on_write
=
176 !(job
->cleared
& PIPE_CLEAR_DEPTH
);
177 store
.disable_stencil_buffer_clear_on_write
=
178 !(job
->cleared
& PIPE_CLEAR_STENCIL
);
180 store
.padded_height_of_output_image_in_uif_blocks
=
181 surf
->padded_height_of_output_image_in_uif_blocks
;
182 #endif /* V3D_VERSION < 40 */
185 /* There must be a TILE_COORDINATES_IMPLICIT between each store. */
186 if (V3D_VERSION
< 40 && !last_store
) {
187 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
192 zs_buffer_from_pipe_bits(int pipe_clear_bits
)
194 switch (pipe_clear_bits
& PIPE_CLEAR_DEPTHSTENCIL
) {
195 case PIPE_CLEAR_DEPTHSTENCIL
:
197 case PIPE_CLEAR_DEPTH
:
199 case PIPE_CLEAR_STENCIL
:
207 v3d_rcl_emit_loads(struct v3d_job
*job
, struct v3d_cl
*cl
)
209 uint32_t loads_pending
= job
->resolve
& ~job
->cleared
;
211 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
212 uint32_t bit
= PIPE_CLEAR_COLOR0
<< i
;
213 if (!(loads_pending
& bit
))
216 struct pipe_surface
*psurf
= job
->cbufs
[i
];
217 if (!psurf
|| (V3D_VERSION
< 40 &&
218 psurf
->texture
->nr_samples
<= 1)) {
222 load_general(cl
, psurf
, RENDER_TARGET_0
+ i
,
223 bit
, &loads_pending
);
226 if ((loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
) &&
227 (V3D_VERSION
>= 40 ||
228 (job
->zsbuf
&& job
->zsbuf
->texture
->nr_samples
> 1))) {
229 struct v3d_resource
*rsc
= v3d_resource(job
->zsbuf
->texture
);
231 if (rsc
->separate_stencil
&&
232 (loads_pending
& PIPE_CLEAR_STENCIL
)) {
233 load_general(cl
, job
->zsbuf
,
239 if (loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
) {
240 load_general(cl
, job
->zsbuf
,
241 zs_buffer_from_pipe_bits(loads_pending
),
242 loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
,
248 /* The initial reload will be queued until we get the
252 cl_emit(cl
, RELOAD_TILE_COLOUR_BUFFER
, load
) {
253 load
.disable_colour_buffer_load
=
255 PIPE_CLEAR_COLOR_BUFFERS
) >>
256 PIPE_FIRST_COLOR_BUFFER_BIT
;
258 loads_pending
& PIPE_CLEAR_DEPTH
;
259 load
.enable_stencil_load
=
260 loads_pending
& PIPE_CLEAR_STENCIL
;
263 #else /* V3D_VERSION >= 40 */
264 assert(!loads_pending
);
265 cl_emit(cl
, END_OF_LOADS
, end
);
270 v3d_rcl_emit_stores(struct v3d_job
*job
, struct v3d_cl
*cl
)
272 MAYBE_UNUSED
bool needs_color_clear
= job
->cleared
& PIPE_CLEAR_COLOR_BUFFERS
;
273 MAYBE_UNUSED
bool needs_z_clear
= job
->cleared
& PIPE_CLEAR_DEPTH
;
274 MAYBE_UNUSED
bool needs_s_clear
= job
->cleared
& PIPE_CLEAR_STENCIL
;
276 /* For clearing color in a TLB general on V3D 3.3:
278 * - NONE buffer store clears all TLB color buffers.
279 * - color buffer store clears just the TLB color buffer being stored.
280 * - Z/S buffers store may not clear the TLB color buffer.
282 * And on V3D 4.1, we only have one flag for "clear the buffer being
283 * stored" in the general packet, and a separate packet to clear all
286 * As a result, we only bother flagging TLB color clears in a general
287 * packet when we don't have to emit a separate packet to clear all
290 bool general_color_clear
= (needs_color_clear
&&
291 (job
->cleared
& PIPE_CLEAR_COLOR_BUFFERS
) ==
292 (job
->resolve
& PIPE_CLEAR_COLOR_BUFFERS
));
294 uint32_t stores_pending
= job
->resolve
;
296 /* For V3D 4.1, use general stores for all TLB stores.
298 * For V3D 3.3, we only use general stores to do raw stores for any
299 * MSAA surfaces. These output UIF tiled images where each 4x MSAA
300 * pixel is a 2x2 quad, and the format will be that of the
301 * internal_type/internal_bpp, rather than the format from GL's
302 * perspective. Non-MSAA surfaces will use
303 * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
305 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
306 uint32_t bit
= PIPE_CLEAR_COLOR0
<< i
;
307 if (!(job
->resolve
& bit
))
310 struct pipe_surface
*psurf
= job
->cbufs
[i
];
312 (V3D_VERSION
< 40 && psurf
->texture
->nr_samples
<= 1)) {
316 store_general(job
, cl
, psurf
, RENDER_TARGET_0
+ i
, bit
,
317 &stores_pending
, general_color_clear
);
320 if (job
->resolve
& PIPE_CLEAR_DEPTHSTENCIL
&& job
->zsbuf
&&
321 !(V3D_VERSION
< 40 && job
->zsbuf
->texture
->nr_samples
<= 1)) {
322 struct v3d_resource
*rsc
= v3d_resource(job
->zsbuf
->texture
);
323 if (rsc
->separate_stencil
) {
324 if (job
->resolve
& PIPE_CLEAR_DEPTH
) {
325 store_general(job
, cl
, job
->zsbuf
, Z
,
328 general_color_clear
);
331 if (job
->resolve
& PIPE_CLEAR_STENCIL
) {
332 store_general(job
, cl
, job
->zsbuf
, STENCIL
,
335 general_color_clear
);
338 store_general(job
, cl
, job
->zsbuf
,
339 zs_buffer_from_pipe_bits(job
->resolve
),
340 job
->resolve
& PIPE_CLEAR_DEPTHSTENCIL
,
341 &stores_pending
, general_color_clear
);
345 if (stores_pending
) {
347 cl_emit(cl
, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED
, store
) {
349 store
.disable_color_buffer_write
=
351 PIPE_FIRST_COLOR_BUFFER_BIT
) & 0xf;
352 store
.enable_z_write
= stores_pending
& PIPE_CLEAR_DEPTH
;
353 store
.enable_stencil_write
= stores_pending
& PIPE_CLEAR_STENCIL
;
355 /* Note that when set this will clear all of the color
358 store
.disable_colour_buffers_clear_on_write
=
360 store
.disable_z_buffer_clear_on_write
=
362 store
.disable_stencil_buffer_clear_on_write
=
365 #else /* V3D_VERSION >= 40 */
366 unreachable("All color buffers should have been stored.");
367 #endif /* V3D_VERSION >= 40 */
368 } else if (needs_color_clear
&& !general_color_clear
) {
369 /* If we didn't do our color clears in the general packet,
370 * then emit a packet to clear all the TLB color buffers now.
373 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
374 store
.buffer_to_store
= NONE
;
376 #else /* V3D_VERSION >= 40 */
377 cl_emit(cl
, CLEAR_TILE_BUFFERS
, clear
) {
378 clear
.clear_all_render_targets
= true;
380 #endif /* V3D_VERSION >= 40 */
385 v3d_rcl_emit_generic_per_tile_list(struct v3d_job
*job
, int last_cbuf
)
387 /* Emit the generic list in our indirect state -- the rcl will just
388 * have pointers into it.
390 struct v3d_cl
*cl
= &job
->indirect
;
391 v3d_cl_ensure_space(cl
, 200, 1);
392 struct v3d_cl_reloc tile_list_start
= cl_get_address(cl
);
394 if (V3D_VERSION
>= 40) {
395 /* V3D 4.x only requires a single tile coordinates, and
396 * END_OF_LOADS switches us between loading and rendering.
398 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
401 v3d_rcl_emit_loads(job
, cl
);
403 if (V3D_VERSION
< 40) {
404 /* Tile Coordinates triggers the last reload and sets where
405 * the stores go. There must be one per store packet.
407 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
410 /* The binner starts out writing tiles assuming that the initial mode
411 * is triangles, so make sure that's the case.
413 cl_emit(cl
, PRIMITIVE_LIST_FORMAT
, fmt
) {
414 fmt
.data_type
= LIST_INDEXED
;
415 fmt
.primitive_type
= LIST_TRIANGLES
;
418 cl_emit(cl
, BRANCH_TO_IMPLICIT_TILE_LIST
, branch
);
420 v3d_rcl_emit_stores(job
, cl
);
422 #if V3D_VERSION >= 40
423 cl_emit(cl
, END_OF_TILE_MARKER
, end
);
426 cl_emit(cl
, RETURN_FROM_SUB_LIST
, ret
);
428 cl_emit(&job
->rcl
, START_ADDRESS_OF_GENERIC_TILE_LIST
, branch
) {
429 branch
.start
= tile_list_start
;
430 branch
.end
= cl_get_address(cl
);
434 #if V3D_VERSION >= 40
436 v3d_setup_render_target(struct v3d_job
*job
, int cbuf
,
437 uint32_t *rt_bpp
, uint32_t *rt_type
, uint32_t *rt_clamp
)
439 if (!job
->cbufs
[cbuf
])
442 struct v3d_surface
*surf
= v3d_surface(job
->cbufs
[cbuf
]);
443 *rt_bpp
= surf
->internal_bpp
;
444 *rt_type
= surf
->internal_type
;
445 *rt_clamp
= V3D_RENDER_TARGET_CLAMP_NONE
;
448 #else /* V3D_VERSION < 40 */
451 v3d_emit_z_stencil_config(struct v3d_job
*job
, struct v3d_surface
*surf
,
452 struct v3d_resource
*rsc
, bool is_separate_stencil
)
454 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CONFIG
, zs
) {
455 zs
.address
= cl_address(rsc
->bo
, surf
->offset
);
457 if (!is_separate_stencil
) {
458 zs
.internal_type
= surf
->internal_type
;
459 zs
.output_image_format
= surf
->format
;
461 zs
.z_stencil_id
= 1; /* Separate stencil */
464 zs
.padded_height_of_output_image_in_uif_blocks
=
465 surf
->padded_height_of_output_image_in_uif_blocks
;
467 assert(surf
->tiling
!= VC5_TILING_RASTER
);
468 zs
.memory_format
= surf
->tiling
;
471 if (job
->resolve
& (is_separate_stencil
?
473 PIPE_CLEAR_DEPTHSTENCIL
)) {
477 #endif /* V3D_VERSION < 40 */
479 #define div_round_up(a, b) (((a) + (b) - 1) / b)
482 v3dX(emit_rcl
)(struct v3d_job
*job
)
484 /* The RCL list should be empty. */
485 assert(!job
->rcl
.bo
);
487 v3d_cl_ensure_space_with_branch(&job
->rcl
, 200 + 256 *
488 cl_packet_length(SUPERTILE_COORDINATES
));
489 job
->submit
.rcl_start
= job
->rcl
.bo
->offset
;
490 v3d_job_add_bo(job
, job
->rcl
.bo
);
493 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
498 /* Comon config must be the first TILE_RENDERING_MODE_CONFIGURATION
499 * and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
500 * optional updates to the previous HW state.
502 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION
,
505 config
.enable_z_store
= job
->resolve
& PIPE_CLEAR_DEPTH
;
506 config
.enable_stencil_store
= job
->resolve
& PIPE_CLEAR_STENCIL
;
507 #else /* V3D_VERSION >= 40 */
509 struct v3d_surface
*surf
= v3d_surface(job
->zsbuf
);
510 config
.internal_depth_type
= surf
->internal_type
;
512 #endif /* V3D_VERSION >= 40 */
514 /* XXX: Early D/S clear */
516 switch (job
->first_ez_state
) {
517 case VC5_EZ_UNDECIDED
:
519 config
.early_z_disable
= false;
520 config
.early_z_test_and_update_direction
=
521 EARLY_Z_DIRECTION_LT_LE
;
524 config
.early_z_disable
= false;
525 config
.early_z_test_and_update_direction
=
526 EARLY_Z_DIRECTION_GT_GE
;
528 case VC5_EZ_DISABLED
:
529 config
.early_z_disable
= true;
532 config
.image_width_pixels
= job
->draw_width
;
533 config
.image_height_pixels
= job
->draw_height
;
535 config
.number_of_render_targets_minus_1
=
536 MAX2(nr_cbufs
, 1) - 1;
538 config
.multisample_mode_4x
= job
->msaa
;
540 config
.maximum_bpp_of_all_render_targets
= job
->internal_bpp
;
543 for (int i
= 0; i
< nr_cbufs
; i
++) {
544 struct pipe_surface
*psurf
= job
->cbufs
[i
];
547 struct v3d_surface
*surf
= v3d_surface(psurf
);
548 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
550 MAYBE_UNUSED
uint32_t config_pad
= 0;
551 uint32_t clear_pad
= 0;
553 /* XXX: Set the pad for raster. */
554 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
555 surf
->tiling
== VC5_TILING_UIF_XOR
) {
556 int uif_block_height
= v3d_utile_height(rsc
->cpp
) * 2;
557 uint32_t implicit_padded_height
= (align(job
->draw_height
, uif_block_height
) /
559 if (surf
->padded_height_of_output_image_in_uif_blocks
-
560 implicit_padded_height
< 15) {
561 config_pad
= (surf
->padded_height_of_output_image_in_uif_blocks
-
562 implicit_padded_height
);
565 clear_pad
= surf
->padded_height_of_output_image_in_uif_blocks
;
570 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG
, rt
) {
571 rt
.address
= cl_address(rsc
->bo
, surf
->offset
);
572 rt
.internal_type
= surf
->internal_type
;
573 rt
.output_image_format
= surf
->format
;
574 rt
.memory_format
= surf
->tiling
;
575 rt
.internal_bpp
= surf
->internal_bpp
;
576 rt
.render_target_number
= i
;
579 if (job
->resolve
& PIPE_CLEAR_COLOR0
<< i
)
582 #endif /* V3D_VERSION < 40 */
584 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1
,
586 clear
.clear_color_low_32_bits
= job
->clear_color
[i
][0];
587 clear
.clear_color_next_24_bits
= job
->clear_color
[i
][1] & 0xffffff;
588 clear
.render_target_number
= i
;
591 if (surf
->internal_bpp
>= V3D_INTERNAL_BPP_64
) {
592 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2
,
594 clear
.clear_color_mid_low_32_bits
=
595 ((job
->clear_color
[i
][1] >> 24) |
596 (job
->clear_color
[i
][2] << 8));
597 clear
.clear_color_mid_high_24_bits
=
598 ((job
->clear_color
[i
][2] >> 24) |
599 ((job
->clear_color
[i
][3] & 0xffff) << 8));
600 clear
.render_target_number
= i
;
604 if (surf
->internal_bpp
>= V3D_INTERNAL_BPP_128
|| clear_pad
) {
605 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3
,
607 clear
.uif_padded_height_in_uif_blocks
= clear_pad
;
608 clear
.clear_color_high_16_bits
= job
->clear_color
[i
][3] >> 16;
609 clear
.render_target_number
= i
;
614 #if V3D_VERSION >= 40
615 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG
, rt
) {
616 v3d_setup_render_target(job
, 0,
617 &rt
.render_target_0_internal_bpp
,
618 &rt
.render_target_0_internal_type
,
619 &rt
.render_target_0_clamp
);
620 v3d_setup_render_target(job
, 1,
621 &rt
.render_target_1_internal_bpp
,
622 &rt
.render_target_1_internal_type
,
623 &rt
.render_target_1_clamp
);
624 v3d_setup_render_target(job
, 2,
625 &rt
.render_target_2_internal_bpp
,
626 &rt
.render_target_2_internal_type
,
627 &rt
.render_target_2_clamp
);
628 v3d_setup_render_target(job
, 3,
629 &rt
.render_target_3_internal_bpp
,
630 &rt
.render_target_3_internal_type
,
631 &rt
.render_target_3_clamp
);
636 /* TODO: Don't bother emitting if we don't load/clear Z/S. */
638 struct pipe_surface
*psurf
= job
->zsbuf
;
639 struct v3d_surface
*surf
= v3d_surface(psurf
);
640 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
642 v3d_emit_z_stencil_config(job
, surf
, rsc
, false);
644 /* Emit the separate stencil packet if we have a resource for
645 * it. The HW will only load/store this buffer if the
646 * Z/Stencil config doesn't have stencil in its format.
648 if (surf
->separate_stencil
) {
649 v3d_emit_z_stencil_config(job
,
650 v3d_surface(surf
->separate_stencil
),
651 rsc
->separate_stencil
, true);
654 #endif /* V3D_VERSION < 40 */
656 /* Ends rendering mode config. */
657 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES
,
659 clear
.z_clear_value
= job
->clear_z
;
660 clear
.stencil_vg_mask_clear_value
= job
->clear_s
;
663 /* Always set initial block size before the first branch, which needs
664 * to match the value from binning mode config.
666 cl_emit(&job
->rcl
, TILE_LIST_INITIAL_BLOCK_SIZE
, init
) {
667 init
.use_auto_chained_tile_lists
= true;
668 init
.size_of_first_block_in_chained_tile_lists
=
669 TILE_ALLOCATION_BLOCK_SIZE_64B
;
672 uint32_t supertile_w
= 1, supertile_h
= 1;
674 /* If doing multicore binning, we would need to initialize each core's
677 cl_emit(&job
->rcl
, MULTICORE_RENDERING_TILE_LIST_SET_BASE
, list
) {
678 list
.address
= cl_address(job
->tile_alloc
, 0);
681 cl_emit(&job
->rcl
, MULTICORE_RENDERING_SUPERTILE_CONFIGURATION
, config
) {
682 uint32_t frame_w_in_supertiles
, frame_h_in_supertiles
;
683 const uint32_t max_supertiles
= 256;
685 /* Size up our supertiles until we get under the limit. */
687 frame_w_in_supertiles
= div_round_up(job
->draw_tiles_x
,
689 frame_h_in_supertiles
= div_round_up(job
->draw_tiles_y
,
691 if (frame_w_in_supertiles
* frame_h_in_supertiles
<
696 if (supertile_w
< supertile_h
)
702 config
.total_frame_width_in_tiles
= job
->draw_tiles_x
;
703 config
.total_frame_height_in_tiles
= job
->draw_tiles_y
;
705 config
.supertile_width_in_tiles_minus_1
= supertile_w
- 1;
706 config
.supertile_height_in_tiles_minus_1
= supertile_h
- 1;
708 config
.total_frame_width_in_supertiles
= frame_w_in_supertiles
;
709 config
.total_frame_height_in_supertiles
= frame_h_in_supertiles
;
712 /* Start by clearing the tile buffer. */
713 cl_emit(&job
->rcl
, TILE_COORDINATES
, coords
) {
714 coords
.tile_column_number
= 0;
715 coords
.tile_row_number
= 0;
718 /* Emit an initial clear of the tile buffers. This is necessary for
719 * any buffers that should be cleared (since clearing normally happens
720 * at the *end* of the generic tile list), but it's also nice to clear
721 * everything so the first tile doesn't inherit any contents from some
724 * Also, implement the GFXH-1742 workaround. There's a race in the HW
725 * between the RCL updating the TLB's internal type/size and the
726 * spawning of the QPU instances using the TLB's current internal
727 * type/size. To make sure the QPUs get the right state,, we need 1
728 * dummy store in between internal type/size changes on V3D 3.x, and 2
729 * dummy stores on 4.x.
732 cl_emit(&job
->rcl
, STORE_TILE_BUFFER_GENERAL
, store
) {
733 store
.buffer_to_store
= NONE
;
736 for (int i
= 0; i
< 2; i
++) {
738 cl_emit(&job
->rcl
, TILE_COORDINATES
, coords
);
739 cl_emit(&job
->rcl
, END_OF_LOADS
, end
);
740 cl_emit(&job
->rcl
, STORE_TILE_BUFFER_GENERAL
, store
) {
741 store
.buffer_to_store
= NONE
;
744 cl_emit(&job
->rcl
, CLEAR_TILE_BUFFERS
, clear
) {
745 clear
.clear_z_stencil_buffer
= true;
746 clear
.clear_all_render_targets
= true;
749 cl_emit(&job
->rcl
, END_OF_TILE_MARKER
, end
);
753 cl_emit(&job
->rcl
, FLUSH_VCD_CACHE
, flush
);
755 v3d_rcl_emit_generic_per_tile_list(job
, nr_cbufs
- 1);
757 cl_emit(&job
->rcl
, WAIT_ON_SEMAPHORE
, sem
);
759 /* XXX: Use Morton order */
760 uint32_t supertile_w_in_pixels
= job
->tile_width
* supertile_w
;
761 uint32_t supertile_h_in_pixels
= job
->tile_height
* supertile_h
;
762 uint32_t min_x_supertile
= job
->draw_min_x
/ supertile_w_in_pixels
;
763 uint32_t min_y_supertile
= job
->draw_min_y
/ supertile_h_in_pixels
;
765 uint32_t max_x_supertile
= 0;
766 uint32_t max_y_supertile
= 0;
767 if (job
->draw_max_x
!= 0 && job
->draw_max_y
!= 0) {
768 max_x_supertile
= (job
->draw_max_x
- 1) / supertile_w_in_pixels
;
769 max_y_supertile
= (job
->draw_max_y
- 1) / supertile_h_in_pixels
;
772 for (int y
= min_y_supertile
; y
<= max_y_supertile
; y
++) {
773 for (int x
= min_x_supertile
; x
<= max_x_supertile
; x
++) {
774 cl_emit(&job
->rcl
, SUPERTILE_COORDINATES
, coords
) {
775 coords
.column_number_in_supertiles
= x
;
776 coords
.row_number_in_supertiles
= y
;
781 cl_emit(&job
->rcl
, END_OF_RENDERING
, end
);