2 * Copyright © 2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/u_format.h"
25 #include "v3d_context.h"
26 #include "v3d_tiling.h"
27 #include "broadcom/common/v3d_macros.h"
28 #include "broadcom/cle/v3dx_pack.h"
30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 | \
35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
37 /* The HW queues up the load until the tile coordinates show up, but can only
38 * track one at a time. If we need to do more than one load, then we need to
39 * flush out the previous load by emitting the tile coordinates and doing a
43 flush_last_load(struct v3d_cl
*cl
)
45 if (V3D_VERSION
>= 40)
48 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
49 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
50 store
.buffer_to_store
= NONE
;
55 load_general(struct v3d_cl
*cl
, struct pipe_surface
*psurf
, int buffer
,
56 uint32_t pipe_bit
, uint32_t *loads_pending
)
58 struct v3d_surface
*surf
= v3d_surface(psurf
);
59 bool separate_stencil
= surf
->separate_stencil
&& buffer
== STENCIL
;
60 if (separate_stencil
) {
61 psurf
= surf
->separate_stencil
;
62 surf
= v3d_surface(psurf
);
65 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
67 cl_emit(cl
, LOAD_TILE_BUFFER_GENERAL
, load
) {
68 load
.buffer_to_load
= buffer
;
69 load
.address
= cl_address(rsc
->bo
, surf
->offset
);
72 load
.memory_format
= surf
->tiling
;
74 load
.input_image_format
= V3D_OUTPUT_IMAGE_FORMAT_S8
;
76 load
.input_image_format
= surf
->format
;
77 load
.r_b_swap
= surf
->swap_rb
;
79 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
80 surf
->tiling
== VC5_TILING_UIF_XOR
) {
81 load
.height_in_ub_or_stride
=
82 surf
->padded_height_of_output_image_in_uif_blocks
;
83 } else if (surf
->tiling
== VC5_TILING_RASTER
) {
84 struct v3d_resource_slice
*slice
=
85 &rsc
->slices
[psurf
->u
.tex
.level
];
86 load
.height_in_ub_or_stride
= slice
->stride
;
89 if (psurf
->texture
->nr_samples
> 1)
90 load
.decimate_mode
= V3D_DECIMATE_MODE_ALL_SAMPLES
;
92 load
.decimate_mode
= V3D_DECIMATE_MODE_SAMPLE_0
;
94 #else /* V3D_VERSION < 40 */
95 /* Can't do raw ZSTENCIL loads -- need to load/store them to
96 * separate buffers for Z and stencil.
98 assert(buffer
!= ZSTENCIL
);
100 load
.padded_height_of_output_image_in_uif_blocks
=
101 surf
->padded_height_of_output_image_in_uif_blocks
;
102 #endif /* V3D_VERSION < 40 */
105 *loads_pending
&= ~pipe_bit
;
111 store_general(struct v3d_job
*job
,
112 struct v3d_cl
*cl
, struct pipe_surface
*psurf
, int buffer
,
113 int pipe_bit
, uint32_t *stores_pending
, bool general_color_clear
)
115 struct v3d_surface
*surf
= v3d_surface(psurf
);
116 bool separate_stencil
= surf
->separate_stencil
&& buffer
== STENCIL
;
117 if (separate_stencil
) {
118 psurf
= surf
->separate_stencil
;
119 surf
= v3d_surface(psurf
);
122 *stores_pending
&= ~pipe_bit
;
123 bool last_store
= !(*stores_pending
);
125 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
129 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
130 store
.buffer_to_store
= buffer
;
131 store
.address
= cl_address(rsc
->bo
, surf
->offset
);
133 #if V3D_VERSION >= 40
134 store
.clear_buffer_being_stored
= false;
136 if (separate_stencil
)
137 store
.output_image_format
= V3D_OUTPUT_IMAGE_FORMAT_S8
;
139 store
.output_image_format
= surf
->format
;
141 store
.r_b_swap
= surf
->swap_rb
;
142 store
.memory_format
= surf
->tiling
;
144 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
145 surf
->tiling
== VC5_TILING_UIF_XOR
) {
146 store
.height_in_ub_or_stride
=
147 surf
->padded_height_of_output_image_in_uif_blocks
;
148 } else if (surf
->tiling
== VC5_TILING_RASTER
) {
149 struct v3d_resource_slice
*slice
=
150 &rsc
->slices
[psurf
->u
.tex
.level
];
151 store
.height_in_ub_or_stride
= slice
->stride
;
154 if (psurf
->texture
->nr_samples
> 1)
155 store
.decimate_mode
= V3D_DECIMATE_MODE_ALL_SAMPLES
;
157 store
.decimate_mode
= V3D_DECIMATE_MODE_SAMPLE_0
;
159 #else /* V3D_VERSION < 40 */
160 /* Can't do raw ZSTENCIL stores -- need to load/store them to
161 * separate buffers for Z and stencil.
163 assert(buffer
!= ZSTENCIL
);
164 store
.raw_mode
= true;
166 store
.disable_color_buffers_clear_on_write
= true;
167 store
.disable_z_buffer_clear_on_write
= true;
168 store
.disable_stencil_buffer_clear_on_write
= true;
170 store
.disable_color_buffers_clear_on_write
=
171 !(((pipe_bit
& PIPE_CLEAR_COLOR_BUFFERS
) &&
172 general_color_clear
&&
173 (job
->clear
& pipe_bit
)));
174 store
.disable_z_buffer_clear_on_write
=
175 !(job
->clear
& PIPE_CLEAR_DEPTH
);
176 store
.disable_stencil_buffer_clear_on_write
=
177 !(job
->clear
& PIPE_CLEAR_STENCIL
);
179 store
.padded_height_of_output_image_in_uif_blocks
=
180 surf
->padded_height_of_output_image_in_uif_blocks
;
181 #endif /* V3D_VERSION < 40 */
184 /* There must be a TILE_COORDINATES_IMPLICIT between each store. */
185 if (V3D_VERSION
< 40 && !last_store
) {
186 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
191 zs_buffer_from_pipe_bits(int pipe_clear_bits
)
193 switch (pipe_clear_bits
& PIPE_CLEAR_DEPTHSTENCIL
) {
194 case PIPE_CLEAR_DEPTHSTENCIL
:
196 case PIPE_CLEAR_DEPTH
:
198 case PIPE_CLEAR_STENCIL
:
206 v3d_rcl_emit_loads(struct v3d_job
*job
, struct v3d_cl
*cl
)
208 uint32_t loads_pending
= job
->load
;
210 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
211 uint32_t bit
= PIPE_CLEAR_COLOR0
<< i
;
212 if (!(loads_pending
& bit
))
215 struct pipe_surface
*psurf
= job
->cbufs
[i
];
216 if (!psurf
|| (V3D_VERSION
< 40 &&
217 psurf
->texture
->nr_samples
<= 1)) {
221 load_general(cl
, psurf
, RENDER_TARGET_0
+ i
,
222 bit
, &loads_pending
);
225 if ((loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
) &&
226 (V3D_VERSION
>= 40 ||
227 (job
->zsbuf
&& job
->zsbuf
->texture
->nr_samples
> 1))) {
228 struct v3d_resource
*rsc
= v3d_resource(job
->zsbuf
->texture
);
230 if (rsc
->separate_stencil
&&
231 (loads_pending
& PIPE_CLEAR_STENCIL
)) {
232 load_general(cl
, job
->zsbuf
,
238 if (loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
) {
239 load_general(cl
, job
->zsbuf
,
240 zs_buffer_from_pipe_bits(loads_pending
),
241 loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
,
247 /* The initial reload will be queued until we get the
251 cl_emit(cl
, RELOAD_TILE_COLOR_BUFFER
, load
) {
252 load
.disable_color_buffer_load
=
254 PIPE_CLEAR_COLOR_BUFFERS
) >>
255 PIPE_FIRST_COLOR_BUFFER_BIT
;
257 loads_pending
& PIPE_CLEAR_DEPTH
;
258 load
.enable_stencil_load
=
259 loads_pending
& PIPE_CLEAR_STENCIL
;
262 #else /* V3D_VERSION >= 40 */
263 assert(!loads_pending
);
264 cl_emit(cl
, END_OF_LOADS
, end
);
269 v3d_rcl_emit_stores(struct v3d_job
*job
, struct v3d_cl
*cl
)
272 MAYBE_UNUSED
bool needs_color_clear
= job
->clear
& PIPE_CLEAR_COLOR_BUFFERS
;
273 MAYBE_UNUSED
bool needs_z_clear
= job
->clear
& PIPE_CLEAR_DEPTH
;
274 MAYBE_UNUSED
bool needs_s_clear
= job
->clear
& PIPE_CLEAR_STENCIL
;
276 /* For clearing color in a TLB general on V3D 3.3:
278 * - NONE buffer store clears all TLB color buffers.
279 * - color buffer store clears just the TLB color buffer being stored.
280 * - Z/S buffers store may not clear the TLB color buffer.
282 * And on V3D 4.1, we only have one flag for "clear the buffer being
283 * stored" in the general packet, and a separate packet to clear all
286 * As a result, we only bother flagging TLB color clears in a general
287 * packet when we don't have to emit a separate packet to clear all
290 bool general_color_clear
= (needs_color_clear
&&
291 (job
->clear
& PIPE_CLEAR_COLOR_BUFFERS
) ==
292 (job
->store
& PIPE_CLEAR_COLOR_BUFFERS
));
294 bool general_color_clear
= false;
297 uint32_t stores_pending
= job
->store
;
299 /* For V3D 4.1, use general stores for all TLB stores.
301 * For V3D 3.3, we only use general stores to do raw stores for any
302 * MSAA surfaces. These output UIF tiled images where each 4x MSAA
303 * pixel is a 2x2 quad, and the format will be that of the
304 * internal_type/internal_bpp, rather than the format from GL's
305 * perspective. Non-MSAA surfaces will use
306 * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
308 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
309 uint32_t bit
= PIPE_CLEAR_COLOR0
<< i
;
310 if (!(job
->store
& bit
))
313 struct pipe_surface
*psurf
= job
->cbufs
[i
];
315 (V3D_VERSION
< 40 && psurf
->texture
->nr_samples
<= 1)) {
319 store_general(job
, cl
, psurf
, RENDER_TARGET_0
+ i
, bit
,
320 &stores_pending
, general_color_clear
);
323 if (job
->store
& PIPE_CLEAR_DEPTHSTENCIL
&& job
->zsbuf
&&
324 !(V3D_VERSION
< 40 && job
->zsbuf
->texture
->nr_samples
<= 1)) {
325 struct v3d_resource
*rsc
= v3d_resource(job
->zsbuf
->texture
);
326 if (rsc
->separate_stencil
) {
327 if (job
->store
& PIPE_CLEAR_DEPTH
) {
328 store_general(job
, cl
, job
->zsbuf
, Z
,
331 general_color_clear
);
334 if (job
->store
& PIPE_CLEAR_STENCIL
) {
335 store_general(job
, cl
, job
->zsbuf
, STENCIL
,
338 general_color_clear
);
341 store_general(job
, cl
, job
->zsbuf
,
342 zs_buffer_from_pipe_bits(job
->store
),
343 job
->store
& PIPE_CLEAR_DEPTHSTENCIL
,
344 &stores_pending
, general_color_clear
);
349 if (stores_pending
) {
350 cl_emit(cl
, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED
, store
) {
352 store
.disable_color_buffer_write
=
354 PIPE_FIRST_COLOR_BUFFER_BIT
) & 0xf;
355 store
.enable_z_write
= stores_pending
& PIPE_CLEAR_DEPTH
;
356 store
.enable_stencil_write
= stores_pending
& PIPE_CLEAR_STENCIL
;
358 /* Note that when set this will clear all of the color
361 store
.disable_color_buffers_clear_on_write
=
363 store
.disable_z_buffer_clear_on_write
=
365 store
.disable_stencil_buffer_clear_on_write
=
368 } else if (needs_color_clear
&& !general_color_clear
) {
369 /* If we didn't do our color clears in the general packet,
370 * then emit a packet to clear all the TLB color buffers now.
372 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
373 store
.buffer_to_store
= NONE
;
376 #else /* V3D_VERSION >= 40 */
377 assert(!stores_pending
);
379 /* GFXH-1461/GFXH-1689: The per-buffer store command's clear
380 * buffer bit is broken for depth/stencil. In addition, the
381 * clear packet's Z/S bit is broken, but the RTs bit ends up
385 cl_emit(cl
, CLEAR_TILE_BUFFERS
, clear
) {
386 clear
.clear_z_stencil_buffer
= true;
387 clear
.clear_all_render_targets
= true;
390 #endif /* V3D_VERSION >= 40 */
394 v3d_rcl_emit_generic_per_tile_list(struct v3d_job
*job
, int last_cbuf
)
396 /* Emit the generic list in our indirect state -- the rcl will just
397 * have pointers into it.
399 struct v3d_cl
*cl
= &job
->indirect
;
400 v3d_cl_ensure_space(cl
, 200, 1);
401 struct v3d_cl_reloc tile_list_start
= cl_get_address(cl
);
403 if (V3D_VERSION
>= 40) {
404 /* V3D 4.x only requires a single tile coordinates, and
405 * END_OF_LOADS switches us between loading and rendering.
407 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
410 v3d_rcl_emit_loads(job
, cl
);
412 if (V3D_VERSION
< 40) {
413 /* Tile Coordinates triggers the last reload and sets where
414 * the stores go. There must be one per store packet.
416 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
419 /* The binner starts out writing tiles assuming that the initial mode
420 * is triangles, so make sure that's the case.
422 cl_emit(cl
, PRIM_LIST_FORMAT
, fmt
) {
423 fmt
.primitive_type
= LIST_TRIANGLES
;
426 cl_emit(cl
, BRANCH_TO_IMPLICIT_TILE_LIST
, branch
);
428 v3d_rcl_emit_stores(job
, cl
);
430 #if V3D_VERSION >= 40
431 cl_emit(cl
, END_OF_TILE_MARKER
, end
);
434 cl_emit(cl
, RETURN_FROM_SUB_LIST
, ret
);
436 cl_emit(&job
->rcl
, START_ADDRESS_OF_GENERIC_TILE_LIST
, branch
) {
437 branch
.start
= tile_list_start
;
438 branch
.end
= cl_get_address(cl
);
442 #if V3D_VERSION >= 40
444 v3d_setup_render_target(struct v3d_job
*job
, int cbuf
,
445 uint32_t *rt_bpp
, uint32_t *rt_type
, uint32_t *rt_clamp
)
447 if (!job
->cbufs
[cbuf
])
450 struct v3d_surface
*surf
= v3d_surface(job
->cbufs
[cbuf
]);
451 *rt_bpp
= surf
->internal_bpp
;
452 *rt_type
= surf
->internal_type
;
453 *rt_clamp
= V3D_RENDER_TARGET_CLAMP_NONE
;
456 #else /* V3D_VERSION < 40 */
459 v3d_emit_z_stencil_config(struct v3d_job
*job
, struct v3d_surface
*surf
,
460 struct v3d_resource
*rsc
, bool is_separate_stencil
)
462 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_Z_STENCIL
, zs
) {
463 zs
.address
= cl_address(rsc
->bo
, surf
->offset
);
465 if (!is_separate_stencil
) {
466 zs
.internal_type
= surf
->internal_type
;
467 zs
.output_image_format
= surf
->format
;
469 zs
.z_stencil_id
= 1; /* Separate stencil */
472 zs
.padded_height_of_output_image_in_uif_blocks
=
473 surf
->padded_height_of_output_image_in_uif_blocks
;
475 assert(surf
->tiling
!= VC5_TILING_RASTER
);
476 zs
.memory_format
= surf
->tiling
;
479 if (job
->store
& (is_separate_stencil
?
481 PIPE_CLEAR_DEPTHSTENCIL
)) {
485 #endif /* V3D_VERSION < 40 */
487 #define div_round_up(a, b) (((a) + (b) - 1) / b)
490 v3dX(emit_rcl
)(struct v3d_job
*job
)
492 /* The RCL list should be empty. */
493 assert(!job
->rcl
.bo
);
495 v3d_cl_ensure_space_with_branch(&job
->rcl
, 200 + 256 *
496 cl_packet_length(SUPERTILE_COORDINATES
));
497 job
->submit
.rcl_start
= job
->rcl
.bo
->offset
;
498 v3d_job_add_bo(job
, job
->rcl
.bo
);
501 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
506 /* Comon config must be the first TILE_RENDERING_MODE_CFG
507 * and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
508 * optional updates to the previous HW state.
510 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_COMMON
, config
) {
512 config
.enable_z_store
= job
->store
& PIPE_CLEAR_DEPTH
;
513 config
.enable_stencil_store
= job
->store
& PIPE_CLEAR_STENCIL
;
514 #else /* V3D_VERSION >= 40 */
516 struct v3d_surface
*surf
= v3d_surface(job
->zsbuf
);
517 config
.internal_depth_type
= surf
->internal_type
;
519 #endif /* V3D_VERSION >= 40 */
521 /* XXX: Early D/S clear */
523 switch (job
->first_ez_state
) {
524 case VC5_EZ_UNDECIDED
:
526 config
.early_z_disable
= false;
527 config
.early_z_test_and_update_direction
=
528 EARLY_Z_DIRECTION_LT_LE
;
531 config
.early_z_disable
= false;
532 config
.early_z_test_and_update_direction
=
533 EARLY_Z_DIRECTION_GT_GE
;
535 case VC5_EZ_DISABLED
:
536 config
.early_z_disable
= true;
539 config
.image_width_pixels
= job
->draw_width
;
540 config
.image_height_pixels
= job
->draw_height
;
542 config
.number_of_render_targets
= MAX2(nr_cbufs
, 1);
544 config
.multisample_mode_4x
= job
->msaa
;
546 config
.maximum_bpp_of_all_render_targets
= job
->internal_bpp
;
549 for (int i
= 0; i
< nr_cbufs
; i
++) {
550 struct pipe_surface
*psurf
= job
->cbufs
[i
];
553 struct v3d_surface
*surf
= v3d_surface(psurf
);
554 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
556 MAYBE_UNUSED
uint32_t config_pad
= 0;
557 uint32_t clear_pad
= 0;
559 /* XXX: Set the pad for raster. */
560 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
561 surf
->tiling
== VC5_TILING_UIF_XOR
) {
562 int uif_block_height
= v3d_utile_height(rsc
->cpp
) * 2;
563 uint32_t implicit_padded_height
= (align(job
->draw_height
, uif_block_height
) /
565 if (surf
->padded_height_of_output_image_in_uif_blocks
-
566 implicit_padded_height
< 15) {
567 config_pad
= (surf
->padded_height_of_output_image_in_uif_blocks
-
568 implicit_padded_height
);
571 clear_pad
= surf
->padded_height_of_output_image_in_uif_blocks
;
576 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_COLOR
, rt
) {
577 rt
.address
= cl_address(rsc
->bo
, surf
->offset
);
578 rt
.internal_type
= surf
->internal_type
;
579 rt
.output_image_format
= surf
->format
;
580 rt
.memory_format
= surf
->tiling
;
581 rt
.internal_bpp
= surf
->internal_bpp
;
582 rt
.render_target_number
= i
;
585 if (job
->store
& PIPE_CLEAR_COLOR0
<< i
)
588 #endif /* V3D_VERSION < 40 */
590 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1
,
592 clear
.clear_color_low_32_bits
= job
->clear_color
[i
][0];
593 clear
.clear_color_next_24_bits
= job
->clear_color
[i
][1] & 0xffffff;
594 clear
.render_target_number
= i
;
597 if (surf
->internal_bpp
>= V3D_INTERNAL_BPP_64
) {
598 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2
,
600 clear
.clear_color_mid_low_32_bits
=
601 ((job
->clear_color
[i
][1] >> 24) |
602 (job
->clear_color
[i
][2] << 8));
603 clear
.clear_color_mid_high_24_bits
=
604 ((job
->clear_color
[i
][2] >> 24) |
605 ((job
->clear_color
[i
][3] & 0xffff) << 8));
606 clear
.render_target_number
= i
;
610 if (surf
->internal_bpp
>= V3D_INTERNAL_BPP_128
|| clear_pad
) {
611 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3
,
613 clear
.uif_padded_height_in_uif_blocks
= clear_pad
;
614 clear
.clear_color_high_16_bits
= job
->clear_color
[i
][3] >> 16;
615 clear
.render_target_number
= i
;
620 #if V3D_VERSION >= 40
621 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_COLOR
, rt
) {
622 v3d_setup_render_target(job
, 0,
623 &rt
.render_target_0_internal_bpp
,
624 &rt
.render_target_0_internal_type
,
625 &rt
.render_target_0_clamp
);
626 v3d_setup_render_target(job
, 1,
627 &rt
.render_target_1_internal_bpp
,
628 &rt
.render_target_1_internal_type
,
629 &rt
.render_target_1_clamp
);
630 v3d_setup_render_target(job
, 2,
631 &rt
.render_target_2_internal_bpp
,
632 &rt
.render_target_2_internal_type
,
633 &rt
.render_target_2_clamp
);
634 v3d_setup_render_target(job
, 3,
635 &rt
.render_target_3_internal_bpp
,
636 &rt
.render_target_3_internal_type
,
637 &rt
.render_target_3_clamp
);
642 /* TODO: Don't bother emitting if we don't load/clear Z/S. */
644 struct pipe_surface
*psurf
= job
->zsbuf
;
645 struct v3d_surface
*surf
= v3d_surface(psurf
);
646 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
648 v3d_emit_z_stencil_config(job
, surf
, rsc
, false);
650 /* Emit the separate stencil packet if we have a resource for
651 * it. The HW will only load/store this buffer if the
652 * Z/Stencil config doesn't have stencil in its format.
654 if (surf
->separate_stencil
) {
655 v3d_emit_z_stencil_config(job
,
656 v3d_surface(surf
->separate_stencil
),
657 rsc
->separate_stencil
, true);
660 #endif /* V3D_VERSION < 40 */
662 /* Ends rendering mode config. */
663 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES
,
665 clear
.z_clear_value
= job
->clear_z
;
666 clear
.stencil_clear_value
= job
->clear_s
;
669 /* Always set initial block size before the first branch, which needs
670 * to match the value from binning mode config.
672 cl_emit(&job
->rcl
, TILE_LIST_INITIAL_BLOCK_SIZE
, init
) {
673 init
.use_auto_chained_tile_lists
= true;
674 init
.size_of_first_block_in_chained_tile_lists
=
675 TILE_ALLOCATION_BLOCK_SIZE_64B
;
678 uint32_t supertile_w
= 1, supertile_h
= 1;
680 /* If doing multicore binning, we would need to initialize each core's
683 cl_emit(&job
->rcl
, MULTICORE_RENDERING_TILE_LIST_SET_BASE
, list
) {
684 list
.address
= cl_address(job
->tile_alloc
, 0);
687 cl_emit(&job
->rcl
, MULTICORE_RENDERING_SUPERTILE_CFG
, config
) {
688 uint32_t frame_w_in_supertiles
, frame_h_in_supertiles
;
689 const uint32_t max_supertiles
= 256;
691 /* Size up our supertiles until we get under the limit. */
693 frame_w_in_supertiles
= div_round_up(job
->draw_tiles_x
,
695 frame_h_in_supertiles
= div_round_up(job
->draw_tiles_y
,
697 if (frame_w_in_supertiles
* frame_h_in_supertiles
<
702 if (supertile_w
< supertile_h
)
708 config
.number_of_bin_tile_lists
= 1;
709 config
.total_frame_width_in_tiles
= job
->draw_tiles_x
;
710 config
.total_frame_height_in_tiles
= job
->draw_tiles_y
;
712 config
.supertile_width_in_tiles
= supertile_w
;
713 config
.supertile_height_in_tiles
= supertile_h
;
715 config
.total_frame_width_in_supertiles
= frame_w_in_supertiles
;
716 config
.total_frame_height_in_supertiles
= frame_h_in_supertiles
;
719 /* Start by clearing the tile buffer. */
720 cl_emit(&job
->rcl
, TILE_COORDINATES
, coords
) {
721 coords
.tile_column_number
= 0;
722 coords
.tile_row_number
= 0;
725 /* Emit an initial clear of the tile buffers. This is necessary for
726 * any buffers that should be cleared (since clearing normally happens
727 * at the *end* of the generic tile list), but it's also nice to clear
728 * everything so the first tile doesn't inherit any contents from some
731 * Also, implement the GFXH-1742 workaround. There's a race in the HW
732 * between the RCL updating the TLB's internal type/size and the
733 * spawning of the QPU instances using the TLB's current internal
734 * type/size. To make sure the QPUs get the right state,, we need 1
735 * dummy store in between internal type/size changes on V3D 3.x, and 2
736 * dummy stores on 4.x.
739 cl_emit(&job
->rcl
, STORE_TILE_BUFFER_GENERAL
, store
) {
740 store
.buffer_to_store
= NONE
;
743 for (int i
= 0; i
< 2; i
++) {
745 cl_emit(&job
->rcl
, TILE_COORDINATES
, coords
);
746 cl_emit(&job
->rcl
, END_OF_LOADS
, end
);
747 cl_emit(&job
->rcl
, STORE_TILE_BUFFER_GENERAL
, store
) {
748 store
.buffer_to_store
= NONE
;
751 cl_emit(&job
->rcl
, CLEAR_TILE_BUFFERS
, clear
) {
752 clear
.clear_z_stencil_buffer
= true;
753 clear
.clear_all_render_targets
= true;
756 cl_emit(&job
->rcl
, END_OF_TILE_MARKER
, end
);
760 cl_emit(&job
->rcl
, FLUSH_VCD_CACHE
, flush
);
762 v3d_rcl_emit_generic_per_tile_list(job
, nr_cbufs
- 1);
764 /* XXX perf: We should expose GL_MESA_tile_raster_order to improve X11
765 * performance, but we should use Morton order otherwise to improve
768 uint32_t supertile_w_in_pixels
= job
->tile_width
* supertile_w
;
769 uint32_t supertile_h_in_pixels
= job
->tile_height
* supertile_h
;
770 uint32_t min_x_supertile
= job
->draw_min_x
/ supertile_w_in_pixels
;
771 uint32_t min_y_supertile
= job
->draw_min_y
/ supertile_h_in_pixels
;
773 uint32_t max_x_supertile
= 0;
774 uint32_t max_y_supertile
= 0;
775 if (job
->draw_max_x
!= 0 && job
->draw_max_y
!= 0) {
776 max_x_supertile
= (job
->draw_max_x
- 1) / supertile_w_in_pixels
;
777 max_y_supertile
= (job
->draw_max_y
- 1) / supertile_h_in_pixels
;
780 for (int y
= min_y_supertile
; y
<= max_y_supertile
; y
++) {
781 for (int x
= min_x_supertile
; x
<= max_x_supertile
; x
++) {
782 cl_emit(&job
->rcl
, SUPERTILE_COORDINATES
, coords
) {
783 coords
.column_number_in_supertiles
= x
;
784 coords
.row_number_in_supertiles
= y
;
789 cl_emit(&job
->rcl
, END_OF_RENDERING
, end
);