2 * Copyright © 2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/u_format.h"
25 #include "v3d_context.h"
26 #include "v3d_tiling.h"
27 #include "broadcom/common/v3d_macros.h"
28 #include "broadcom/cle/v3dx_pack.h"
30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 | \
35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
37 /* The HW queues up the load until the tile coordinates show up, but can only
38 * track one at a time. If we need to do more than one load, then we need to
39 * flush out the previous load by emitting the tile coordinates and doing a
43 flush_last_load(struct v3d_cl
*cl
)
45 if (V3D_VERSION
>= 40)
48 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
49 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
50 store
.buffer_to_store
= NONE
;
55 load_general(struct v3d_cl
*cl
, struct pipe_surface
*psurf
, int buffer
,
56 uint32_t pipe_bit
, uint32_t *loads_pending
)
58 struct v3d_surface
*surf
= v3d_surface(psurf
);
59 bool separate_stencil
= surf
->separate_stencil
&& buffer
== STENCIL
;
60 if (separate_stencil
) {
61 psurf
= surf
->separate_stencil
;
62 surf
= v3d_surface(psurf
);
65 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
67 cl_emit(cl
, LOAD_TILE_BUFFER_GENERAL
, load
) {
68 load
.buffer_to_load
= buffer
;
69 load
.address
= cl_address(rsc
->bo
, surf
->offset
);
72 load
.memory_format
= surf
->tiling
;
74 load
.input_image_format
= V3D_OUTPUT_IMAGE_FORMAT_S8
;
76 load
.input_image_format
= surf
->format
;
78 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
79 surf
->tiling
== VC5_TILING_UIF_XOR
) {
80 load
.height_in_ub_or_stride
=
81 surf
->padded_height_of_output_image_in_uif_blocks
;
82 } else if (surf
->tiling
== VC5_TILING_RASTER
) {
83 struct v3d_resource_slice
*slice
=
84 &rsc
->slices
[psurf
->u
.tex
.level
];
85 load
.height_in_ub_or_stride
= slice
->stride
;
88 if (psurf
->texture
->nr_samples
> 1)
89 load
.decimate_mode
= V3D_DECIMATE_MODE_ALL_SAMPLES
;
91 load
.decimate_mode
= V3D_DECIMATE_MODE_SAMPLE_0
;
93 #else /* V3D_VERSION < 40 */
94 /* Can't do raw ZSTENCIL loads -- need to load/store them to
95 * separate buffers for Z and stencil.
97 assert(buffer
!= ZSTENCIL
);
99 load
.padded_height_of_output_image_in_uif_blocks
=
100 surf
->padded_height_of_output_image_in_uif_blocks
;
101 #endif /* V3D_VERSION < 40 */
104 *loads_pending
&= ~pipe_bit
;
110 store_general(struct v3d_job
*job
,
111 struct v3d_cl
*cl
, struct pipe_surface
*psurf
, int buffer
,
112 int pipe_bit
, uint32_t *stores_pending
, bool general_color_clear
)
114 struct v3d_surface
*surf
= v3d_surface(psurf
);
115 bool separate_stencil
= surf
->separate_stencil
&& buffer
== STENCIL
;
116 if (separate_stencil
) {
117 psurf
= surf
->separate_stencil
;
118 surf
= v3d_surface(psurf
);
121 *stores_pending
&= ~pipe_bit
;
122 bool last_store
= !(*stores_pending
);
124 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
128 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
129 store
.buffer_to_store
= buffer
;
130 store
.address
= cl_address(rsc
->bo
, surf
->offset
);
132 #if V3D_VERSION >= 40
133 store
.clear_buffer_being_stored
= false;
135 if (separate_stencil
)
136 store
.output_image_format
= V3D_OUTPUT_IMAGE_FORMAT_S8
;
138 store
.output_image_format
= surf
->format
;
140 store
.memory_format
= surf
->tiling
;
142 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
143 surf
->tiling
== VC5_TILING_UIF_XOR
) {
144 store
.height_in_ub_or_stride
=
145 surf
->padded_height_of_output_image_in_uif_blocks
;
146 } else if (surf
->tiling
== VC5_TILING_RASTER
) {
147 struct v3d_resource_slice
*slice
=
148 &rsc
->slices
[psurf
->u
.tex
.level
];
149 store
.height_in_ub_or_stride
= slice
->stride
;
152 if (psurf
->texture
->nr_samples
> 1)
153 store
.decimate_mode
= V3D_DECIMATE_MODE_ALL_SAMPLES
;
155 store
.decimate_mode
= V3D_DECIMATE_MODE_SAMPLE_0
;
157 #else /* V3D_VERSION < 40 */
158 /* Can't do raw ZSTENCIL stores -- need to load/store them to
159 * separate buffers for Z and stencil.
161 assert(buffer
!= ZSTENCIL
);
162 store
.raw_mode
= true;
164 store
.disable_colour_buffers_clear_on_write
= true;
165 store
.disable_z_buffer_clear_on_write
= true;
166 store
.disable_stencil_buffer_clear_on_write
= true;
168 store
.disable_colour_buffers_clear_on_write
=
169 !(((pipe_bit
& PIPE_CLEAR_COLOR_BUFFERS
) &&
170 general_color_clear
&&
171 (job
->clear
& pipe_bit
)));
172 store
.disable_z_buffer_clear_on_write
=
173 !(job
->clear
& PIPE_CLEAR_DEPTH
);
174 store
.disable_stencil_buffer_clear_on_write
=
175 !(job
->clear
& PIPE_CLEAR_STENCIL
);
177 store
.padded_height_of_output_image_in_uif_blocks
=
178 surf
->padded_height_of_output_image_in_uif_blocks
;
179 #endif /* V3D_VERSION < 40 */
182 /* There must be a TILE_COORDINATES_IMPLICIT between each store. */
183 if (V3D_VERSION
< 40 && !last_store
) {
184 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
189 zs_buffer_from_pipe_bits(int pipe_clear_bits
)
191 switch (pipe_clear_bits
& PIPE_CLEAR_DEPTHSTENCIL
) {
192 case PIPE_CLEAR_DEPTHSTENCIL
:
194 case PIPE_CLEAR_DEPTH
:
196 case PIPE_CLEAR_STENCIL
:
204 v3d_rcl_emit_loads(struct v3d_job
*job
, struct v3d_cl
*cl
)
206 uint32_t loads_pending
= job
->load
;
208 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
209 uint32_t bit
= PIPE_CLEAR_COLOR0
<< i
;
210 if (!(loads_pending
& bit
))
213 struct pipe_surface
*psurf
= job
->cbufs
[i
];
214 if (!psurf
|| (V3D_VERSION
< 40 &&
215 psurf
->texture
->nr_samples
<= 1)) {
219 load_general(cl
, psurf
, RENDER_TARGET_0
+ i
,
220 bit
, &loads_pending
);
223 if ((loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
) &&
224 (V3D_VERSION
>= 40 ||
225 (job
->zsbuf
&& job
->zsbuf
->texture
->nr_samples
> 1))) {
226 struct v3d_resource
*rsc
= v3d_resource(job
->zsbuf
->texture
);
228 if (rsc
->separate_stencil
&&
229 (loads_pending
& PIPE_CLEAR_STENCIL
)) {
230 load_general(cl
, job
->zsbuf
,
236 if (loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
) {
237 load_general(cl
, job
->zsbuf
,
238 zs_buffer_from_pipe_bits(loads_pending
),
239 loads_pending
& PIPE_CLEAR_DEPTHSTENCIL
,
245 /* The initial reload will be queued until we get the
249 cl_emit(cl
, RELOAD_TILE_COLOUR_BUFFER
, load
) {
250 load
.disable_colour_buffer_load
=
252 PIPE_CLEAR_COLOR_BUFFERS
) >>
253 PIPE_FIRST_COLOR_BUFFER_BIT
;
255 loads_pending
& PIPE_CLEAR_DEPTH
;
256 load
.enable_stencil_load
=
257 loads_pending
& PIPE_CLEAR_STENCIL
;
260 #else /* V3D_VERSION >= 40 */
261 assert(!loads_pending
);
262 cl_emit(cl
, END_OF_LOADS
, end
);
267 v3d_rcl_emit_stores(struct v3d_job
*job
, struct v3d_cl
*cl
)
270 MAYBE_UNUSED
bool needs_color_clear
= job
->clear
& PIPE_CLEAR_COLOR_BUFFERS
;
271 MAYBE_UNUSED
bool needs_z_clear
= job
->clear
& PIPE_CLEAR_DEPTH
;
272 MAYBE_UNUSED
bool needs_s_clear
= job
->clear
& PIPE_CLEAR_STENCIL
;
274 /* For clearing color in a TLB general on V3D 3.3:
276 * - NONE buffer store clears all TLB color buffers.
277 * - color buffer store clears just the TLB color buffer being stored.
278 * - Z/S buffers store may not clear the TLB color buffer.
280 * And on V3D 4.1, we only have one flag for "clear the buffer being
281 * stored" in the general packet, and a separate packet to clear all
284 * As a result, we only bother flagging TLB color clears in a general
285 * packet when we don't have to emit a separate packet to clear all
288 bool general_color_clear
= (needs_color_clear
&&
289 (job
->clear
& PIPE_CLEAR_COLOR_BUFFERS
) ==
290 (job
->store
& PIPE_CLEAR_COLOR_BUFFERS
));
292 bool general_color_clear
= false;
295 uint32_t stores_pending
= job
->store
;
297 /* For V3D 4.1, use general stores for all TLB stores.
299 * For V3D 3.3, we only use general stores to do raw stores for any
300 * MSAA surfaces. These output UIF tiled images where each 4x MSAA
301 * pixel is a 2x2 quad, and the format will be that of the
302 * internal_type/internal_bpp, rather than the format from GL's
303 * perspective. Non-MSAA surfaces will use
304 * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
306 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
307 uint32_t bit
= PIPE_CLEAR_COLOR0
<< i
;
308 if (!(job
->store
& bit
))
311 struct pipe_surface
*psurf
= job
->cbufs
[i
];
313 (V3D_VERSION
< 40 && psurf
->texture
->nr_samples
<= 1)) {
317 store_general(job
, cl
, psurf
, RENDER_TARGET_0
+ i
, bit
,
318 &stores_pending
, general_color_clear
);
321 if (job
->store
& PIPE_CLEAR_DEPTHSTENCIL
&& job
->zsbuf
&&
322 !(V3D_VERSION
< 40 && job
->zsbuf
->texture
->nr_samples
<= 1)) {
323 struct v3d_resource
*rsc
= v3d_resource(job
->zsbuf
->texture
);
324 if (rsc
->separate_stencil
) {
325 if (job
->store
& PIPE_CLEAR_DEPTH
) {
326 store_general(job
, cl
, job
->zsbuf
, Z
,
329 general_color_clear
);
332 if (job
->store
& PIPE_CLEAR_STENCIL
) {
333 store_general(job
, cl
, job
->zsbuf
, STENCIL
,
336 general_color_clear
);
339 store_general(job
, cl
, job
->zsbuf
,
340 zs_buffer_from_pipe_bits(job
->store
),
341 job
->store
& PIPE_CLEAR_DEPTHSTENCIL
,
342 &stores_pending
, general_color_clear
);
347 if (stores_pending
) {
348 cl_emit(cl
, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED
, store
) {
350 store
.disable_color_buffer_write
=
352 PIPE_FIRST_COLOR_BUFFER_BIT
) & 0xf;
353 store
.enable_z_write
= stores_pending
& PIPE_CLEAR_DEPTH
;
354 store
.enable_stencil_write
= stores_pending
& PIPE_CLEAR_STENCIL
;
356 /* Note that when set this will clear all of the color
359 store
.disable_colour_buffers_clear_on_write
=
361 store
.disable_z_buffer_clear_on_write
=
363 store
.disable_stencil_buffer_clear_on_write
=
366 } else if (needs_color_clear
&& !general_color_clear
) {
367 /* If we didn't do our color clears in the general packet,
368 * then emit a packet to clear all the TLB color buffers now.
370 cl_emit(cl
, STORE_TILE_BUFFER_GENERAL
, store
) {
371 store
.buffer_to_store
= NONE
;
374 #else /* V3D_VERSION >= 40 */
375 assert(!stores_pending
);
377 /* GFXH-1461/GFXH-1689: The per-buffer store command's clear
378 * buffer bit is broken for depth/stencil. In addition, the
379 * clear packet's Z/S bit is broken, but the RTs bit ends up
383 cl_emit(cl
, CLEAR_TILE_BUFFERS
, clear
) {
384 clear
.clear_z_stencil_buffer
= true;
385 clear
.clear_all_render_targets
= true;
388 #endif /* V3D_VERSION >= 40 */
392 v3d_rcl_emit_generic_per_tile_list(struct v3d_job
*job
, int last_cbuf
)
394 /* Emit the generic list in our indirect state -- the rcl will just
395 * have pointers into it.
397 struct v3d_cl
*cl
= &job
->indirect
;
398 v3d_cl_ensure_space(cl
, 200, 1);
399 struct v3d_cl_reloc tile_list_start
= cl_get_address(cl
);
401 if (V3D_VERSION
>= 40) {
402 /* V3D 4.x only requires a single tile coordinates, and
403 * END_OF_LOADS switches us between loading and rendering.
405 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
408 v3d_rcl_emit_loads(job
, cl
);
410 if (V3D_VERSION
< 40) {
411 /* Tile Coordinates triggers the last reload and sets where
412 * the stores go. There must be one per store packet.
414 cl_emit(cl
, TILE_COORDINATES_IMPLICIT
, coords
);
417 /* The binner starts out writing tiles assuming that the initial mode
418 * is triangles, so make sure that's the case.
420 cl_emit(cl
, PRIM_LIST_FORMAT
, fmt
) {
421 fmt
.primitive_type
= LIST_TRIANGLES
;
424 cl_emit(cl
, BRANCH_TO_IMPLICIT_TILE_LIST
, branch
);
426 v3d_rcl_emit_stores(job
, cl
);
428 #if V3D_VERSION >= 40
429 cl_emit(cl
, END_OF_TILE_MARKER
, end
);
432 cl_emit(cl
, RETURN_FROM_SUB_LIST
, ret
);
434 cl_emit(&job
->rcl
, START_ADDRESS_OF_GENERIC_TILE_LIST
, branch
) {
435 branch
.start
= tile_list_start
;
436 branch
.end
= cl_get_address(cl
);
440 #if V3D_VERSION >= 40
442 v3d_setup_render_target(struct v3d_job
*job
, int cbuf
,
443 uint32_t *rt_bpp
, uint32_t *rt_type
, uint32_t *rt_clamp
)
445 if (!job
->cbufs
[cbuf
])
448 struct v3d_surface
*surf
= v3d_surface(job
->cbufs
[cbuf
]);
449 *rt_bpp
= surf
->internal_bpp
;
450 *rt_type
= surf
->internal_type
;
451 *rt_clamp
= V3D_RENDER_TARGET_CLAMP_NONE
;
454 #else /* V3D_VERSION < 40 */
457 v3d_emit_z_stencil_config(struct v3d_job
*job
, struct v3d_surface
*surf
,
458 struct v3d_resource
*rsc
, bool is_separate_stencil
)
460 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CONFIG
, zs
) {
461 zs
.address
= cl_address(rsc
->bo
, surf
->offset
);
463 if (!is_separate_stencil
) {
464 zs
.internal_type
= surf
->internal_type
;
465 zs
.output_image_format
= surf
->format
;
467 zs
.z_stencil_id
= 1; /* Separate stencil */
470 zs
.padded_height_of_output_image_in_uif_blocks
=
471 surf
->padded_height_of_output_image_in_uif_blocks
;
473 assert(surf
->tiling
!= VC5_TILING_RASTER
);
474 zs
.memory_format
= surf
->tiling
;
477 if (job
->store
& (is_separate_stencil
?
479 PIPE_CLEAR_DEPTHSTENCIL
)) {
483 #endif /* V3D_VERSION < 40 */
485 #define div_round_up(a, b) (((a) + (b) - 1) / b)
488 v3dX(emit_rcl
)(struct v3d_job
*job
)
490 /* The RCL list should be empty. */
491 assert(!job
->rcl
.bo
);
493 v3d_cl_ensure_space_with_branch(&job
->rcl
, 200 + 256 *
494 cl_packet_length(SUPERTILE_COORDINATES
));
495 job
->submit
.rcl_start
= job
->rcl
.bo
->offset
;
496 v3d_job_add_bo(job
, job
->rcl
.bo
);
499 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
504 /* Comon config must be the first TILE_RENDERING_MODE_CONFIGURATION
505 * and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
506 * optional updates to the previous HW state.
508 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION
,
511 config
.enable_z_store
= job
->store
& PIPE_CLEAR_DEPTH
;
512 config
.enable_stencil_store
= job
->store
& PIPE_CLEAR_STENCIL
;
513 #else /* V3D_VERSION >= 40 */
515 struct v3d_surface
*surf
= v3d_surface(job
->zsbuf
);
516 config
.internal_depth_type
= surf
->internal_type
;
518 #endif /* V3D_VERSION >= 40 */
520 /* XXX: Early D/S clear */
522 switch (job
->first_ez_state
) {
523 case VC5_EZ_UNDECIDED
:
525 config
.early_z_disable
= false;
526 config
.early_z_test_and_update_direction
=
527 EARLY_Z_DIRECTION_LT_LE
;
530 config
.early_z_disable
= false;
531 config
.early_z_test_and_update_direction
=
532 EARLY_Z_DIRECTION_GT_GE
;
534 case VC5_EZ_DISABLED
:
535 config
.early_z_disable
= true;
538 config
.image_width_pixels
= job
->draw_width
;
539 config
.image_height_pixels
= job
->draw_height
;
541 config
.number_of_render_targets
= MAX2(nr_cbufs
, 1);
543 config
.multisample_mode_4x
= job
->msaa
;
545 config
.maximum_bpp_of_all_render_targets
= job
->internal_bpp
;
548 for (int i
= 0; i
< nr_cbufs
; i
++) {
549 struct pipe_surface
*psurf
= job
->cbufs
[i
];
552 struct v3d_surface
*surf
= v3d_surface(psurf
);
553 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
555 MAYBE_UNUSED
uint32_t config_pad
= 0;
556 uint32_t clear_pad
= 0;
558 /* XXX: Set the pad for raster. */
559 if (surf
->tiling
== VC5_TILING_UIF_NO_XOR
||
560 surf
->tiling
== VC5_TILING_UIF_XOR
) {
561 int uif_block_height
= v3d_utile_height(rsc
->cpp
) * 2;
562 uint32_t implicit_padded_height
= (align(job
->draw_height
, uif_block_height
) /
564 if (surf
->padded_height_of_output_image_in_uif_blocks
-
565 implicit_padded_height
< 15) {
566 config_pad
= (surf
->padded_height_of_output_image_in_uif_blocks
-
567 implicit_padded_height
);
570 clear_pad
= surf
->padded_height_of_output_image_in_uif_blocks
;
575 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG
, rt
) {
576 rt
.address
= cl_address(rsc
->bo
, surf
->offset
);
577 rt
.internal_type
= surf
->internal_type
;
578 rt
.output_image_format
= surf
->format
;
579 rt
.memory_format
= surf
->tiling
;
580 rt
.internal_bpp
= surf
->internal_bpp
;
581 rt
.render_target_number
= i
;
584 if (job
->store
& PIPE_CLEAR_COLOR0
<< i
)
587 #endif /* V3D_VERSION < 40 */
589 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1
,
591 clear
.clear_color_low_32_bits
= job
->clear_color
[i
][0];
592 clear
.clear_color_next_24_bits
= job
->clear_color
[i
][1] & 0xffffff;
593 clear
.render_target_number
= i
;
596 if (surf
->internal_bpp
>= V3D_INTERNAL_BPP_64
) {
597 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2
,
599 clear
.clear_color_mid_low_32_bits
=
600 ((job
->clear_color
[i
][1] >> 24) |
601 (job
->clear_color
[i
][2] << 8));
602 clear
.clear_color_mid_high_24_bits
=
603 ((job
->clear_color
[i
][2] >> 24) |
604 ((job
->clear_color
[i
][3] & 0xffff) << 8));
605 clear
.render_target_number
= i
;
609 if (surf
->internal_bpp
>= V3D_INTERNAL_BPP_128
|| clear_pad
) {
610 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3
,
612 clear
.uif_padded_height_in_uif_blocks
= clear_pad
;
613 clear
.clear_color_high_16_bits
= job
->clear_color
[i
][3] >> 16;
614 clear
.render_target_number
= i
;
619 #if V3D_VERSION >= 40
620 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG
, rt
) {
621 v3d_setup_render_target(job
, 0,
622 &rt
.render_target_0_internal_bpp
,
623 &rt
.render_target_0_internal_type
,
624 &rt
.render_target_0_clamp
);
625 v3d_setup_render_target(job
, 1,
626 &rt
.render_target_1_internal_bpp
,
627 &rt
.render_target_1_internal_type
,
628 &rt
.render_target_1_clamp
);
629 v3d_setup_render_target(job
, 2,
630 &rt
.render_target_2_internal_bpp
,
631 &rt
.render_target_2_internal_type
,
632 &rt
.render_target_2_clamp
);
633 v3d_setup_render_target(job
, 3,
634 &rt
.render_target_3_internal_bpp
,
635 &rt
.render_target_3_internal_type
,
636 &rt
.render_target_3_clamp
);
641 /* TODO: Don't bother emitting if we don't load/clear Z/S. */
643 struct pipe_surface
*psurf
= job
->zsbuf
;
644 struct v3d_surface
*surf
= v3d_surface(psurf
);
645 struct v3d_resource
*rsc
= v3d_resource(psurf
->texture
);
647 v3d_emit_z_stencil_config(job
, surf
, rsc
, false);
649 /* Emit the separate stencil packet if we have a resource for
650 * it. The HW will only load/store this buffer if the
651 * Z/Stencil config doesn't have stencil in its format.
653 if (surf
->separate_stencil
) {
654 v3d_emit_z_stencil_config(job
,
655 v3d_surface(surf
->separate_stencil
),
656 rsc
->separate_stencil
, true);
659 #endif /* V3D_VERSION < 40 */
661 /* Ends rendering mode config. */
662 cl_emit(&job
->rcl
, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES
,
664 clear
.z_clear_value
= job
->clear_z
;
665 clear
.stencil_clear_value
= job
->clear_s
;
668 /* Always set initial block size before the first branch, which needs
669 * to match the value from binning mode config.
671 cl_emit(&job
->rcl
, TILE_LIST_INITIAL_BLOCK_SIZE
, init
) {
672 init
.use_auto_chained_tile_lists
= true;
673 init
.size_of_first_block_in_chained_tile_lists
=
674 TILE_ALLOCATION_BLOCK_SIZE_64B
;
677 uint32_t supertile_w
= 1, supertile_h
= 1;
679 /* If doing multicore binning, we would need to initialize each core's
682 cl_emit(&job
->rcl
, MULTICORE_RENDERING_TILE_LIST_SET_BASE
, list
) {
683 list
.address
= cl_address(job
->tile_alloc
, 0);
686 cl_emit(&job
->rcl
, MULTICORE_RENDERING_SUPERTILE_CONFIGURATION
, config
) {
687 uint32_t frame_w_in_supertiles
, frame_h_in_supertiles
;
688 const uint32_t max_supertiles
= 256;
690 /* Size up our supertiles until we get under the limit. */
692 frame_w_in_supertiles
= div_round_up(job
->draw_tiles_x
,
694 frame_h_in_supertiles
= div_round_up(job
->draw_tiles_y
,
696 if (frame_w_in_supertiles
* frame_h_in_supertiles
<
701 if (supertile_w
< supertile_h
)
707 config
.number_of_bin_tile_lists
= 1;
708 config
.total_frame_width_in_tiles
= job
->draw_tiles_x
;
709 config
.total_frame_height_in_tiles
= job
->draw_tiles_y
;
711 config
.supertile_width_in_tiles
= supertile_w
;
712 config
.supertile_height_in_tiles
= supertile_h
;
714 config
.total_frame_width_in_supertiles
= frame_w_in_supertiles
;
715 config
.total_frame_height_in_supertiles
= frame_h_in_supertiles
;
718 /* Start by clearing the tile buffer. */
719 cl_emit(&job
->rcl
, TILE_COORDINATES
, coords
) {
720 coords
.tile_column_number
= 0;
721 coords
.tile_row_number
= 0;
724 /* Emit an initial clear of the tile buffers. This is necessary for
725 * any buffers that should be cleared (since clearing normally happens
726 * at the *end* of the generic tile list), but it's also nice to clear
727 * everything so the first tile doesn't inherit any contents from some
730 * Also, implement the GFXH-1742 workaround. There's a race in the HW
731 * between the RCL updating the TLB's internal type/size and the
732 * spawning of the QPU instances using the TLB's current internal
733 * type/size. To make sure the QPUs get the right state,, we need 1
734 * dummy store in between internal type/size changes on V3D 3.x, and 2
735 * dummy stores on 4.x.
738 cl_emit(&job
->rcl
, STORE_TILE_BUFFER_GENERAL
, store
) {
739 store
.buffer_to_store
= NONE
;
742 for (int i
= 0; i
< 2; i
++) {
744 cl_emit(&job
->rcl
, TILE_COORDINATES
, coords
);
745 cl_emit(&job
->rcl
, END_OF_LOADS
, end
);
746 cl_emit(&job
->rcl
, STORE_TILE_BUFFER_GENERAL
, store
) {
747 store
.buffer_to_store
= NONE
;
750 cl_emit(&job
->rcl
, CLEAR_TILE_BUFFERS
, clear
) {
751 clear
.clear_z_stencil_buffer
= true;
752 clear
.clear_all_render_targets
= true;
755 cl_emit(&job
->rcl
, END_OF_TILE_MARKER
, end
);
759 cl_emit(&job
->rcl
, FLUSH_VCD_CACHE
, flush
);
761 v3d_rcl_emit_generic_per_tile_list(job
, nr_cbufs
- 1);
763 /* XXX: Use Morton order */
764 uint32_t supertile_w_in_pixels
= job
->tile_width
* supertile_w
;
765 uint32_t supertile_h_in_pixels
= job
->tile_height
* supertile_h
;
766 uint32_t min_x_supertile
= job
->draw_min_x
/ supertile_w_in_pixels
;
767 uint32_t min_y_supertile
= job
->draw_min_y
/ supertile_h_in_pixels
;
769 uint32_t max_x_supertile
= 0;
770 uint32_t max_y_supertile
= 0;
771 if (job
->draw_max_x
!= 0 && job
->draw_max_y
!= 0) {
772 max_x_supertile
= (job
->draw_max_x
- 1) / supertile_w_in_pixels
;
773 max_y_supertile
= (job
->draw_max_y
- 1) / supertile_h_in_pixels
;
776 for (int y
= min_y_supertile
; y
<= max_y_supertile
; y
++) {
777 for (int x
= min_x_supertile
; x
<= max_x_supertile
; x
++) {
778 cl_emit(&job
->rcl
, SUPERTILE_COORDINATES
, coords
) {
779 coords
.column_number_in_supertiles
= x
;
780 coords
.row_number_in_supertiles
= y
;
785 cl_emit(&job
->rcl
, END_OF_RENDERING
, end
);