2 * Copyright © 2014-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * @file v3d_simulator_hw.c
27 * Implements the actual HW interaction betweeh the GL driver's VC5 simulator and the simulator.
29 * The register headers between V3D versions will have conflicting defines, so
30 * all register interactions appear in this file and are compiled per V3D version
34 #ifdef USE_V3D_SIMULATOR
36 #include "v3d_screen.h"
37 #include "v3d_context.h"
38 #include "v3d_simulator_wrapper.h"
40 #define HW_REGISTER_RO(x) (x)
41 #define HW_REGISTER_RW(x) (x)
43 #include "libs/core/v3d/registers/4.1.34.0/v3d.h"
45 #include "libs/core/v3d/registers/3.3.0.0/v3d.h"
48 #define V3D_WRITE(reg, val) v3d_hw_write_reg(v3d, reg, val)
49 #define V3D_READ(reg) v3d_hw_read_reg(v3d, reg)
52 v3d_flush_l3(struct v3d_hw
*v3d
)
54 if (!v3d_hw_has_gca(v3d
))
58 uint32_t gca_ctrl
= V3D_READ(V3D_GCA_CACHE_CTRL
);
60 V3D_WRITE(V3D_GCA_CACHE_CTRL
, gca_ctrl
| V3D_GCA_CACHE_CTRL_FLUSH_SET
);
61 V3D_WRITE(V3D_GCA_CACHE_CTRL
, gca_ctrl
& ~V3D_GCA_CACHE_CTRL_FLUSH_SET
);
65 /* Invalidates the L2 cache. This is a read-only cache. */
67 v3d_flush_l2(struct v3d_hw
*v3d
)
69 V3D_WRITE(V3D_CTL_0_L2CACTL
,
70 V3D_CTL_0_L2CACTL_L2CCLR_SET
|
71 V3D_CTL_0_L2CACTL_L2CENA_SET
);
74 /* Invalidates texture L2 cachelines */
76 v3d_flush_l2t(struct v3d_hw
*v3d
)
78 V3D_WRITE(V3D_CTL_0_L2TFLSTA
, 0);
79 V3D_WRITE(V3D_CTL_0_L2TFLEND
, ~0);
80 V3D_WRITE(V3D_CTL_0_L2TCACTL
,
81 V3D_CTL_0_L2TCACTL_L2TFLS_SET
|
82 (0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB
));
85 /* Invalidates the slice caches. These are read-only caches. */
87 v3d_flush_slices(struct v3d_hw
*v3d
)
89 V3D_WRITE(V3D_CTL_0_SLCACTL
, ~0);
93 v3d_flush_caches(struct v3d_hw
*v3d
)
98 v3d_flush_slices(v3d
);
102 v3dX(simulator_submit_tfu_ioctl
)(struct v3d_hw
*v3d
,
103 struct drm_v3d_submit_tfu
*args
)
105 int last_vtct
= V3D_READ(V3D_TFU_CS
) & V3D_TFU_CS_CVTCT_SET
;
107 V3D_WRITE(V3D_TFU_IIA
, args
->iia
);
108 V3D_WRITE(V3D_TFU_IIS
, args
->iis
);
109 V3D_WRITE(V3D_TFU_ICA
, args
->ica
);
110 V3D_WRITE(V3D_TFU_IUA
, args
->iua
);
111 V3D_WRITE(V3D_TFU_IOA
, args
->ioa
);
112 V3D_WRITE(V3D_TFU_IOS
, args
->ios
);
113 V3D_WRITE(V3D_TFU_COEF0
, args
->coef
[0]);
114 V3D_WRITE(V3D_TFU_COEF1
, args
->coef
[1]);
115 V3D_WRITE(V3D_TFU_COEF2
, args
->coef
[2]);
116 V3D_WRITE(V3D_TFU_COEF3
, args
->coef
[3]);
118 V3D_WRITE(V3D_TFU_ICFG
, args
->icfg
);
120 while ((V3D_READ(V3D_TFU_CS
) & V3D_TFU_CS_CVTCT_SET
) != last_vtct
) {
128 v3dX(simulator_get_param_ioctl
)(struct v3d_hw
*v3d
,
129 struct drm_v3d_get_param
*args
)
131 static const uint32_t reg_map
[] = {
132 [DRM_V3D_PARAM_V3D_UIFCFG
] = V3D_HUB_CTL_UIFCFG
,
133 [DRM_V3D_PARAM_V3D_HUB_IDENT1
] = V3D_HUB_CTL_IDENT1
,
134 [DRM_V3D_PARAM_V3D_HUB_IDENT2
] = V3D_HUB_CTL_IDENT2
,
135 [DRM_V3D_PARAM_V3D_HUB_IDENT3
] = V3D_HUB_CTL_IDENT3
,
136 [DRM_V3D_PARAM_V3D_CORE0_IDENT0
] = V3D_CTL_0_IDENT0
,
137 [DRM_V3D_PARAM_V3D_CORE0_IDENT1
] = V3D_CTL_0_IDENT1
,
138 [DRM_V3D_PARAM_V3D_CORE0_IDENT2
] = V3D_CTL_0_IDENT2
,
141 switch (args
->param
) {
142 case DRM_V3D_PARAM_SUPPORTS_TFU
:
147 if (args
->param
< ARRAY_SIZE(reg_map
) && reg_map
[args
->param
]) {
148 args
->value
= V3D_READ(reg_map
[args
->param
]);
152 fprintf(stderr
, "Unknown DRM_IOCTL_VC5_GET_PARAM(%lld)\n",
153 (long long)args
->value
);
158 v3dX(simulator_init_regs
)(struct v3d_hw
*v3d
)
160 #if V3D_VERSION == 33
161 /* Set OVRTMUOUT to match kernel behavior.
163 * This means that the texture sampler uniform configuration's tmu
164 * output type field is used, instead of using the hardware default
165 * behavior based on the texture type. If you want the default
166 * behavior, you can still put "2" in the indirect texture state's
169 V3D_WRITE(V3D_CTL_0_MISCCFG
, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET
);
174 v3dX(simulator_submit_cl_ioctl
)(struct v3d_hw
*v3d
,
175 struct drm_v3d_submit_cl
*submit
,
178 /* Completely reset the GMP. */
179 V3D_WRITE(V3D_GMP_0_CFG
,
180 V3D_GMP_0_CFG_PROTENABLE_SET
);
181 V3D_WRITE(V3D_GMP_0_TABLE_ADDR
, gmp_ofs
);
182 V3D_WRITE(V3D_GMP_0_CLEAR_LOAD
, ~0);
183 while (V3D_READ(V3D_GMP_0_STATUS
) &
184 V3D_GMP_0_STATUS_CFG_BUSY_SET
) {
188 v3d_flush_caches(v3d
);
191 V3D_WRITE(V3D_CLE_0_CT0QMA
, submit
->qma
);
192 V3D_WRITE(V3D_CLE_0_CT0QMS
, submit
->qms
);
194 #if V3D_VERSION >= 41
196 V3D_WRITE(V3D_CLE_0_CT0QTS
,
197 V3D_CLE_0_CT0QTS_CTQTSEN_SET
|
201 V3D_WRITE(V3D_CLE_0_CT0QBA
, submit
->bcl_start
);
202 V3D_WRITE(V3D_CLE_0_CT0QEA
, submit
->bcl_end
);
204 /* Wait for bin to complete before firing render, as it seems the
205 * simulator doesn't implement the semaphores.
207 while (V3D_READ(V3D_CLE_0_CT0CA
) !=
208 V3D_READ(V3D_CLE_0_CT0EA
)) {
212 V3D_WRITE(V3D_CLE_0_CT1QBA
, submit
->rcl_start
);
213 V3D_WRITE(V3D_CLE_0_CT1QEA
, submit
->rcl_end
);
215 while (V3D_READ(V3D_CLE_0_CT1CA
) !=
216 V3D_READ(V3D_CLE_0_CT1EA
) ||
217 V3D_READ(V3D_CLE_1_CT1CA
) !=
218 V3D_READ(V3D_CLE_1_CT1EA
)) {
223 #endif /* USE_V3D_SIMULATOR */