2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "pipe/p_state.h"
26 #include "util/u_format.h"
27 #include "util/u_framebuffer.h"
28 #include "util/u_inlines.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/u_half.h"
32 #include "util/u_helpers.h"
34 #include "v3d_context.h"
35 #include "v3d_tiling.h"
36 #include "broadcom/common/v3d_macros.h"
37 #include "broadcom/cle/v3dx_pack.h"
40 v3d_generic_cso_state_delete(struct pipe_context
*pctx
, void *hwcso
)
46 v3d_set_blend_color(struct pipe_context
*pctx
,
47 const struct pipe_blend_color
*blend_color
)
49 struct v3d_context
*v3d
= v3d_context(pctx
);
50 v3d
->blend_color
.f
= *blend_color
;
51 for (int i
= 0; i
< 4; i
++) {
52 v3d
->blend_color
.hf
[i
] =
53 util_float_to_half(blend_color
->color
[i
]);
55 v3d
->dirty
|= VC5_DIRTY_BLEND_COLOR
;
59 v3d_set_stencil_ref(struct pipe_context
*pctx
,
60 const struct pipe_stencil_ref
*stencil_ref
)
62 struct v3d_context
*v3d
= v3d_context(pctx
);
63 v3d
->stencil_ref
= *stencil_ref
;
64 v3d
->dirty
|= VC5_DIRTY_STENCIL_REF
;
68 v3d_set_clip_state(struct pipe_context
*pctx
,
69 const struct pipe_clip_state
*clip
)
71 struct v3d_context
*v3d
= v3d_context(pctx
);
73 v3d
->dirty
|= VC5_DIRTY_CLIP
;
77 v3d_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
79 struct v3d_context
*v3d
= v3d_context(pctx
);
80 v3d
->sample_mask
= sample_mask
& ((1 << VC5_MAX_SAMPLES
) - 1);
81 v3d
->dirty
|= VC5_DIRTY_SAMPLE_STATE
;
85 float_to_187_half(float f
)
91 v3d_create_rasterizer_state(struct pipe_context
*pctx
,
92 const struct pipe_rasterizer_state
*cso
)
94 struct v3d_rasterizer_state
*so
;
96 so
= CALLOC_STRUCT(v3d_rasterizer_state
);
102 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
105 so
->point_size
= MAX2(cso
->point_size
, .125f
);
107 if (cso
->offset_tri
) {
108 so
->offset_units
= float_to_187_half(cso
->offset_units
);
109 so
->z16_offset_units
= float_to_187_half(cso
->offset_units
* 256.0);
110 so
->offset_factor
= float_to_187_half(cso
->offset_scale
);
116 /* Blend state is baked into shaders. */
118 v3d_create_blend_state(struct pipe_context
*pctx
,
119 const struct pipe_blend_state
*cso
)
121 struct v3d_blend_state
*so
;
123 so
= CALLOC_STRUCT(v3d_blend_state
);
129 if (cso
->independent_blend_enable
) {
130 for (int i
= 0; i
< VC5_MAX_DRAW_BUFFERS
; i
++) {
131 so
->blend_enables
|= cso
->rt
[i
].blend_enable
<< i
;
133 /* V3D 4.x is when we got independent blend enables. */
134 assert(V3D_VERSION
>= 40 ||
135 cso
->rt
[i
].blend_enable
== cso
->rt
[0].blend_enable
);
138 if (cso
->rt
[0].blend_enable
)
139 so
->blend_enables
= (1 << VC5_MAX_DRAW_BUFFERS
) - 1;
146 translate_stencil_op(enum pipe_stencil_op op
)
149 case PIPE_STENCIL_OP_KEEP
: return V3D_STENCIL_OP_KEEP
;
150 case PIPE_STENCIL_OP_ZERO
: return V3D_STENCIL_OP_ZERO
;
151 case PIPE_STENCIL_OP_REPLACE
: return V3D_STENCIL_OP_REPLACE
;
152 case PIPE_STENCIL_OP_INCR
: return V3D_STENCIL_OP_INCR
;
153 case PIPE_STENCIL_OP_DECR
: return V3D_STENCIL_OP_DECR
;
154 case PIPE_STENCIL_OP_INCR_WRAP
: return V3D_STENCIL_OP_INCWRAP
;
155 case PIPE_STENCIL_OP_DECR_WRAP
: return V3D_STENCIL_OP_DECWRAP
;
156 case PIPE_STENCIL_OP_INVERT
: return V3D_STENCIL_OP_INVERT
;
158 unreachable("bad stencil op");
162 v3d_create_depth_stencil_alpha_state(struct pipe_context
*pctx
,
163 const struct pipe_depth_stencil_alpha_state
*cso
)
165 struct v3d_depth_stencil_alpha_state
*so
;
167 so
= CALLOC_STRUCT(v3d_depth_stencil_alpha_state
);
173 if (cso
->depth
.enabled
) {
174 switch (cso
->depth
.func
) {
176 case PIPE_FUNC_LEQUAL
:
177 so
->ez_state
= VC5_EZ_LT_LE
;
179 case PIPE_FUNC_GREATER
:
180 case PIPE_FUNC_GEQUAL
:
181 so
->ez_state
= VC5_EZ_GT_GE
;
183 case PIPE_FUNC_NEVER
:
184 case PIPE_FUNC_EQUAL
:
185 so
->ez_state
= VC5_EZ_UNDECIDED
;
188 so
->ez_state
= VC5_EZ_DISABLED
;
192 /* If stencil is enabled and it's not a no-op, then it would
195 if (cso
->stencil
[0].enabled
&&
196 (cso
->stencil
[0].zfail_op
!= PIPE_STENCIL_OP_KEEP
||
197 cso
->stencil
[0].func
!= PIPE_FUNC_ALWAYS
||
198 (cso
->stencil
[1].enabled
&&
199 (cso
->stencil
[1].zfail_op
!= PIPE_STENCIL_OP_KEEP
&&
200 cso
->stencil
[1].func
!= PIPE_FUNC_ALWAYS
)))) {
201 so
->ez_state
= VC5_EZ_DISABLED
;
205 const struct pipe_stencil_state
*front
= &cso
->stencil
[0];
206 const struct pipe_stencil_state
*back
= &cso
->stencil
[1];
208 if (front
->enabled
) {
209 STATIC_ASSERT(sizeof(so
->stencil_front
) >=
210 cl_packet_length(STENCIL_CONFIG
));
211 v3dx_pack(&so
->stencil_front
, STENCIL_CONFIG
, config
) {
212 config
.front_config
= true;
213 /* If !back->enabled, then the front values should be
214 * used for both front and back-facing primitives.
216 config
.back_config
= !back
->enabled
;
218 config
.stencil_write_mask
= front
->writemask
;
219 config
.stencil_test_mask
= front
->valuemask
;
221 config
.stencil_test_function
= front
->func
;
222 config
.stencil_pass_op
=
223 translate_stencil_op(front
->zpass_op
);
224 config
.depth_test_fail_op
=
225 translate_stencil_op(front
->zfail_op
);
226 config
.stencil_test_fail_op
=
227 translate_stencil_op(front
->fail_op
);
231 STATIC_ASSERT(sizeof(so
->stencil_back
) >=
232 cl_packet_length(STENCIL_CONFIG
));
233 v3dx_pack(&so
->stencil_back
, STENCIL_CONFIG
, config
) {
234 config
.front_config
= false;
235 config
.back_config
= true;
237 config
.stencil_write_mask
= back
->writemask
;
238 config
.stencil_test_mask
= back
->valuemask
;
240 config
.stencil_test_function
= back
->func
;
241 config
.stencil_pass_op
=
242 translate_stencil_op(back
->zpass_op
);
243 config
.depth_test_fail_op
=
244 translate_stencil_op(back
->zfail_op
);
245 config
.stencil_test_fail_op
=
246 translate_stencil_op(back
->fail_op
);
254 v3d_set_polygon_stipple(struct pipe_context
*pctx
,
255 const struct pipe_poly_stipple
*stipple
)
257 struct v3d_context
*v3d
= v3d_context(pctx
);
258 v3d
->stipple
= *stipple
;
259 v3d
->dirty
|= VC5_DIRTY_STIPPLE
;
263 v3d_set_scissor_states(struct pipe_context
*pctx
,
265 unsigned num_scissors
,
266 const struct pipe_scissor_state
*scissor
)
268 struct v3d_context
*v3d
= v3d_context(pctx
);
270 v3d
->scissor
= *scissor
;
271 v3d
->dirty
|= VC5_DIRTY_SCISSOR
;
275 v3d_set_viewport_states(struct pipe_context
*pctx
,
277 unsigned num_viewports
,
278 const struct pipe_viewport_state
*viewport
)
280 struct v3d_context
*v3d
= v3d_context(pctx
);
281 v3d
->viewport
= *viewport
;
282 v3d
->dirty
|= VC5_DIRTY_VIEWPORT
;
286 v3d_set_vertex_buffers(struct pipe_context
*pctx
,
287 unsigned start_slot
, unsigned count
,
288 const struct pipe_vertex_buffer
*vb
)
290 struct v3d_context
*v3d
= v3d_context(pctx
);
291 struct v3d_vertexbuf_stateobj
*so
= &v3d
->vertexbuf
;
293 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
,
295 so
->count
= util_last_bit(so
->enabled_mask
);
297 v3d
->dirty
|= VC5_DIRTY_VTXBUF
;
301 v3d_blend_state_bind(struct pipe_context
*pctx
, void *hwcso
)
303 struct v3d_context
*v3d
= v3d_context(pctx
);
305 v3d
->dirty
|= VC5_DIRTY_BLEND
;
309 v3d_rasterizer_state_bind(struct pipe_context
*pctx
, void *hwcso
)
311 struct v3d_context
*v3d
= v3d_context(pctx
);
312 v3d
->rasterizer
= hwcso
;
313 v3d
->dirty
|= VC5_DIRTY_RASTERIZER
;
317 v3d_zsa_state_bind(struct pipe_context
*pctx
, void *hwcso
)
319 struct v3d_context
*v3d
= v3d_context(pctx
);
321 v3d
->dirty
|= VC5_DIRTY_ZSA
;
325 v3d_vertex_state_create(struct pipe_context
*pctx
, unsigned num_elements
,
326 const struct pipe_vertex_element
*elements
)
328 struct v3d_context
*v3d
= v3d_context(pctx
);
329 struct v3d_vertex_stateobj
*so
= CALLOC_STRUCT(v3d_vertex_stateobj
);
334 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
335 so
->num_elements
= num_elements
;
337 for (int i
= 0; i
< so
->num_elements
; i
++) {
338 const struct pipe_vertex_element
*elem
= &elements
[i
];
339 const struct util_format_description
*desc
=
340 util_format_description(elem
->src_format
);
341 uint32_t r_size
= desc
->channel
[0].size
;
343 const uint32_t size
=
344 cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD
);
346 v3dx_pack(&so
->attrs
[i
* size
],
347 GL_SHADER_STATE_ATTRIBUTE_RECORD
, attr
) {
348 /* vec_size == 0 means 4 */
349 attr
.vec_size
= desc
->nr_channels
& 3;
350 attr
.signed_int_type
= (desc
->channel
[0].type
==
351 UTIL_FORMAT_TYPE_SIGNED
);
353 attr
.normalized_int_type
= desc
->channel
[0].normalized
;
354 attr
.read_as_int_uint
= desc
->channel
[0].pure_integer
;
355 attr
.instance_divisor
= MIN2(elem
->instance_divisor
,
358 switch (desc
->channel
[0].type
) {
359 case UTIL_FORMAT_TYPE_FLOAT
:
361 attr
.type
= ATTRIBUTE_FLOAT
;
363 assert(r_size
== 16);
364 attr
.type
= ATTRIBUTE_HALF_FLOAT
;
368 case UTIL_FORMAT_TYPE_SIGNED
:
369 case UTIL_FORMAT_TYPE_UNSIGNED
:
372 attr
.type
= ATTRIBUTE_INT
;
375 attr
.type
= ATTRIBUTE_SHORT
;
378 attr
.type
= ATTRIBUTE_INT2_10_10_10
;
381 attr
.type
= ATTRIBUTE_BYTE
;
385 "format %s unsupported\n",
387 attr
.type
= ATTRIBUTE_BYTE
;
394 "format %s unsupported\n",
401 /* Set up the default attribute values in case any of the vertex
404 so
->default_attribute_values
= v3d_bo_alloc(v3d
->screen
,
407 "default_attributes");
408 uint32_t *attrs
= v3d_bo_map(so
->default_attribute_values
);
409 for (int i
= 0; i
< VC5_MAX_ATTRIBUTES
; i
++) {
410 attrs
[i
* 4 + 0] = 0;
411 attrs
[i
* 4 + 1] = 0;
412 attrs
[i
* 4 + 2] = 0;
413 if (i
< so
->num_elements
&&
414 util_format_is_pure_integer(so
->pipe
[i
].src_format
)) {
415 attrs
[i
* 4 + 3] = 1;
417 attrs
[i
* 4 + 3] = fui(1.0);
425 v3d_vertex_state_delete(struct pipe_context
*pctx
, void *hwcso
)
427 struct v3d_vertex_stateobj
*so
= hwcso
;
429 v3d_bo_unreference(&so
->default_attribute_values
);
434 v3d_vertex_state_bind(struct pipe_context
*pctx
, void *hwcso
)
436 struct v3d_context
*v3d
= v3d_context(pctx
);
438 v3d
->dirty
|= VC5_DIRTY_VTXSTATE
;
442 v3d_set_constant_buffer(struct pipe_context
*pctx
, uint shader
, uint index
,
443 const struct pipe_constant_buffer
*cb
)
445 struct v3d_context
*v3d
= v3d_context(pctx
);
446 struct v3d_constbuf_stateobj
*so
= &v3d
->constbuf
[shader
];
448 util_copy_constant_buffer(&so
->cb
[index
], cb
);
450 /* Note that the state tracker can unbind constant buffers by
454 so
->enabled_mask
&= ~(1 << index
);
455 so
->dirty_mask
&= ~(1 << index
);
459 so
->enabled_mask
|= 1 << index
;
460 so
->dirty_mask
|= 1 << index
;
461 v3d
->dirty
|= VC5_DIRTY_CONSTBUF
;
465 v3d_set_framebuffer_state(struct pipe_context
*pctx
,
466 const struct pipe_framebuffer_state
*framebuffer
)
468 struct v3d_context
*v3d
= v3d_context(pctx
);
469 struct pipe_framebuffer_state
*cso
= &v3d
->framebuffer
;
473 util_copy_framebuffer_state(cso
, framebuffer
);
475 v3d
->swap_color_rb
= 0;
476 v3d
->blend_dst_alpha_one
= 0;
477 for (int i
= 0; i
< v3d
->framebuffer
.nr_cbufs
; i
++) {
478 struct pipe_surface
*cbuf
= v3d
->framebuffer
.cbufs
[i
];
482 const struct util_format_description
*desc
=
483 util_format_description(cbuf
->format
);
485 /* For BGRA8 formats (DRI window system default format), we
486 * need to swap R and B, since the HW's format is RGBA8.
488 if (desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
489 cbuf
->format
!= PIPE_FORMAT_B5G6R5_UNORM
) {
490 v3d
->swap_color_rb
|= 1 << i
;
493 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
494 v3d
->blend_dst_alpha_one
|= 1 << i
;
497 v3d
->dirty
|= VC5_DIRTY_FRAMEBUFFER
;
500 static struct v3d_texture_stateobj
*
501 v3d_get_stage_tex(struct v3d_context
*v3d
, enum pipe_shader_type shader
)
504 case PIPE_SHADER_FRAGMENT
:
505 v3d
->dirty
|= VC5_DIRTY_FRAGTEX
;
506 return &v3d
->fragtex
;
508 case PIPE_SHADER_VERTEX
:
509 v3d
->dirty
|= VC5_DIRTY_VERTTEX
;
510 return &v3d
->verttex
;
513 fprintf(stderr
, "Unknown shader target %d\n", shader
);
518 static uint32_t translate_wrap(uint32_t pipe_wrap
, bool using_nearest
)
521 case PIPE_TEX_WRAP_REPEAT
:
523 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
525 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
527 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
529 case PIPE_TEX_WRAP_CLAMP
:
530 return (using_nearest
? 1 : 3);
532 unreachable("Unknown wrap mode");
538 v3d_create_sampler_state(struct pipe_context
*pctx
,
539 const struct pipe_sampler_state
*cso
)
541 MAYBE_UNUSED
struct v3d_context
*v3d
= v3d_context(pctx
);
542 struct v3d_sampler_state
*so
= CALLOC_STRUCT(v3d_sampler_state
);
547 memcpy(so
, cso
, sizeof(*cso
));
549 bool either_nearest
=
550 (cso
->mag_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
||
551 cso
->min_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
);
553 #if V3D_VERSION >= 40
554 so
->bo
= v3d_bo_alloc(v3d
->screen
, cl_packet_length(SAMPLER_STATE
),
556 void *map
= v3d_bo_map(so
->bo
);
558 v3dx_pack(map
, SAMPLER_STATE
, sampler
) {
559 sampler
.wrap_i_border
= false;
561 sampler
.wrap_s
= translate_wrap(cso
->wrap_s
, either_nearest
);
562 sampler
.wrap_t
= translate_wrap(cso
->wrap_t
, either_nearest
);
563 sampler
.wrap_r
= translate_wrap(cso
->wrap_r
, either_nearest
);
565 sampler
.fixed_bias
= cso
->lod_bias
;
566 sampler
.depth_compare_function
= cso
->compare_func
;
568 sampler
.min_filter_nearest
=
569 cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
570 sampler
.mag_filter_nearest
=
571 cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
572 sampler
.mip_filter_nearest
=
573 cso
->min_mip_filter
!= PIPE_TEX_MIPFILTER_LINEAR
;
575 sampler
.min_level_of_detail
= MIN2(MAX2(0, cso
->min_lod
),
577 sampler
.max_level_of_detail
= MIN2(cso
->max_lod
, 15);
579 /* If we're not doing inter-miplevel filtering, we need to
580 * clamp the LOD so that we only sample from baselevel.
581 * However, we need to still allow the calculated LOD to be
582 * fractionally over the baselevel, so that the HW can decide
583 * between the min and mag filters.
585 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
586 sampler
.min_level_of_detail
=
587 MIN2(sampler
.min_level_of_detail
, 1.0 / 256.0);
588 sampler
.max_level_of_detail
=
589 MIN2(sampler
.max_level_of_detail
, 1.0 / 256.0);
592 if (cso
->max_anisotropy
) {
593 sampler
.anisotropy_enable
= true;
595 if (cso
->max_anisotropy
> 8)
596 sampler
.maximum_anisotropy
= 3;
597 else if (cso
->max_anisotropy
> 4)
598 sampler
.maximum_anisotropy
= 2;
599 else if (cso
->max_anisotropy
> 2)
600 sampler
.maximum_anisotropy
= 1;
603 sampler
.border_colour_mode
= V3D_BORDER_COLOUR_FOLLOWS
;
604 /* XXX: The border colour field is in the TMU blending format
605 * (32, f16, or i16), and we need to customize it based on
608 * XXX: for compat alpha formats, we need the alpha field to
609 * be in the red channel.
611 sampler
.border_colour_red
=
612 util_float_to_half(cso
->border_color
.f
[0]);
613 sampler
.border_colour_green
=
614 util_float_to_half(cso
->border_color
.f
[1]);
615 sampler
.border_colour_blue
=
616 util_float_to_half(cso
->border_color
.f
[2]);
617 sampler
.border_colour_alpha
=
618 util_float_to_half(cso
->border_color
.f
[3]);
621 #else /* V3D_VERSION < 40 */
622 v3dx_pack(&so
->p0
, TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1
, p0
) {
623 p0
.s_wrap_mode
= translate_wrap(cso
->wrap_s
, either_nearest
);
624 p0
.t_wrap_mode
= translate_wrap(cso
->wrap_t
, either_nearest
);
625 p0
.r_wrap_mode
= translate_wrap(cso
->wrap_r
, either_nearest
);
628 v3dx_pack(&so
->texture_shader_state
, TEXTURE_SHADER_STATE
, tex
) {
629 tex
.depth_compare_function
= cso
->compare_func
;
630 tex
.fixed_bias
= cso
->lod_bias
;
632 #endif /* V3D_VERSION < 40 */
637 v3d_sampler_states_bind(struct pipe_context
*pctx
,
638 enum pipe_shader_type shader
, unsigned start
,
639 unsigned nr
, void **hwcso
)
641 struct v3d_context
*v3d
= v3d_context(pctx
);
642 struct v3d_texture_stateobj
*stage_tex
= v3d_get_stage_tex(v3d
, shader
);
648 for (i
= 0; i
< nr
; i
++) {
651 stage_tex
->samplers
[i
] = hwcso
[i
];
654 for (; i
< stage_tex
->num_samplers
; i
++) {
655 stage_tex
->samplers
[i
] = NULL
;
658 stage_tex
->num_samplers
= new_nr
;
662 v3d_sampler_state_delete(struct pipe_context
*pctx
,
665 struct pipe_sampler_state
*psampler
= hwcso
;
666 struct v3d_sampler_state
*sampler
= v3d_sampler_state(psampler
);
668 v3d_bo_unreference(&sampler
->bo
);
672 #if V3D_VERSION >= 40
674 translate_swizzle(unsigned char pipe_swizzle
)
676 switch (pipe_swizzle
) {
685 return 2 + pipe_swizzle
;
687 unreachable("unknown swizzle");
692 static struct pipe_sampler_view
*
693 v3d_create_sampler_view(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
694 const struct pipe_sampler_view
*cso
)
696 struct v3d_context
*v3d
= v3d_context(pctx
);
697 struct v3d_screen
*screen
= v3d
->screen
;
698 struct v3d_sampler_view
*so
= CALLOC_STRUCT(v3d_sampler_view
);
699 struct v3d_resource
*rsc
= v3d_resource(prsc
);
706 pipe_reference(NULL
, &prsc
->reference
);
708 /* Compute the sampler view's swizzle up front. This will be plugged
709 * into either the sampler (for 16-bit returns) or the shader's
710 * texture key (for 32)
712 uint8_t view_swizzle
[4] = {
718 const uint8_t *fmt_swizzle
=
719 v3d_get_format_swizzle(&screen
->devinfo
, so
->base
.format
);
720 util_format_compose_swizzles(fmt_swizzle
, view_swizzle
, so
->swizzle
);
722 so
->base
.texture
= prsc
;
723 so
->base
.reference
.count
= 1;
724 so
->base
.context
= pctx
;
726 int msaa_scale
= prsc
->nr_samples
> 1 ? 2 : 1;
728 #if V3D_VERSION >= 40
729 so
->bo
= v3d_bo_alloc(v3d
->screen
,
730 cl_packet_length(TEXTURE_SHADER_STATE
), "sampler");
731 void *map
= v3d_bo_map(so
->bo
);
733 v3dx_pack(map
, TEXTURE_SHADER_STATE
, tex
) {
734 #else /* V3D_VERSION < 40 */
735 STATIC_ASSERT(sizeof(so
->texture_shader_state
) >=
736 cl_packet_length(TEXTURE_SHADER_STATE
));
737 v3dx_pack(&so
->texture_shader_state
, TEXTURE_SHADER_STATE
, tex
) {
740 tex
.image_width
= prsc
->width0
* msaa_scale
;
741 tex
.image_height
= prsc
->height0
* msaa_scale
;
743 #if V3D_VERSION >= 40
744 /* On 4.x, the height of a 1D texture is redefined to be the
745 * upper 14 bits of the width (which is only usable with txf).
747 if (prsc
->target
== PIPE_TEXTURE_1D
||
748 prsc
->target
== PIPE_TEXTURE_1D_ARRAY
) {
749 tex
.image_height
= tex
.image_width
>> 14;
753 if (prsc
->target
== PIPE_TEXTURE_3D
) {
754 tex
.image_depth
= prsc
->depth0
;
756 tex
.image_depth
= (cso
->u
.tex
.last_layer
-
757 cso
->u
.tex
.first_layer
) + 1;
760 tex
.srgb
= util_format_is_srgb(cso
->format
);
762 tex
.base_level
= cso
->u
.tex
.first_level
;
763 #if V3D_VERSION >= 40
764 tex
.max_level
= cso
->u
.tex
.last_level
;
765 /* Note that we don't have a job to reference the texture's sBO
766 * at state create time, so any time this sampler view is used
767 * we need to add the texture to the job.
769 tex
.texture_base_pointer
= cl_address(NULL
,
771 rsc
->slices
[0].offset
+
772 cso
->u
.tex
.first_layer
*
773 rsc
->cube_map_stride
),
775 tex
.swizzle_r
= translate_swizzle(so
->swizzle
[0]);
776 tex
.swizzle_g
= translate_swizzle(so
->swizzle
[1]);
777 tex
.swizzle_b
= translate_swizzle(so
->swizzle
[2]);
778 tex
.swizzle_a
= translate_swizzle(so
->swizzle
[3]);
780 tex
.array_stride_64_byte_aligned
= rsc
->cube_map_stride
/ 64;
782 if (prsc
->nr_samples
> 1 && V3D_VERSION
< 40) {
783 /* Using texture views to reinterpret formats on our
784 * MSAA textures won't work, because we don't lay out
785 * the bits in memory as it's expected -- for example,
786 * RGBA8 and RGB10_A2 are compatible in the
787 * ARB_texture_view spec, but in HW we lay them out as
788 * 32bpp RGBA8 and 64bpp RGBA16F. Just assert for now
791 * We explicitly allow remapping S8Z24 to RGBA8888 for
792 * v3d_blit.c's stencil blits.
794 assert((util_format_linear(cso
->format
) ==
795 util_format_linear(prsc
->format
)) ||
796 (prsc
->format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
&&
797 cso
->format
== PIPE_FORMAT_R8G8B8A8_UNORM
));
798 uint32_t output_image_format
=
799 v3d_get_rt_format(&screen
->devinfo
, cso
->format
);
800 uint32_t internal_type
;
801 uint32_t internal_bpp
;
802 v3d_get_internal_type_bpp_for_output_format(&screen
->devinfo
,
807 switch (internal_type
) {
808 case V3D_INTERNAL_TYPE_8
:
809 tex
.texture_type
= TEXTURE_DATA_FORMAT_RGBA8
;
811 case V3D_INTERNAL_TYPE_16F
:
812 tex
.texture_type
= TEXTURE_DATA_FORMAT_RGBA16F
;
815 unreachable("Bad MSAA texture type");
818 /* sRGB was stored in the tile buffer as linear and
819 * would have been encoded to sRGB on resolved tile
820 * buffer store. Note that this means we would need
821 * shader code if we wanted to read an MSAA sRGB
822 * texture without sRGB decode.
826 tex
.texture_type
= v3d_get_tex_format(&screen
->devinfo
,
830 /* Since other platform devices may produce UIF images even
831 * when they're not big enough for V3D to assume they're UIF,
832 * we force images with level 0 as UIF to be always treated
835 tex
.level_0_is_strictly_uif
= (rsc
->slices
[0].tiling
==
836 VC5_TILING_UIF_XOR
||
837 rsc
->slices
[0].tiling
==
838 VC5_TILING_UIF_NO_XOR
);
839 tex
.level_0_xor_enable
= (rsc
->slices
[0].tiling
==
842 if (tex
.level_0_is_strictly_uif
)
843 tex
.level_0_ub_pad
= rsc
->slices
[0].ub_pad
;
845 #if V3D_VERSION >= 40
846 if (tex
.uif_xor_disable
||
847 tex
.level_0_is_strictly_uif
) {
850 #endif /* V3D_VERSION >= 40 */
857 v3d_sampler_view_destroy(struct pipe_context
*pctx
,
858 struct pipe_sampler_view
*psview
)
860 struct v3d_sampler_view
*sview
= v3d_sampler_view(psview
);
862 v3d_bo_unreference(&sview
->bo
);
863 pipe_resource_reference(&psview
->texture
, NULL
);
868 v3d_set_sampler_views(struct pipe_context
*pctx
,
869 enum pipe_shader_type shader
,
870 unsigned start
, unsigned nr
,
871 struct pipe_sampler_view
**views
)
873 struct v3d_context
*v3d
= v3d_context(pctx
);
874 struct v3d_texture_stateobj
*stage_tex
= v3d_get_stage_tex(v3d
, shader
);
880 for (i
= 0; i
< nr
; i
++) {
883 pipe_sampler_view_reference(&stage_tex
->textures
[i
], views
[i
]);
886 for (; i
< stage_tex
->num_textures
; i
++) {
887 pipe_sampler_view_reference(&stage_tex
->textures
[i
], NULL
);
890 stage_tex
->num_textures
= new_nr
;
893 static struct pipe_stream_output_target
*
894 v3d_create_stream_output_target(struct pipe_context
*pctx
,
895 struct pipe_resource
*prsc
,
896 unsigned buffer_offset
,
897 unsigned buffer_size
)
899 struct pipe_stream_output_target
*target
;
901 target
= CALLOC_STRUCT(pipe_stream_output_target
);
905 pipe_reference_init(&target
->reference
, 1);
906 pipe_resource_reference(&target
->buffer
, prsc
);
908 target
->context
= pctx
;
909 target
->buffer_offset
= buffer_offset
;
910 target
->buffer_size
= buffer_size
;
916 v3d_stream_output_target_destroy(struct pipe_context
*pctx
,
917 struct pipe_stream_output_target
*target
)
919 pipe_resource_reference(&target
->buffer
, NULL
);
924 v3d_set_stream_output_targets(struct pipe_context
*pctx
,
925 unsigned num_targets
,
926 struct pipe_stream_output_target
**targets
,
927 const unsigned *offsets
)
929 struct v3d_context
*ctx
= v3d_context(pctx
);
930 struct v3d_streamout_stateobj
*so
= &ctx
->streamout
;
933 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
935 for (i
= 0; i
< num_targets
; i
++) {
936 if (offsets
[i
] != -1)
937 so
->offsets
[i
] = offsets
[i
];
939 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
942 for (; i
< so
->num_targets
; i
++)
943 pipe_so_target_reference(&so
->targets
[i
], NULL
);
945 so
->num_targets
= num_targets
;
947 ctx
->dirty
|= VC5_DIRTY_STREAMOUT
;
951 v3dX(state_init
)(struct pipe_context
*pctx
)
953 pctx
->set_blend_color
= v3d_set_blend_color
;
954 pctx
->set_stencil_ref
= v3d_set_stencil_ref
;
955 pctx
->set_clip_state
= v3d_set_clip_state
;
956 pctx
->set_sample_mask
= v3d_set_sample_mask
;
957 pctx
->set_constant_buffer
= v3d_set_constant_buffer
;
958 pctx
->set_framebuffer_state
= v3d_set_framebuffer_state
;
959 pctx
->set_polygon_stipple
= v3d_set_polygon_stipple
;
960 pctx
->set_scissor_states
= v3d_set_scissor_states
;
961 pctx
->set_viewport_states
= v3d_set_viewport_states
;
963 pctx
->set_vertex_buffers
= v3d_set_vertex_buffers
;
965 pctx
->create_blend_state
= v3d_create_blend_state
;
966 pctx
->bind_blend_state
= v3d_blend_state_bind
;
967 pctx
->delete_blend_state
= v3d_generic_cso_state_delete
;
969 pctx
->create_rasterizer_state
= v3d_create_rasterizer_state
;
970 pctx
->bind_rasterizer_state
= v3d_rasterizer_state_bind
;
971 pctx
->delete_rasterizer_state
= v3d_generic_cso_state_delete
;
973 pctx
->create_depth_stencil_alpha_state
= v3d_create_depth_stencil_alpha_state
;
974 pctx
->bind_depth_stencil_alpha_state
= v3d_zsa_state_bind
;
975 pctx
->delete_depth_stencil_alpha_state
= v3d_generic_cso_state_delete
;
977 pctx
->create_vertex_elements_state
= v3d_vertex_state_create
;
978 pctx
->delete_vertex_elements_state
= v3d_vertex_state_delete
;
979 pctx
->bind_vertex_elements_state
= v3d_vertex_state_bind
;
981 pctx
->create_sampler_state
= v3d_create_sampler_state
;
982 pctx
->delete_sampler_state
= v3d_sampler_state_delete
;
983 pctx
->bind_sampler_states
= v3d_sampler_states_bind
;
985 pctx
->create_sampler_view
= v3d_create_sampler_view
;
986 pctx
->sampler_view_destroy
= v3d_sampler_view_destroy
;
987 pctx
->set_sampler_views
= v3d_set_sampler_views
;
989 pctx
->create_stream_output_target
= v3d_create_stream_output_target
;
990 pctx
->stream_output_target_destroy
= v3d_stream_output_target_destroy
;
991 pctx
->set_stream_output_targets
= v3d_set_stream_output_targets
;