v3d: Add proper support for GL_EXT_draw_buffers2's blending enables.
[mesa.git] / src / gallium / drivers / v3d / v3dx_state.c
1 /*
2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "pipe/p_state.h"
26 #include "util/u_format.h"
27 #include "util/u_framebuffer.h"
28 #include "util/u_inlines.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/u_half.h"
32 #include "util/u_helpers.h"
33
34 #include "v3d_context.h"
35 #include "v3d_tiling.h"
36 #include "broadcom/common/v3d_macros.h"
37 #include "broadcom/cle/v3dx_pack.h"
38
39 static void
40 v3d_generic_cso_state_delete(struct pipe_context *pctx, void *hwcso)
41 {
42 free(hwcso);
43 }
44
45 static void
46 v3d_set_blend_color(struct pipe_context *pctx,
47 const struct pipe_blend_color *blend_color)
48 {
49 struct v3d_context *v3d = v3d_context(pctx);
50 v3d->blend_color.f = *blend_color;
51 for (int i = 0; i < 4; i++) {
52 v3d->blend_color.hf[i] =
53 util_float_to_half(blend_color->color[i]);
54 }
55 v3d->dirty |= VC5_DIRTY_BLEND_COLOR;
56 }
57
58 static void
59 v3d_set_stencil_ref(struct pipe_context *pctx,
60 const struct pipe_stencil_ref *stencil_ref)
61 {
62 struct v3d_context *v3d = v3d_context(pctx);
63 v3d->stencil_ref = *stencil_ref;
64 v3d->dirty |= VC5_DIRTY_STENCIL_REF;
65 }
66
67 static void
68 v3d_set_clip_state(struct pipe_context *pctx,
69 const struct pipe_clip_state *clip)
70 {
71 struct v3d_context *v3d = v3d_context(pctx);
72 v3d->clip = *clip;
73 v3d->dirty |= VC5_DIRTY_CLIP;
74 }
75
76 static void
77 v3d_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
78 {
79 struct v3d_context *v3d = v3d_context(pctx);
80 v3d->sample_mask = sample_mask & ((1 << VC5_MAX_SAMPLES) - 1);
81 v3d->dirty |= VC5_DIRTY_SAMPLE_STATE;
82 }
83
84 static uint16_t
85 float_to_187_half(float f)
86 {
87 return fui(f) >> 16;
88 }
89
90 static void *
91 v3d_create_rasterizer_state(struct pipe_context *pctx,
92 const struct pipe_rasterizer_state *cso)
93 {
94 struct v3d_rasterizer_state *so;
95
96 so = CALLOC_STRUCT(v3d_rasterizer_state);
97 if (!so)
98 return NULL;
99
100 so->base = *cso;
101
102 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
103 * BCM21553).
104 */
105 so->point_size = MAX2(cso->point_size, .125f);
106
107 if (cso->offset_tri) {
108 so->offset_units = float_to_187_half(cso->offset_units);
109 so->z16_offset_units = float_to_187_half(cso->offset_units * 256.0);
110 so->offset_factor = float_to_187_half(cso->offset_scale);
111 }
112
113 return so;
114 }
115
116 /* Blend state is baked into shaders. */
117 static void *
118 v3d_create_blend_state(struct pipe_context *pctx,
119 const struct pipe_blend_state *cso)
120 {
121 struct v3d_blend_state *so;
122
123 so = CALLOC_STRUCT(v3d_blend_state);
124 if (!so)
125 return NULL;
126
127 so->base = *cso;
128
129 for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
130 so->blend_enables |= cso->rt[i].blend_enable << i;
131
132 /* V3D 4.x is when we got independent blend enables. */
133 assert(V3D_VERSION >= 40 ||
134 cso->rt[i].blend_enable == cso->rt[0].blend_enable);
135 }
136
137 return so;
138 }
139
140 static uint32_t
141 translate_stencil_op(enum pipe_stencil_op op)
142 {
143 switch (op) {
144 case PIPE_STENCIL_OP_KEEP: return V3D_STENCIL_OP_KEEP;
145 case PIPE_STENCIL_OP_ZERO: return V3D_STENCIL_OP_ZERO;
146 case PIPE_STENCIL_OP_REPLACE: return V3D_STENCIL_OP_REPLACE;
147 case PIPE_STENCIL_OP_INCR: return V3D_STENCIL_OP_INCR;
148 case PIPE_STENCIL_OP_DECR: return V3D_STENCIL_OP_DECR;
149 case PIPE_STENCIL_OP_INCR_WRAP: return V3D_STENCIL_OP_INCWRAP;
150 case PIPE_STENCIL_OP_DECR_WRAP: return V3D_STENCIL_OP_DECWRAP;
151 case PIPE_STENCIL_OP_INVERT: return V3D_STENCIL_OP_INVERT;
152 }
153 unreachable("bad stencil op");
154 }
155
156 static void *
157 v3d_create_depth_stencil_alpha_state(struct pipe_context *pctx,
158 const struct pipe_depth_stencil_alpha_state *cso)
159 {
160 struct v3d_depth_stencil_alpha_state *so;
161
162 so = CALLOC_STRUCT(v3d_depth_stencil_alpha_state);
163 if (!so)
164 return NULL;
165
166 so->base = *cso;
167
168 if (cso->depth.enabled) {
169 switch (cso->depth.func) {
170 case PIPE_FUNC_LESS:
171 case PIPE_FUNC_LEQUAL:
172 so->ez_state = VC5_EZ_LT_LE;
173 break;
174 case PIPE_FUNC_GREATER:
175 case PIPE_FUNC_GEQUAL:
176 so->ez_state = VC5_EZ_GT_GE;
177 break;
178 case PIPE_FUNC_NEVER:
179 case PIPE_FUNC_EQUAL:
180 so->ez_state = VC5_EZ_UNDECIDED;
181 break;
182 default:
183 so->ez_state = VC5_EZ_DISABLED;
184 break;
185 }
186
187 /* If stencil is enabled and it's not a no-op, then it would
188 * break EZ updates.
189 */
190 if (cso->stencil[0].enabled &&
191 (cso->stencil[0].zfail_op != PIPE_STENCIL_OP_KEEP ||
192 cso->stencil[0].func != PIPE_FUNC_ALWAYS ||
193 (cso->stencil[1].enabled &&
194 (cso->stencil[1].zfail_op != PIPE_STENCIL_OP_KEEP &&
195 cso->stencil[1].func != PIPE_FUNC_ALWAYS)))) {
196 so->ez_state = VC5_EZ_DISABLED;
197 }
198 }
199
200 const struct pipe_stencil_state *front = &cso->stencil[0];
201 const struct pipe_stencil_state *back = &cso->stencil[1];
202
203 if (front->enabled) {
204 STATIC_ASSERT(sizeof(so->stencil_front) >=
205 cl_packet_length(STENCIL_CONFIG));
206 v3dx_pack(&so->stencil_front, STENCIL_CONFIG, config) {
207 config.front_config = true;
208 /* If !back->enabled, then the front values should be
209 * used for both front and back-facing primitives.
210 */
211 config.back_config = !back->enabled;
212
213 config.stencil_write_mask = front->writemask;
214 config.stencil_test_mask = front->valuemask;
215
216 config.stencil_test_function = front->func;
217 config.stencil_pass_op =
218 translate_stencil_op(front->zpass_op);
219 config.depth_test_fail_op =
220 translate_stencil_op(front->zfail_op);
221 config.stencil_test_fail_op =
222 translate_stencil_op(front->fail_op);
223 }
224 }
225 if (back->enabled) {
226 STATIC_ASSERT(sizeof(so->stencil_back) >=
227 cl_packet_length(STENCIL_CONFIG));
228 v3dx_pack(&so->stencil_back, STENCIL_CONFIG, config) {
229 config.front_config = false;
230 config.back_config = true;
231
232 config.stencil_write_mask = back->writemask;
233 config.stencil_test_mask = back->valuemask;
234
235 config.stencil_test_function = back->func;
236 config.stencil_pass_op =
237 translate_stencil_op(back->zpass_op);
238 config.depth_test_fail_op =
239 translate_stencil_op(back->zfail_op);
240 config.stencil_test_fail_op =
241 translate_stencil_op(back->fail_op);
242 }
243 }
244
245 return so;
246 }
247
248 static void
249 v3d_set_polygon_stipple(struct pipe_context *pctx,
250 const struct pipe_poly_stipple *stipple)
251 {
252 struct v3d_context *v3d = v3d_context(pctx);
253 v3d->stipple = *stipple;
254 v3d->dirty |= VC5_DIRTY_STIPPLE;
255 }
256
257 static void
258 v3d_set_scissor_states(struct pipe_context *pctx,
259 unsigned start_slot,
260 unsigned num_scissors,
261 const struct pipe_scissor_state *scissor)
262 {
263 struct v3d_context *v3d = v3d_context(pctx);
264
265 v3d->scissor = *scissor;
266 v3d->dirty |= VC5_DIRTY_SCISSOR;
267 }
268
269 static void
270 v3d_set_viewport_states(struct pipe_context *pctx,
271 unsigned start_slot,
272 unsigned num_viewports,
273 const struct pipe_viewport_state *viewport)
274 {
275 struct v3d_context *v3d = v3d_context(pctx);
276 v3d->viewport = *viewport;
277 v3d->dirty |= VC5_DIRTY_VIEWPORT;
278 }
279
280 static void
281 v3d_set_vertex_buffers(struct pipe_context *pctx,
282 unsigned start_slot, unsigned count,
283 const struct pipe_vertex_buffer *vb)
284 {
285 struct v3d_context *v3d = v3d_context(pctx);
286 struct v3d_vertexbuf_stateobj *so = &v3d->vertexbuf;
287
288 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
289 start_slot, count);
290 so->count = util_last_bit(so->enabled_mask);
291
292 v3d->dirty |= VC5_DIRTY_VTXBUF;
293 }
294
295 static void
296 v3d_blend_state_bind(struct pipe_context *pctx, void *hwcso)
297 {
298 struct v3d_context *v3d = v3d_context(pctx);
299 v3d->blend = hwcso;
300 v3d->dirty |= VC5_DIRTY_BLEND;
301 }
302
303 static void
304 v3d_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
305 {
306 struct v3d_context *v3d = v3d_context(pctx);
307 v3d->rasterizer = hwcso;
308 v3d->dirty |= VC5_DIRTY_RASTERIZER;
309 }
310
311 static void
312 v3d_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
313 {
314 struct v3d_context *v3d = v3d_context(pctx);
315 v3d->zsa = hwcso;
316 v3d->dirty |= VC5_DIRTY_ZSA;
317 }
318
319 static void *
320 v3d_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
321 const struct pipe_vertex_element *elements)
322 {
323 struct v3d_context *v3d = v3d_context(pctx);
324 struct v3d_vertex_stateobj *so = CALLOC_STRUCT(v3d_vertex_stateobj);
325
326 if (!so)
327 return NULL;
328
329 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
330 so->num_elements = num_elements;
331
332 for (int i = 0; i < so->num_elements; i++) {
333 const struct pipe_vertex_element *elem = &elements[i];
334 const struct util_format_description *desc =
335 util_format_description(elem->src_format);
336 uint32_t r_size = desc->channel[0].size;
337
338 const uint32_t size =
339 cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD);
340
341 v3dx_pack(&so->attrs[i * size],
342 GL_SHADER_STATE_ATTRIBUTE_RECORD, attr) {
343 /* vec_size == 0 means 4 */
344 attr.vec_size = desc->nr_channels & 3;
345 attr.signed_int_type = (desc->channel[0].type ==
346 UTIL_FORMAT_TYPE_SIGNED);
347
348 attr.normalized_int_type = desc->channel[0].normalized;
349 attr.read_as_int_uint = desc->channel[0].pure_integer;
350 attr.instance_divisor = MIN2(elem->instance_divisor,
351 0xffff);
352
353 switch (desc->channel[0].type) {
354 case UTIL_FORMAT_TYPE_FLOAT:
355 if (r_size == 32) {
356 attr.type = ATTRIBUTE_FLOAT;
357 } else {
358 assert(r_size == 16);
359 attr.type = ATTRIBUTE_HALF_FLOAT;
360 }
361 break;
362
363 case UTIL_FORMAT_TYPE_SIGNED:
364 case UTIL_FORMAT_TYPE_UNSIGNED:
365 switch (r_size) {
366 case 32:
367 attr.type = ATTRIBUTE_INT;
368 break;
369 case 16:
370 attr.type = ATTRIBUTE_SHORT;
371 break;
372 case 10:
373 attr.type = ATTRIBUTE_INT2_10_10_10;
374 break;
375 case 8:
376 attr.type = ATTRIBUTE_BYTE;
377 break;
378 default:
379 fprintf(stderr,
380 "format %s unsupported\n",
381 desc->name);
382 attr.type = ATTRIBUTE_BYTE;
383 abort();
384 }
385 break;
386
387 default:
388 fprintf(stderr,
389 "format %s unsupported\n",
390 desc->name);
391 abort();
392 }
393 }
394 }
395
396 /* Set up the default attribute values in case any of the vertex
397 * elements use them.
398 */
399 so->default_attribute_values = v3d_bo_alloc(v3d->screen,
400 VC5_MAX_ATTRIBUTES *
401 4 * sizeof(float),
402 "default attributes");
403 uint32_t *attrs = v3d_bo_map(so->default_attribute_values);
404 for (int i = 0; i < VC5_MAX_ATTRIBUTES; i++) {
405 attrs[i * 4 + 0] = 0;
406 attrs[i * 4 + 1] = 0;
407 attrs[i * 4 + 2] = 0;
408 if (i < so->num_elements &&
409 util_format_is_pure_integer(so->pipe[i].src_format)) {
410 attrs[i * 4 + 3] = 1;
411 } else {
412 attrs[i * 4 + 3] = fui(1.0);
413 }
414 }
415
416 return so;
417 }
418
419 static void
420 v3d_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
421 {
422 struct v3d_context *v3d = v3d_context(pctx);
423 v3d->vtx = hwcso;
424 v3d->dirty |= VC5_DIRTY_VTXSTATE;
425 }
426
427 static void
428 v3d_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
429 const struct pipe_constant_buffer *cb)
430 {
431 struct v3d_context *v3d = v3d_context(pctx);
432 struct v3d_constbuf_stateobj *so = &v3d->constbuf[shader];
433
434 util_copy_constant_buffer(&so->cb[index], cb);
435
436 /* Note that the state tracker can unbind constant buffers by
437 * passing NULL here.
438 */
439 if (unlikely(!cb)) {
440 so->enabled_mask &= ~(1 << index);
441 so->dirty_mask &= ~(1 << index);
442 return;
443 }
444
445 so->enabled_mask |= 1 << index;
446 so->dirty_mask |= 1 << index;
447 v3d->dirty |= VC5_DIRTY_CONSTBUF;
448 }
449
450 static void
451 v3d_set_framebuffer_state(struct pipe_context *pctx,
452 const struct pipe_framebuffer_state *framebuffer)
453 {
454 struct v3d_context *v3d = v3d_context(pctx);
455 struct pipe_framebuffer_state *cso = &v3d->framebuffer;
456
457 v3d->job = NULL;
458
459 util_copy_framebuffer_state(cso, framebuffer);
460
461 v3d->swap_color_rb = 0;
462 v3d->blend_dst_alpha_one = 0;
463 for (int i = 0; i < v3d->framebuffer.nr_cbufs; i++) {
464 struct pipe_surface *cbuf = v3d->framebuffer.cbufs[i];
465 if (!cbuf)
466 continue;
467
468 const struct util_format_description *desc =
469 util_format_description(cbuf->format);
470
471 /* For BGRA8 formats (DRI window system default format), we
472 * need to swap R and B, since the HW's format is RGBA8.
473 */
474 if (desc->swizzle[0] == PIPE_SWIZZLE_Z &&
475 cbuf->format != PIPE_FORMAT_B5G6R5_UNORM) {
476 v3d->swap_color_rb |= 1 << i;
477 }
478
479 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
480 v3d->blend_dst_alpha_one |= 1 << i;
481 }
482
483 v3d->dirty |= VC5_DIRTY_FRAMEBUFFER;
484 }
485
486 static struct v3d_texture_stateobj *
487 v3d_get_stage_tex(struct v3d_context *v3d, enum pipe_shader_type shader)
488 {
489 switch (shader) {
490 case PIPE_SHADER_FRAGMENT:
491 v3d->dirty |= VC5_DIRTY_FRAGTEX;
492 return &v3d->fragtex;
493 break;
494 case PIPE_SHADER_VERTEX:
495 v3d->dirty |= VC5_DIRTY_VERTTEX;
496 return &v3d->verttex;
497 break;
498 default:
499 fprintf(stderr, "Unknown shader target %d\n", shader);
500 abort();
501 }
502 }
503
504 static uint32_t translate_wrap(uint32_t pipe_wrap, bool using_nearest)
505 {
506 switch (pipe_wrap) {
507 case PIPE_TEX_WRAP_REPEAT:
508 return 0;
509 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
510 return 1;
511 case PIPE_TEX_WRAP_MIRROR_REPEAT:
512 return 2;
513 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
514 return 3;
515 case PIPE_TEX_WRAP_CLAMP:
516 return (using_nearest ? 1 : 3);
517 default:
518 unreachable("Unknown wrap mode");
519 }
520 }
521
522
523 static void *
524 v3d_create_sampler_state(struct pipe_context *pctx,
525 const struct pipe_sampler_state *cso)
526 {
527 MAYBE_UNUSED struct v3d_context *v3d = v3d_context(pctx);
528 struct v3d_sampler_state *so = CALLOC_STRUCT(v3d_sampler_state);
529
530 if (!so)
531 return NULL;
532
533 memcpy(so, cso, sizeof(*cso));
534
535 bool either_nearest =
536 (cso->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
537 cso->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
538
539 #if V3D_VERSION >= 40
540 so->bo = v3d_bo_alloc(v3d->screen, cl_packet_length(SAMPLER_STATE),
541 "sampler");
542 void *map = v3d_bo_map(so->bo);
543
544 v3dx_pack(map, SAMPLER_STATE, sampler) {
545 sampler.wrap_i_border = false;
546
547 sampler.wrap_s = translate_wrap(cso->wrap_s, either_nearest);
548 sampler.wrap_t = translate_wrap(cso->wrap_t, either_nearest);
549 sampler.wrap_r = translate_wrap(cso->wrap_r, either_nearest);
550
551 sampler.fixed_bias = cso->lod_bias;
552 sampler.depth_compare_function = cso->compare_func;
553
554 sampler.min_filter_nearest =
555 cso->min_img_filter == PIPE_TEX_FILTER_NEAREST;
556 sampler.mag_filter_nearest =
557 cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
558 sampler.mip_filter_nearest =
559 cso->min_mip_filter != PIPE_TEX_MIPFILTER_LINEAR;
560
561 sampler.min_level_of_detail = MIN2(MAX2(0, cso->min_lod),
562 15);
563 sampler.max_level_of_detail = MIN2(cso->max_lod, 15);
564
565 /* If we're not doing inter-miplevel filtering, we need to
566 * clamp the LOD so that we only sample from baselevel.
567 * However, we need to still allow the calculated LOD to be
568 * fractionally over the baselevel, so that the HW can decide
569 * between the min and mag filters.
570 */
571 if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) {
572 sampler.min_level_of_detail =
573 MIN2(sampler.min_level_of_detail, 1.0 / 256.0);
574 sampler.max_level_of_detail =
575 MIN2(sampler.max_level_of_detail, 1.0 / 256.0);
576 }
577
578 if (cso->max_anisotropy) {
579 sampler.anisotropy_enable = true;
580
581 if (cso->max_anisotropy > 8)
582 sampler.maximum_anisotropy = 3;
583 else if (cso->max_anisotropy > 4)
584 sampler.maximum_anisotropy = 2;
585 else if (cso->max_anisotropy > 2)
586 sampler.maximum_anisotropy = 1;
587 }
588
589 sampler.border_colour_mode = V3D_BORDER_COLOUR_FOLLOWS;
590 /* XXX: The border colour field is in the TMU blending format
591 * (32, f16, or i16), and we need to customize it based on
592 * that.
593 *
594 * XXX: for compat alpha formats, we need the alpha field to
595 * be in the red channel.
596 */
597 sampler.border_colour_red =
598 util_float_to_half(cso->border_color.f[0]);
599 sampler.border_colour_green =
600 util_float_to_half(cso->border_color.f[1]);
601 sampler.border_colour_blue =
602 util_float_to_half(cso->border_color.f[2]);
603 sampler.border_colour_alpha =
604 util_float_to_half(cso->border_color.f[3]);
605 }
606
607 #else /* V3D_VERSION < 40 */
608 v3dx_pack(&so->p0, TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1, p0) {
609 p0.s_wrap_mode = translate_wrap(cso->wrap_s, either_nearest);
610 p0.t_wrap_mode = translate_wrap(cso->wrap_t, either_nearest);
611 p0.r_wrap_mode = translate_wrap(cso->wrap_r, either_nearest);
612 }
613
614 v3dx_pack(&so->texture_shader_state, TEXTURE_SHADER_STATE, tex) {
615 tex.depth_compare_function = cso->compare_func;
616 tex.fixed_bias = cso->lod_bias;
617 }
618 #endif /* V3D_VERSION < 40 */
619 return so;
620 }
621
622 static void
623 v3d_sampler_states_bind(struct pipe_context *pctx,
624 enum pipe_shader_type shader, unsigned start,
625 unsigned nr, void **hwcso)
626 {
627 struct v3d_context *v3d = v3d_context(pctx);
628 struct v3d_texture_stateobj *stage_tex = v3d_get_stage_tex(v3d, shader);
629
630 assert(start == 0);
631 unsigned i;
632 unsigned new_nr = 0;
633
634 for (i = 0; i < nr; i++) {
635 if (hwcso[i])
636 new_nr = i + 1;
637 stage_tex->samplers[i] = hwcso[i];
638 }
639
640 for (; i < stage_tex->num_samplers; i++) {
641 stage_tex->samplers[i] = NULL;
642 }
643
644 stage_tex->num_samplers = new_nr;
645 }
646
647 static void
648 v3d_sampler_state_delete(struct pipe_context *pctx,
649 void *hwcso)
650 {
651 struct pipe_sampler_state *psampler = hwcso;
652 struct v3d_sampler_state *sampler = v3d_sampler_state(psampler);
653
654 v3d_bo_unreference(&sampler->bo);
655 free(psampler);
656 }
657
658 #if V3D_VERSION >= 40
659 static uint32_t
660 translate_swizzle(unsigned char pipe_swizzle)
661 {
662 switch (pipe_swizzle) {
663 case PIPE_SWIZZLE_0:
664 return 0;
665 case PIPE_SWIZZLE_1:
666 return 1;
667 case PIPE_SWIZZLE_X:
668 case PIPE_SWIZZLE_Y:
669 case PIPE_SWIZZLE_Z:
670 case PIPE_SWIZZLE_W:
671 return 2 + pipe_swizzle;
672 default:
673 unreachable("unknown swizzle");
674 }
675 }
676 #endif
677
678 static struct pipe_sampler_view *
679 v3d_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
680 const struct pipe_sampler_view *cso)
681 {
682 struct v3d_context *v3d = v3d_context(pctx);
683 struct v3d_screen *screen = v3d->screen;
684 struct v3d_sampler_view *so = CALLOC_STRUCT(v3d_sampler_view);
685 struct v3d_resource *rsc = v3d_resource(prsc);
686
687 if (!so)
688 return NULL;
689
690 so->base = *cso;
691
692 pipe_reference(NULL, &prsc->reference);
693
694 /* Compute the sampler view's swizzle up front. This will be plugged
695 * into either the sampler (for 16-bit returns) or the shader's
696 * texture key (for 32)
697 */
698 uint8_t view_swizzle[4] = {
699 cso->swizzle_r,
700 cso->swizzle_g,
701 cso->swizzle_b,
702 cso->swizzle_a
703 };
704 const uint8_t *fmt_swizzle =
705 v3d_get_format_swizzle(&screen->devinfo, so->base.format);
706 util_format_compose_swizzles(fmt_swizzle, view_swizzle, so->swizzle);
707
708 so->base.texture = prsc;
709 so->base.reference.count = 1;
710 so->base.context = pctx;
711
712 int msaa_scale = prsc->nr_samples > 1 ? 2 : 1;
713
714 #if V3D_VERSION >= 40
715 so->bo = v3d_bo_alloc(v3d->screen,
716 cl_packet_length(TEXTURE_SHADER_STATE), "sampler");
717 void *map = v3d_bo_map(so->bo);
718
719 v3dx_pack(map, TEXTURE_SHADER_STATE, tex) {
720 #else /* V3D_VERSION < 40 */
721 STATIC_ASSERT(sizeof(so->texture_shader_state) >=
722 cl_packet_length(TEXTURE_SHADER_STATE));
723 v3dx_pack(&so->texture_shader_state, TEXTURE_SHADER_STATE, tex) {
724 #endif
725
726 tex.image_width = prsc->width0 * msaa_scale;
727 tex.image_height = prsc->height0 * msaa_scale;
728
729 #if V3D_VERSION >= 40
730 /* On 4.x, the height of a 1D texture is redefined to be the
731 * upper 14 bits of the width (which is only usable with txf).
732 */
733 if (prsc->target == PIPE_TEXTURE_1D ||
734 prsc->target == PIPE_TEXTURE_1D_ARRAY) {
735 tex.image_height = tex.image_width >> 14;
736 }
737 #endif
738
739 if (prsc->target == PIPE_TEXTURE_3D) {
740 tex.image_depth = prsc->depth0;
741 } else {
742 tex.image_depth = (cso->u.tex.last_layer -
743 cso->u.tex.first_layer) + 1;
744 }
745
746 tex.srgb = util_format_is_srgb(cso->format);
747
748 tex.base_level = cso->u.tex.first_level;
749 #if V3D_VERSION >= 40
750 tex.max_level = cso->u.tex.last_level;
751 /* Note that we don't have a job to reference the texture's sBO
752 * at state create time, so any time this sampler view is used
753 * we need to add the texture to the job.
754 */
755 tex.texture_base_pointer = cl_address(NULL,
756 rsc->bo->offset +
757 rsc->slices[0].offset),
758
759 tex.swizzle_r = translate_swizzle(so->swizzle[0]);
760 tex.swizzle_g = translate_swizzle(so->swizzle[1]);
761 tex.swizzle_b = translate_swizzle(so->swizzle[2]);
762 tex.swizzle_a = translate_swizzle(so->swizzle[3]);
763 #endif
764 tex.array_stride_64_byte_aligned = rsc->cube_map_stride / 64;
765
766 if (prsc->nr_samples > 1 && V3D_VERSION < 40) {
767 /* Using texture views to reinterpret formats on our
768 * MSAA textures won't work, because we don't lay out
769 * the bits in memory as it's expected -- for example,
770 * RGBA8 and RGB10_A2 are compatible in the
771 * ARB_texture_view spec, but in HW we lay them out as
772 * 32bpp RGBA8 and 64bpp RGBA16F. Just assert for now
773 * to catch failures.
774 *
775 * We explicitly allow remapping S8Z24 to RGBA8888 for
776 * v3d_blit.c's stencil blits.
777 */
778 assert((util_format_linear(cso->format) ==
779 util_format_linear(prsc->format)) ||
780 (prsc->format == PIPE_FORMAT_S8_UINT_Z24_UNORM &&
781 cso->format == PIPE_FORMAT_R8G8B8A8_UNORM));
782 uint32_t output_image_format =
783 v3d_get_rt_format(&screen->devinfo, cso->format);
784 uint32_t internal_type;
785 uint32_t internal_bpp;
786 v3d_get_internal_type_bpp_for_output_format(&screen->devinfo,
787 output_image_format,
788 &internal_type,
789 &internal_bpp);
790
791 switch (internal_type) {
792 case V3D_INTERNAL_TYPE_8:
793 tex.texture_type = TEXTURE_DATA_FORMAT_RGBA8;
794 break;
795 case V3D_INTERNAL_TYPE_16F:
796 tex.texture_type = TEXTURE_DATA_FORMAT_RGBA16F;
797 break;
798 default:
799 unreachable("Bad MSAA texture type");
800 }
801
802 /* sRGB was stored in the tile buffer as linear and
803 * would have been encoded to sRGB on resolved tile
804 * buffer store. Note that this means we would need
805 * shader code if we wanted to read an MSAA sRGB
806 * texture without sRGB decode.
807 */
808 tex.srgb = false;
809 } else {
810 tex.texture_type = v3d_get_tex_format(&screen->devinfo,
811 cso->format);
812 }
813
814 /* Since other platform devices may produce UIF images even
815 * when they're not big enough for V3D to assume they're UIF,
816 * we force images with level 0 as UIF to be always treated
817 * that way.
818 */
819 tex.level_0_is_strictly_uif = (rsc->slices[0].tiling ==
820 VC5_TILING_UIF_XOR ||
821 rsc->slices[0].tiling ==
822 VC5_TILING_UIF_NO_XOR);
823 tex.level_0_xor_enable = (rsc->slices[0].tiling ==
824 VC5_TILING_UIF_XOR);
825
826 if (tex.level_0_is_strictly_uif)
827 tex.level_0_ub_pad = rsc->slices[0].ub_pad;
828
829 #if V3D_VERSION >= 40
830 if (tex.uif_xor_disable ||
831 tex.level_0_is_strictly_uif) {
832 tex.extended = true;
833 }
834 #endif /* V3D_VERSION >= 40 */
835 };
836
837 return &so->base;
838 }
839
840 static void
841 v3d_sampler_view_destroy(struct pipe_context *pctx,
842 struct pipe_sampler_view *psview)
843 {
844 struct v3d_sampler_view *sview = v3d_sampler_view(psview);
845
846 v3d_bo_unreference(&sview->bo);
847 pipe_resource_reference(&psview->texture, NULL);
848 free(psview);
849 }
850
851 static void
852 v3d_set_sampler_views(struct pipe_context *pctx,
853 enum pipe_shader_type shader,
854 unsigned start, unsigned nr,
855 struct pipe_sampler_view **views)
856 {
857 struct v3d_context *v3d = v3d_context(pctx);
858 struct v3d_texture_stateobj *stage_tex = v3d_get_stage_tex(v3d, shader);
859 unsigned i;
860 unsigned new_nr = 0;
861
862 assert(start == 0);
863
864 for (i = 0; i < nr; i++) {
865 if (views[i])
866 new_nr = i + 1;
867 pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
868 }
869
870 for (; i < stage_tex->num_textures; i++) {
871 pipe_sampler_view_reference(&stage_tex->textures[i], NULL);
872 }
873
874 stage_tex->num_textures = new_nr;
875 }
876
877 static struct pipe_stream_output_target *
878 v3d_create_stream_output_target(struct pipe_context *pctx,
879 struct pipe_resource *prsc,
880 unsigned buffer_offset,
881 unsigned buffer_size)
882 {
883 struct pipe_stream_output_target *target;
884
885 target = CALLOC_STRUCT(pipe_stream_output_target);
886 if (!target)
887 return NULL;
888
889 pipe_reference_init(&target->reference, 1);
890 pipe_resource_reference(&target->buffer, prsc);
891
892 target->context = pctx;
893 target->buffer_offset = buffer_offset;
894 target->buffer_size = buffer_size;
895
896 return target;
897 }
898
899 static void
900 v3d_stream_output_target_destroy(struct pipe_context *pctx,
901 struct pipe_stream_output_target *target)
902 {
903 pipe_resource_reference(&target->buffer, NULL);
904 free(target);
905 }
906
907 static void
908 v3d_set_stream_output_targets(struct pipe_context *pctx,
909 unsigned num_targets,
910 struct pipe_stream_output_target **targets,
911 const unsigned *offsets)
912 {
913 struct v3d_context *ctx = v3d_context(pctx);
914 struct v3d_streamout_stateobj *so = &ctx->streamout;
915 unsigned i;
916
917 assert(num_targets <= ARRAY_SIZE(so->targets));
918
919 for (i = 0; i < num_targets; i++) {
920 if (offsets[i] != -1)
921 so->offsets[i] = offsets[i];
922
923 pipe_so_target_reference(&so->targets[i], targets[i]);
924 }
925
926 for (; i < so->num_targets; i++)
927 pipe_so_target_reference(&so->targets[i], NULL);
928
929 so->num_targets = num_targets;
930
931 ctx->dirty |= VC5_DIRTY_STREAMOUT;
932 }
933
934 void
935 v3dX(state_init)(struct pipe_context *pctx)
936 {
937 pctx->set_blend_color = v3d_set_blend_color;
938 pctx->set_stencil_ref = v3d_set_stencil_ref;
939 pctx->set_clip_state = v3d_set_clip_state;
940 pctx->set_sample_mask = v3d_set_sample_mask;
941 pctx->set_constant_buffer = v3d_set_constant_buffer;
942 pctx->set_framebuffer_state = v3d_set_framebuffer_state;
943 pctx->set_polygon_stipple = v3d_set_polygon_stipple;
944 pctx->set_scissor_states = v3d_set_scissor_states;
945 pctx->set_viewport_states = v3d_set_viewport_states;
946
947 pctx->set_vertex_buffers = v3d_set_vertex_buffers;
948
949 pctx->create_blend_state = v3d_create_blend_state;
950 pctx->bind_blend_state = v3d_blend_state_bind;
951 pctx->delete_blend_state = v3d_generic_cso_state_delete;
952
953 pctx->create_rasterizer_state = v3d_create_rasterizer_state;
954 pctx->bind_rasterizer_state = v3d_rasterizer_state_bind;
955 pctx->delete_rasterizer_state = v3d_generic_cso_state_delete;
956
957 pctx->create_depth_stencil_alpha_state = v3d_create_depth_stencil_alpha_state;
958 pctx->bind_depth_stencil_alpha_state = v3d_zsa_state_bind;
959 pctx->delete_depth_stencil_alpha_state = v3d_generic_cso_state_delete;
960
961 pctx->create_vertex_elements_state = v3d_vertex_state_create;
962 pctx->delete_vertex_elements_state = v3d_generic_cso_state_delete;
963 pctx->bind_vertex_elements_state = v3d_vertex_state_bind;
964
965 pctx->create_sampler_state = v3d_create_sampler_state;
966 pctx->delete_sampler_state = v3d_sampler_state_delete;
967 pctx->bind_sampler_states = v3d_sampler_states_bind;
968
969 pctx->create_sampler_view = v3d_create_sampler_view;
970 pctx->sampler_view_destroy = v3d_sampler_view_destroy;
971 pctx->set_sampler_views = v3d_set_sampler_views;
972
973 pctx->create_stream_output_target = v3d_create_stream_output_target;
974 pctx->stream_output_target_destroy = v3d_stream_output_target_destroy;
975 pctx->set_stream_output_targets = v3d_set_stream_output_targets;
976 }