2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "pipe/p_state.h"
26 #include "util/u_format.h"
27 #include "util/u_framebuffer.h"
28 #include "util/u_inlines.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/u_half.h"
32 #include "util/u_helpers.h"
34 #include "v3d_context.h"
35 #include "v3d_tiling.h"
36 #include "broadcom/common/v3d_macros.h"
37 #include "broadcom/cle/v3dx_pack.h"
40 v3d_generic_cso_state_create(const void *src
, uint32_t size
)
42 void *dst
= calloc(1, size
);
45 memcpy(dst
, src
, size
);
50 v3d_generic_cso_state_delete(struct pipe_context
*pctx
, void *hwcso
)
56 v3d_set_blend_color(struct pipe_context
*pctx
,
57 const struct pipe_blend_color
*blend_color
)
59 struct v3d_context
*v3d
= v3d_context(pctx
);
60 v3d
->blend_color
.f
= *blend_color
;
61 for (int i
= 0; i
< 4; i
++) {
62 v3d
->blend_color
.hf
[i
] =
63 util_float_to_half(blend_color
->color
[i
]);
65 v3d
->dirty
|= VC5_DIRTY_BLEND_COLOR
;
69 v3d_set_stencil_ref(struct pipe_context
*pctx
,
70 const struct pipe_stencil_ref
*stencil_ref
)
72 struct v3d_context
*v3d
= v3d_context(pctx
);
73 v3d
->stencil_ref
= *stencil_ref
;
74 v3d
->dirty
|= VC5_DIRTY_STENCIL_REF
;
78 v3d_set_clip_state(struct pipe_context
*pctx
,
79 const struct pipe_clip_state
*clip
)
81 struct v3d_context
*v3d
= v3d_context(pctx
);
83 v3d
->dirty
|= VC5_DIRTY_CLIP
;
87 v3d_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
89 struct v3d_context
*v3d
= v3d_context(pctx
);
90 v3d
->sample_mask
= sample_mask
& ((1 << VC5_MAX_SAMPLES
) - 1);
91 v3d
->dirty
|= VC5_DIRTY_SAMPLE_STATE
;
95 float_to_187_half(float f
)
101 v3d_create_rasterizer_state(struct pipe_context
*pctx
,
102 const struct pipe_rasterizer_state
*cso
)
104 struct v3d_rasterizer_state
*so
;
106 so
= CALLOC_STRUCT(v3d_rasterizer_state
);
112 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
115 so
->point_size
= MAX2(cso
->point_size
, .125f
);
117 if (cso
->offset_tri
) {
118 so
->offset_units
= float_to_187_half(cso
->offset_units
);
119 so
->z16_offset_units
= float_to_187_half(cso
->offset_units
* 256.0);
120 so
->offset_factor
= float_to_187_half(cso
->offset_scale
);
126 /* Blend state is baked into shaders. */
128 v3d_create_blend_state(struct pipe_context
*pctx
,
129 const struct pipe_blend_state
*cso
)
131 return v3d_generic_cso_state_create(cso
, sizeof(*cso
));
135 translate_stencil_op(enum pipe_stencil_op op
)
138 case PIPE_STENCIL_OP_KEEP
: return V3D_STENCIL_OP_KEEP
;
139 case PIPE_STENCIL_OP_ZERO
: return V3D_STENCIL_OP_ZERO
;
140 case PIPE_STENCIL_OP_REPLACE
: return V3D_STENCIL_OP_REPLACE
;
141 case PIPE_STENCIL_OP_INCR
: return V3D_STENCIL_OP_INCR
;
142 case PIPE_STENCIL_OP_DECR
: return V3D_STENCIL_OP_DECR
;
143 case PIPE_STENCIL_OP_INCR_WRAP
: return V3D_STENCIL_OP_INCWRAP
;
144 case PIPE_STENCIL_OP_DECR_WRAP
: return V3D_STENCIL_OP_DECWRAP
;
145 case PIPE_STENCIL_OP_INVERT
: return V3D_STENCIL_OP_INVERT
;
147 unreachable("bad stencil op");
151 v3d_create_depth_stencil_alpha_state(struct pipe_context
*pctx
,
152 const struct pipe_depth_stencil_alpha_state
*cso
)
154 struct v3d_depth_stencil_alpha_state
*so
;
156 so
= CALLOC_STRUCT(v3d_depth_stencil_alpha_state
);
162 if (cso
->depth
.enabled
) {
163 switch (cso
->depth
.func
) {
165 case PIPE_FUNC_LEQUAL
:
166 so
->ez_state
= VC5_EZ_LT_LE
;
168 case PIPE_FUNC_GREATER
:
169 case PIPE_FUNC_GEQUAL
:
170 so
->ez_state
= VC5_EZ_GT_GE
;
172 case PIPE_FUNC_NEVER
:
173 case PIPE_FUNC_EQUAL
:
174 so
->ez_state
= VC5_EZ_UNDECIDED
;
177 so
->ez_state
= VC5_EZ_DISABLED
;
181 /* If stencil is enabled and it's not a no-op, then it would
184 if (cso
->stencil
[0].enabled
&&
185 (cso
->stencil
[0].zfail_op
!= PIPE_STENCIL_OP_KEEP
||
186 cso
->stencil
[0].func
!= PIPE_FUNC_ALWAYS
||
187 (cso
->stencil
[1].enabled
&&
188 (cso
->stencil
[1].zfail_op
!= PIPE_STENCIL_OP_KEEP
&&
189 cso
->stencil
[1].func
!= PIPE_FUNC_ALWAYS
)))) {
190 so
->ez_state
= VC5_EZ_DISABLED
;
194 const struct pipe_stencil_state
*front
= &cso
->stencil
[0];
195 const struct pipe_stencil_state
*back
= &cso
->stencil
[1];
197 if (front
->enabled
) {
198 STATIC_ASSERT(sizeof(so
->stencil_front
) >=
199 cl_packet_length(STENCIL_CONFIG
));
200 v3dx_pack(&so
->stencil_front
, STENCIL_CONFIG
, config
) {
201 config
.front_config
= true;
202 /* If !back->enabled, then the front values should be
203 * used for both front and back-facing primitives.
205 config
.back_config
= !back
->enabled
;
207 config
.stencil_write_mask
= front
->writemask
;
208 config
.stencil_test_mask
= front
->valuemask
;
210 config
.stencil_test_function
= front
->func
;
211 config
.stencil_pass_op
=
212 translate_stencil_op(front
->zpass_op
);
213 config
.depth_test_fail_op
=
214 translate_stencil_op(front
->zfail_op
);
215 config
.stencil_test_fail_op
=
216 translate_stencil_op(front
->fail_op
);
220 STATIC_ASSERT(sizeof(so
->stencil_back
) >=
221 cl_packet_length(STENCIL_CONFIG
));
222 v3dx_pack(&so
->stencil_back
, STENCIL_CONFIG
, config
) {
223 config
.front_config
= false;
224 config
.back_config
= true;
226 config
.stencil_write_mask
= back
->writemask
;
227 config
.stencil_test_mask
= back
->valuemask
;
229 config
.stencil_test_function
= back
->func
;
230 config
.stencil_pass_op
=
231 translate_stencil_op(back
->zpass_op
);
232 config
.depth_test_fail_op
=
233 translate_stencil_op(back
->zfail_op
);
234 config
.stencil_test_fail_op
=
235 translate_stencil_op(back
->fail_op
);
243 v3d_set_polygon_stipple(struct pipe_context
*pctx
,
244 const struct pipe_poly_stipple
*stipple
)
246 struct v3d_context
*v3d
= v3d_context(pctx
);
247 v3d
->stipple
= *stipple
;
248 v3d
->dirty
|= VC5_DIRTY_STIPPLE
;
252 v3d_set_scissor_states(struct pipe_context
*pctx
,
254 unsigned num_scissors
,
255 const struct pipe_scissor_state
*scissor
)
257 struct v3d_context
*v3d
= v3d_context(pctx
);
259 v3d
->scissor
= *scissor
;
260 v3d
->dirty
|= VC5_DIRTY_SCISSOR
;
264 v3d_set_viewport_states(struct pipe_context
*pctx
,
266 unsigned num_viewports
,
267 const struct pipe_viewport_state
*viewport
)
269 struct v3d_context
*v3d
= v3d_context(pctx
);
270 v3d
->viewport
= *viewport
;
271 v3d
->dirty
|= VC5_DIRTY_VIEWPORT
;
275 v3d_set_vertex_buffers(struct pipe_context
*pctx
,
276 unsigned start_slot
, unsigned count
,
277 const struct pipe_vertex_buffer
*vb
)
279 struct v3d_context
*v3d
= v3d_context(pctx
);
280 struct v3d_vertexbuf_stateobj
*so
= &v3d
->vertexbuf
;
282 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
,
284 so
->count
= util_last_bit(so
->enabled_mask
);
286 v3d
->dirty
|= VC5_DIRTY_VTXBUF
;
290 v3d_blend_state_bind(struct pipe_context
*pctx
, void *hwcso
)
292 struct v3d_context
*v3d
= v3d_context(pctx
);
294 v3d
->dirty
|= VC5_DIRTY_BLEND
;
298 v3d_rasterizer_state_bind(struct pipe_context
*pctx
, void *hwcso
)
300 struct v3d_context
*v3d
= v3d_context(pctx
);
301 v3d
->rasterizer
= hwcso
;
302 v3d
->dirty
|= VC5_DIRTY_RASTERIZER
;
306 v3d_zsa_state_bind(struct pipe_context
*pctx
, void *hwcso
)
308 struct v3d_context
*v3d
= v3d_context(pctx
);
310 v3d
->dirty
|= VC5_DIRTY_ZSA
;
314 v3d_vertex_state_create(struct pipe_context
*pctx
, unsigned num_elements
,
315 const struct pipe_vertex_element
*elements
)
317 struct v3d_context
*v3d
= v3d_context(pctx
);
318 struct v3d_vertex_stateobj
*so
= CALLOC_STRUCT(v3d_vertex_stateobj
);
323 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
324 so
->num_elements
= num_elements
;
326 for (int i
= 0; i
< so
->num_elements
; i
++) {
327 const struct pipe_vertex_element
*elem
= &elements
[i
];
328 const struct util_format_description
*desc
=
329 util_format_description(elem
->src_format
);
330 uint32_t r_size
= desc
->channel
[0].size
;
332 const uint32_t size
=
333 cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD
);
335 v3dx_pack(&so
->attrs
[i
* size
],
336 GL_SHADER_STATE_ATTRIBUTE_RECORD
, attr
) {
337 /* vec_size == 0 means 4 */
338 attr
.vec_size
= desc
->nr_channels
& 3;
339 attr
.signed_int_type
= (desc
->channel
[0].type
==
340 UTIL_FORMAT_TYPE_SIGNED
);
342 attr
.normalized_int_type
= desc
->channel
[0].normalized
;
343 attr
.read_as_int_uint
= desc
->channel
[0].pure_integer
;
344 attr
.instance_divisor
= MIN2(elem
->instance_divisor
,
347 switch (desc
->channel
[0].type
) {
348 case UTIL_FORMAT_TYPE_FLOAT
:
350 attr
.type
= ATTRIBUTE_FLOAT
;
352 assert(r_size
== 16);
353 attr
.type
= ATTRIBUTE_HALF_FLOAT
;
357 case UTIL_FORMAT_TYPE_SIGNED
:
358 case UTIL_FORMAT_TYPE_UNSIGNED
:
361 attr
.type
= ATTRIBUTE_INT
;
364 attr
.type
= ATTRIBUTE_SHORT
;
367 attr
.type
= ATTRIBUTE_INT2_10_10_10
;
370 attr
.type
= ATTRIBUTE_BYTE
;
374 "format %s unsupported\n",
376 attr
.type
= ATTRIBUTE_BYTE
;
383 "format %s unsupported\n",
390 /* Set up the default attribute values in case any of the vertex
393 so
->default_attribute_values
= v3d_bo_alloc(v3d
->screen
,
396 "default attributes");
397 uint32_t *attrs
= v3d_bo_map(so
->default_attribute_values
);
398 for (int i
= 0; i
< VC5_MAX_ATTRIBUTES
; i
++) {
399 attrs
[i
* 4 + 0] = 0;
400 attrs
[i
* 4 + 1] = 0;
401 attrs
[i
* 4 + 2] = 0;
402 if (i
< so
->num_elements
&&
403 util_format_is_pure_integer(so
->pipe
[i
].src_format
)) {
404 attrs
[i
* 4 + 3] = 1;
406 attrs
[i
* 4 + 3] = fui(1.0);
414 v3d_vertex_state_bind(struct pipe_context
*pctx
, void *hwcso
)
416 struct v3d_context
*v3d
= v3d_context(pctx
);
418 v3d
->dirty
|= VC5_DIRTY_VTXSTATE
;
422 v3d_set_constant_buffer(struct pipe_context
*pctx
, uint shader
, uint index
,
423 const struct pipe_constant_buffer
*cb
)
425 struct v3d_context
*v3d
= v3d_context(pctx
);
426 struct v3d_constbuf_stateobj
*so
= &v3d
->constbuf
[shader
];
428 util_copy_constant_buffer(&so
->cb
[index
], cb
);
430 /* Note that the state tracker can unbind constant buffers by
434 so
->enabled_mask
&= ~(1 << index
);
435 so
->dirty_mask
&= ~(1 << index
);
439 so
->enabled_mask
|= 1 << index
;
440 so
->dirty_mask
|= 1 << index
;
441 v3d
->dirty
|= VC5_DIRTY_CONSTBUF
;
445 v3d_set_framebuffer_state(struct pipe_context
*pctx
,
446 const struct pipe_framebuffer_state
*framebuffer
)
448 struct v3d_context
*v3d
= v3d_context(pctx
);
449 struct pipe_framebuffer_state
*cso
= &v3d
->framebuffer
;
453 util_copy_framebuffer_state(cso
, framebuffer
);
455 v3d
->swap_color_rb
= 0;
456 v3d
->blend_dst_alpha_one
= 0;
457 for (int i
= 0; i
< v3d
->framebuffer
.nr_cbufs
; i
++) {
458 struct pipe_surface
*cbuf
= v3d
->framebuffer
.cbufs
[i
];
462 const struct util_format_description
*desc
=
463 util_format_description(cbuf
->format
);
465 /* For BGRA8 formats (DRI window system default format), we
466 * need to swap R and B, since the HW's format is RGBA8.
468 if (desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
469 cbuf
->format
!= PIPE_FORMAT_B5G6R5_UNORM
) {
470 v3d
->swap_color_rb
|= 1 << i
;
473 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
474 v3d
->blend_dst_alpha_one
|= 1 << i
;
477 v3d
->dirty
|= VC5_DIRTY_FRAMEBUFFER
;
480 static struct v3d_texture_stateobj
*
481 v3d_get_stage_tex(struct v3d_context
*v3d
, enum pipe_shader_type shader
)
484 case PIPE_SHADER_FRAGMENT
:
485 v3d
->dirty
|= VC5_DIRTY_FRAGTEX
;
486 return &v3d
->fragtex
;
488 case PIPE_SHADER_VERTEX
:
489 v3d
->dirty
|= VC5_DIRTY_VERTTEX
;
490 return &v3d
->verttex
;
493 fprintf(stderr
, "Unknown shader target %d\n", shader
);
498 static uint32_t translate_wrap(uint32_t pipe_wrap
, bool using_nearest
)
501 case PIPE_TEX_WRAP_REPEAT
:
503 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
505 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
507 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
509 case PIPE_TEX_WRAP_CLAMP
:
510 return (using_nearest
? 1 : 3);
512 unreachable("Unknown wrap mode");
518 v3d_create_sampler_state(struct pipe_context
*pctx
,
519 const struct pipe_sampler_state
*cso
)
521 MAYBE_UNUSED
struct v3d_context
*v3d
= v3d_context(pctx
);
522 struct v3d_sampler_state
*so
= CALLOC_STRUCT(v3d_sampler_state
);
527 memcpy(so
, cso
, sizeof(*cso
));
529 bool either_nearest
=
530 (cso
->mag_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
||
531 cso
->min_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
);
533 #if V3D_VERSION >= 40
534 so
->bo
= v3d_bo_alloc(v3d
->screen
, cl_packet_length(SAMPLER_STATE
),
536 void *map
= v3d_bo_map(so
->bo
);
538 v3dx_pack(map
, SAMPLER_STATE
, sampler
) {
539 sampler
.wrap_i_border
= false;
541 sampler
.wrap_s
= translate_wrap(cso
->wrap_s
, either_nearest
);
542 sampler
.wrap_t
= translate_wrap(cso
->wrap_t
, either_nearest
);
543 sampler
.wrap_r
= translate_wrap(cso
->wrap_r
, either_nearest
);
545 sampler
.fixed_bias
= cso
->lod_bias
;
546 sampler
.depth_compare_function
= cso
->compare_func
;
548 sampler
.min_filter_nearest
=
549 cso
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
;
550 sampler
.mag_filter_nearest
=
551 cso
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
;
552 sampler
.mip_filter_nearest
=
553 cso
->min_mip_filter
!= PIPE_TEX_MIPFILTER_LINEAR
;
555 sampler
.min_level_of_detail
= MIN2(MAX2(0, cso
->min_lod
),
557 sampler
.max_level_of_detail
= MIN2(cso
->max_lod
, 15);
559 /* If we're not doing inter-miplevel filtering, we need to
560 * clamp the LOD so that we only sample from baselevel.
561 * However, we need to still allow the calculated LOD to be
562 * fractionally over the baselevel, so that the HW can decide
563 * between the min and mag filters.
565 if (cso
->min_mip_filter
== PIPE_TEX_MIPFILTER_NONE
) {
566 sampler
.min_level_of_detail
=
567 MIN2(sampler
.min_level_of_detail
, 1.0 / 256.0);
568 sampler
.max_level_of_detail
=
569 MIN2(sampler
.max_level_of_detail
, 1.0 / 256.0);
572 if (cso
->max_anisotropy
) {
573 sampler
.anisotropy_enable
= true;
575 if (cso
->max_anisotropy
> 8)
576 sampler
.maximum_anisotropy
= 3;
577 else if (cso
->max_anisotropy
> 4)
578 sampler
.maximum_anisotropy
= 2;
579 else if (cso
->max_anisotropy
> 2)
580 sampler
.maximum_anisotropy
= 1;
583 sampler
.border_colour_mode
= V3D_BORDER_COLOUR_FOLLOWS
;
584 /* XXX: The border colour field is in the TMU blending format
585 * (32, f16, or i16), and we need to customize it based on
588 * XXX: for compat alpha formats, we need the alpha field to
589 * be in the red channel.
591 sampler
.border_colour_red
=
592 util_float_to_half(cso
->border_color
.f
[0]);
593 sampler
.border_colour_green
=
594 util_float_to_half(cso
->border_color
.f
[1]);
595 sampler
.border_colour_blue
=
596 util_float_to_half(cso
->border_color
.f
[2]);
597 sampler
.border_colour_alpha
=
598 util_float_to_half(cso
->border_color
.f
[3]);
601 #else /* V3D_VERSION < 40 */
602 v3dx_pack(&so
->p0
, TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1
, p0
) {
603 p0
.s_wrap_mode
= translate_wrap(cso
->wrap_s
, either_nearest
);
604 p0
.t_wrap_mode
= translate_wrap(cso
->wrap_t
, either_nearest
);
605 p0
.r_wrap_mode
= translate_wrap(cso
->wrap_r
, either_nearest
);
608 v3dx_pack(&so
->texture_shader_state
, TEXTURE_SHADER_STATE
, tex
) {
609 tex
.depth_compare_function
= cso
->compare_func
;
610 tex
.fixed_bias
= cso
->lod_bias
;
612 #endif /* V3D_VERSION < 40 */
617 v3d_sampler_states_bind(struct pipe_context
*pctx
,
618 enum pipe_shader_type shader
, unsigned start
,
619 unsigned nr
, void **hwcso
)
621 struct v3d_context
*v3d
= v3d_context(pctx
);
622 struct v3d_texture_stateobj
*stage_tex
= v3d_get_stage_tex(v3d
, shader
);
628 for (i
= 0; i
< nr
; i
++) {
631 stage_tex
->samplers
[i
] = hwcso
[i
];
634 for (; i
< stage_tex
->num_samplers
; i
++) {
635 stage_tex
->samplers
[i
] = NULL
;
638 stage_tex
->num_samplers
= new_nr
;
642 v3d_sampler_state_delete(struct pipe_context
*pctx
,
645 struct pipe_sampler_state
*psampler
= hwcso
;
646 struct v3d_sampler_state
*sampler
= v3d_sampler_state(psampler
);
648 v3d_bo_unreference(&sampler
->bo
);
652 #if V3D_VERSION >= 40
654 translate_swizzle(unsigned char pipe_swizzle
)
656 switch (pipe_swizzle
) {
665 return 2 + pipe_swizzle
;
667 unreachable("unknown swizzle");
672 static struct pipe_sampler_view
*
673 v3d_create_sampler_view(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
674 const struct pipe_sampler_view
*cso
)
676 struct v3d_context
*v3d
= v3d_context(pctx
);
677 struct v3d_screen
*screen
= v3d
->screen
;
678 struct v3d_sampler_view
*so
= CALLOC_STRUCT(v3d_sampler_view
);
679 struct v3d_resource
*rsc
= v3d_resource(prsc
);
686 pipe_reference(NULL
, &prsc
->reference
);
688 /* Compute the sampler view's swizzle up front. This will be plugged
689 * into either the sampler (for 16-bit returns) or the shader's
690 * texture key (for 32)
692 uint8_t view_swizzle
[4] = {
698 const uint8_t *fmt_swizzle
=
699 v3d_get_format_swizzle(&screen
->devinfo
, so
->base
.format
);
700 util_format_compose_swizzles(fmt_swizzle
, view_swizzle
, so
->swizzle
);
702 so
->base
.texture
= prsc
;
703 so
->base
.reference
.count
= 1;
704 so
->base
.context
= pctx
;
706 int msaa_scale
= prsc
->nr_samples
> 1 ? 2 : 1;
708 #if V3D_VERSION >= 40
709 so
->bo
= v3d_bo_alloc(v3d
->screen
,
710 cl_packet_length(TEXTURE_SHADER_STATE
), "sampler");
711 void *map
= v3d_bo_map(so
->bo
);
713 v3dx_pack(map
, TEXTURE_SHADER_STATE
, tex
) {
714 #else /* V3D_VERSION < 40 */
715 STATIC_ASSERT(sizeof(so
->texture_shader_state
) >=
716 cl_packet_length(TEXTURE_SHADER_STATE
));
717 v3dx_pack(&so
->texture_shader_state
, TEXTURE_SHADER_STATE
, tex
) {
720 tex
.image_width
= prsc
->width0
* msaa_scale
;
721 tex
.image_height
= prsc
->height0
* msaa_scale
;
723 #if V3D_VERSION >= 40
724 /* On 4.x, the height of a 1D texture is redefined to be the
725 * upper 14 bits of the width (which is only usable with txf).
727 if (prsc
->target
== PIPE_TEXTURE_1D
||
728 prsc
->target
== PIPE_TEXTURE_1D_ARRAY
) {
729 tex
.image_height
= tex
.image_width
>> 14;
733 if (prsc
->target
== PIPE_TEXTURE_3D
) {
734 tex
.image_depth
= prsc
->depth0
;
736 tex
.image_depth
= (cso
->u
.tex
.last_layer
-
737 cso
->u
.tex
.first_layer
) + 1;
740 tex
.srgb
= util_format_is_srgb(cso
->format
);
742 tex
.base_level
= cso
->u
.tex
.first_level
;
743 #if V3D_VERSION >= 40
744 tex
.max_level
= cso
->u
.tex
.last_level
;
745 /* Note that we don't have a job to reference the texture's sBO
746 * at state create time, so any time this sampler view is used
747 * we need to add the texture to the job.
749 tex
.texture_base_pointer
= cl_address(NULL
,
751 rsc
->slices
[0].offset
),
753 tex
.swizzle_r
= translate_swizzle(so
->swizzle
[0]);
754 tex
.swizzle_g
= translate_swizzle(so
->swizzle
[1]);
755 tex
.swizzle_b
= translate_swizzle(so
->swizzle
[2]);
756 tex
.swizzle_a
= translate_swizzle(so
->swizzle
[3]);
758 tex
.array_stride_64_byte_aligned
= rsc
->cube_map_stride
/ 64;
760 if (prsc
->nr_samples
> 1 && V3D_VERSION
< 40) {
761 /* Using texture views to reinterpret formats on our
762 * MSAA textures won't work, because we don't lay out
763 * the bits in memory as it's expected -- for example,
764 * RGBA8 and RGB10_A2 are compatible in the
765 * ARB_texture_view spec, but in HW we lay them out as
766 * 32bpp RGBA8 and 64bpp RGBA16F. Just assert for now
769 * We explicitly allow remapping S8Z24 to RGBA8888 for
770 * v3d_blit.c's stencil blits.
772 assert((util_format_linear(cso
->format
) ==
773 util_format_linear(prsc
->format
)) ||
774 (prsc
->format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
&&
775 cso
->format
== PIPE_FORMAT_R8G8B8A8_UNORM
));
776 uint32_t output_image_format
=
777 v3d_get_rt_format(&screen
->devinfo
, cso
->format
);
778 uint32_t internal_type
;
779 uint32_t internal_bpp
;
780 v3d_get_internal_type_bpp_for_output_format(&screen
->devinfo
,
785 switch (internal_type
) {
786 case V3D_INTERNAL_TYPE_8
:
787 tex
.texture_type
= TEXTURE_DATA_FORMAT_RGBA8
;
789 case V3D_INTERNAL_TYPE_16F
:
790 tex
.texture_type
= TEXTURE_DATA_FORMAT_RGBA16F
;
793 unreachable("Bad MSAA texture type");
796 /* sRGB was stored in the tile buffer as linear and
797 * would have been encoded to sRGB on resolved tile
798 * buffer store. Note that this means we would need
799 * shader code if we wanted to read an MSAA sRGB
800 * texture without sRGB decode.
804 tex
.texture_type
= v3d_get_tex_format(&screen
->devinfo
,
808 /* Since other platform devices may produce UIF images even
809 * when they're not big enough for V3D to assume they're UIF,
810 * we force images with level 0 as UIF to be always treated
813 tex
.level_0_is_strictly_uif
= (rsc
->slices
[0].tiling
==
814 VC5_TILING_UIF_XOR
||
815 rsc
->slices
[0].tiling
==
816 VC5_TILING_UIF_NO_XOR
);
817 tex
.level_0_xor_enable
= (rsc
->slices
[0].tiling
==
820 if (tex
.level_0_is_strictly_uif
)
821 tex
.level_0_ub_pad
= rsc
->slices
[0].ub_pad
;
823 #if V3D_VERSION >= 40
824 if (tex
.uif_xor_disable
||
825 tex
.level_0_is_strictly_uif
) {
828 #endif /* V3D_VERSION >= 40 */
835 v3d_sampler_view_destroy(struct pipe_context
*pctx
,
836 struct pipe_sampler_view
*psview
)
838 struct v3d_sampler_view
*sview
= v3d_sampler_view(psview
);
840 v3d_bo_unreference(&sview
->bo
);
841 pipe_resource_reference(&psview
->texture
, NULL
);
846 v3d_set_sampler_views(struct pipe_context
*pctx
,
847 enum pipe_shader_type shader
,
848 unsigned start
, unsigned nr
,
849 struct pipe_sampler_view
**views
)
851 struct v3d_context
*v3d
= v3d_context(pctx
);
852 struct v3d_texture_stateobj
*stage_tex
= v3d_get_stage_tex(v3d
, shader
);
858 for (i
= 0; i
< nr
; i
++) {
861 pipe_sampler_view_reference(&stage_tex
->textures
[i
], views
[i
]);
864 for (; i
< stage_tex
->num_textures
; i
++) {
865 pipe_sampler_view_reference(&stage_tex
->textures
[i
], NULL
);
868 stage_tex
->num_textures
= new_nr
;
871 static struct pipe_stream_output_target
*
872 v3d_create_stream_output_target(struct pipe_context
*pctx
,
873 struct pipe_resource
*prsc
,
874 unsigned buffer_offset
,
875 unsigned buffer_size
)
877 struct pipe_stream_output_target
*target
;
879 target
= CALLOC_STRUCT(pipe_stream_output_target
);
883 pipe_reference_init(&target
->reference
, 1);
884 pipe_resource_reference(&target
->buffer
, prsc
);
886 target
->context
= pctx
;
887 target
->buffer_offset
= buffer_offset
;
888 target
->buffer_size
= buffer_size
;
894 v3d_stream_output_target_destroy(struct pipe_context
*pctx
,
895 struct pipe_stream_output_target
*target
)
897 pipe_resource_reference(&target
->buffer
, NULL
);
902 v3d_set_stream_output_targets(struct pipe_context
*pctx
,
903 unsigned num_targets
,
904 struct pipe_stream_output_target
**targets
,
905 const unsigned *offsets
)
907 struct v3d_context
*ctx
= v3d_context(pctx
);
908 struct v3d_streamout_stateobj
*so
= &ctx
->streamout
;
911 assert(num_targets
<= ARRAY_SIZE(so
->targets
));
913 for (i
= 0; i
< num_targets
; i
++) {
914 if (offsets
[i
] != -1)
915 so
->offsets
[i
] = offsets
[i
];
917 pipe_so_target_reference(&so
->targets
[i
], targets
[i
]);
920 for (; i
< so
->num_targets
; i
++)
921 pipe_so_target_reference(&so
->targets
[i
], NULL
);
923 so
->num_targets
= num_targets
;
925 ctx
->dirty
|= VC5_DIRTY_STREAMOUT
;
929 v3dX(state_init
)(struct pipe_context
*pctx
)
931 pctx
->set_blend_color
= v3d_set_blend_color
;
932 pctx
->set_stencil_ref
= v3d_set_stencil_ref
;
933 pctx
->set_clip_state
= v3d_set_clip_state
;
934 pctx
->set_sample_mask
= v3d_set_sample_mask
;
935 pctx
->set_constant_buffer
= v3d_set_constant_buffer
;
936 pctx
->set_framebuffer_state
= v3d_set_framebuffer_state
;
937 pctx
->set_polygon_stipple
= v3d_set_polygon_stipple
;
938 pctx
->set_scissor_states
= v3d_set_scissor_states
;
939 pctx
->set_viewport_states
= v3d_set_viewport_states
;
941 pctx
->set_vertex_buffers
= v3d_set_vertex_buffers
;
943 pctx
->create_blend_state
= v3d_create_blend_state
;
944 pctx
->bind_blend_state
= v3d_blend_state_bind
;
945 pctx
->delete_blend_state
= v3d_generic_cso_state_delete
;
947 pctx
->create_rasterizer_state
= v3d_create_rasterizer_state
;
948 pctx
->bind_rasterizer_state
= v3d_rasterizer_state_bind
;
949 pctx
->delete_rasterizer_state
= v3d_generic_cso_state_delete
;
951 pctx
->create_depth_stencil_alpha_state
= v3d_create_depth_stencil_alpha_state
;
952 pctx
->bind_depth_stencil_alpha_state
= v3d_zsa_state_bind
;
953 pctx
->delete_depth_stencil_alpha_state
= v3d_generic_cso_state_delete
;
955 pctx
->create_vertex_elements_state
= v3d_vertex_state_create
;
956 pctx
->delete_vertex_elements_state
= v3d_generic_cso_state_delete
;
957 pctx
->bind_vertex_elements_state
= v3d_vertex_state_bind
;
959 pctx
->create_sampler_state
= v3d_create_sampler_state
;
960 pctx
->delete_sampler_state
= v3d_sampler_state_delete
;
961 pctx
->bind_sampler_states
= v3d_sampler_states_bind
;
963 pctx
->create_sampler_view
= v3d_create_sampler_view
;
964 pctx
->sampler_view_destroy
= v3d_sampler_view_destroy
;
965 pctx
->set_sampler_views
= v3d_set_sampler_views
;
967 pctx
->create_stream_output_target
= v3d_create_stream_output_target
;
968 pctx
->stream_output_target_destroy
= v3d_stream_output_target_destroy
;
969 pctx
->set_stream_output_targets
= v3d_set_stream_output_targets
;