2 * Copyright © 2014-2015 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * DOC: Render command list generation
27 * In the VC4 driver, render command list generation is performed by the
28 * kernel instead of userspace. We do this because validating a
29 * user-submitted command list is hard to get right and has high CPU overhead,
30 * while the number of valid configurations for render command lists is
31 * actually fairly low.
35 #include "vc4_packet.h"
37 struct vc4_rcl_setup
{
38 struct drm_gem_cma_object
*color_read
;
39 struct drm_gem_cma_object
*color_ms_write
;
40 struct drm_gem_cma_object
*zs_read
;
41 struct drm_gem_cma_object
*zs_write
;
43 struct drm_gem_cma_object
*rcl
;
47 static inline void rcl_u8(struct vc4_rcl_setup
*setup
, u8 val
)
49 *(u8
*)(setup
->rcl
->vaddr
+ setup
->next_offset
) = val
;
50 setup
->next_offset
+= 1;
53 static inline void rcl_u16(struct vc4_rcl_setup
*setup
, u16 val
)
55 *(u16
*)(setup
->rcl
->vaddr
+ setup
->next_offset
) = val
;
56 setup
->next_offset
+= 2;
59 static inline void rcl_u32(struct vc4_rcl_setup
*setup
, u32 val
)
61 *(u32
*)(setup
->rcl
->vaddr
+ setup
->next_offset
) = val
;
62 setup
->next_offset
+= 4;
67 * Emits a no-op STORE_TILE_BUFFER_GENERAL.
69 * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of
70 * some sort before another load is triggered.
72 static void vc4_store_before_load(struct vc4_rcl_setup
*setup
)
74 rcl_u8(setup
, VC4_PACKET_STORE_TILE_BUFFER_GENERAL
);
76 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE
,
77 VC4_LOADSTORE_TILE_BUFFER_BUFFER
) |
78 VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR
|
79 VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR
|
80 VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR
);
81 rcl_u32(setup
, 0); /* no address, since we're in None mode */
85 * Emits a PACKET_TILE_COORDINATES if one isn't already pending.
87 * The tile coordinates packet triggers a pending load if there is one, are
88 * used for clipping during rendering, and determine where loads/stores happen
89 * relative to their base address.
91 static void vc4_tile_coordinates(struct vc4_rcl_setup
*setup
,
92 uint32_t x
, uint32_t y
)
94 rcl_u8(setup
, VC4_PACKET_TILE_COORDINATES
);
99 static void emit_tile(struct vc4_exec_info
*exec
,
100 struct vc4_rcl_setup
*setup
,
101 uint8_t x
, uint8_t y
, bool first
, bool last
)
103 bool has_bin
= exec
->args
->bin_cl_size
!= 0;
105 /* Note that the load doesn't actually occur until the
106 * tile coords packet is processed, and only one load
107 * may be outstanding at a time.
109 if (setup
->color_read
) {
110 rcl_u8(setup
, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
);
111 rcl_u16(setup
, exec
->args
->color_read
.bits
);
113 setup
->color_read
->paddr
+
114 exec
->args
->color_read
.offset
);
117 if (setup
->zs_read
) {
118 if (setup
->color_read
) {
119 /* Exec previous load. */
120 vc4_tile_coordinates(setup
, x
, y
);
121 vc4_store_before_load(setup
);
124 rcl_u8(setup
, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
);
125 rcl_u16(setup
, exec
->args
->zs_read
.bits
);
127 setup
->zs_read
->paddr
+ exec
->args
->zs_read
.offset
);
130 /* Clipping depends on tile coordinates having been
131 * emitted, so we always need one here.
133 vc4_tile_coordinates(setup
, x
, y
);
135 /* Wait for the binner before jumping to the first
138 if (first
&& has_bin
)
139 rcl_u8(setup
, VC4_PACKET_WAIT_ON_SEMAPHORE
);
142 rcl_u8(setup
, VC4_PACKET_BRANCH_TO_SUB_LIST
);
143 rcl_u32(setup
, (exec
->tile_bo
->paddr
+
144 exec
->tile_alloc_offset
+
145 (y
* exec
->bin_tiles_x
+ x
) * 32));
148 if (setup
->zs_write
) {
149 rcl_u8(setup
, VC4_PACKET_STORE_TILE_BUFFER_GENERAL
);
150 rcl_u16(setup
, exec
->args
->zs_write
.bits
|
151 (setup
->color_ms_write
?
152 VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR
: 0));
154 (setup
->zs_write
->paddr
+ exec
->args
->zs_write
.offset
) |
155 ((last
&& !setup
->color_ms_write
) ?
156 VC4_LOADSTORE_TILE_BUFFER_EOF
: 0));
159 if (setup
->color_ms_write
) {
160 if (setup
->zs_write
) {
161 /* Reset after previous store */
162 vc4_tile_coordinates(setup
, x
, y
);
166 rcl_u8(setup
, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF
);
168 rcl_u8(setup
, VC4_PACKET_STORE_MS_TILE_BUFFER
);
172 static int vc4_create_rcl_bo(struct drm_device
*dev
, struct vc4_exec_info
*exec
,
173 struct vc4_rcl_setup
*setup
)
175 bool has_bin
= exec
->args
->bin_cl_size
!= 0;
176 uint8_t min_x_tile
= exec
->args
->min_x_tile
;
177 uint8_t min_y_tile
= exec
->args
->min_y_tile
;
178 uint8_t max_x_tile
= exec
->args
->max_x_tile
;
179 uint8_t max_y_tile
= exec
->args
->max_y_tile
;
180 uint8_t xtiles
= max_x_tile
- min_x_tile
+ 1;
181 uint8_t ytiles
= max_y_tile
- min_y_tile
+ 1;
183 uint32_t size
, loop_body_size
;
185 size
= VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE
;
186 loop_body_size
= VC4_PACKET_TILE_COORDINATES_SIZE
;
188 if (exec
->args
->flags
& VC4_SUBMIT_CL_USE_CLEAR_COLOR
) {
189 size
+= VC4_PACKET_CLEAR_COLORS_SIZE
+
190 VC4_PACKET_TILE_COORDINATES_SIZE
+
191 VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE
;
194 if (setup
->color_read
) {
195 loop_body_size
+= (VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE
);
197 if (setup
->zs_read
) {
198 if (setup
->color_read
) {
199 loop_body_size
+= VC4_PACKET_TILE_COORDINATES_SIZE
;
200 loop_body_size
+= VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE
;
202 loop_body_size
+= VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE
;
206 size
+= VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE
;
207 loop_body_size
+= VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE
;
211 loop_body_size
+= VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE
;
212 if (setup
->color_ms_write
) {
214 loop_body_size
+= VC4_PACKET_TILE_COORDINATES_SIZE
;
215 loop_body_size
+= VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE
;
217 size
+= xtiles
* ytiles
* loop_body_size
;
219 setup
->rcl
= drm_gem_cma_create(dev
, size
);
222 list_addtail(&to_vc4_bo(&setup
->rcl
->base
)->unref_head
,
225 rcl_u8(setup
, VC4_PACKET_TILE_RENDERING_MODE_CONFIG
);
227 (setup
->color_ms_write
?
228 (setup
->color_ms_write
->paddr
+
229 exec
->args
->color_ms_write
.offset
) :
231 rcl_u16(setup
, exec
->args
->width
);
232 rcl_u16(setup
, exec
->args
->height
);
233 rcl_u16(setup
, exec
->args
->color_ms_write
.bits
);
235 /* The tile buffer gets cleared when the previous tile is stored. If
236 * the clear values changed between frames, then the tile buffer has
237 * stale clear values in it, so we have to do a store in None mode (no
238 * writes) so that we trigger the tile buffer clear.
240 if (exec
->args
->flags
& VC4_SUBMIT_CL_USE_CLEAR_COLOR
) {
241 rcl_u8(setup
, VC4_PACKET_CLEAR_COLORS
);
242 rcl_u32(setup
, exec
->args
->clear_color
[0]);
243 rcl_u32(setup
, exec
->args
->clear_color
[1]);
244 rcl_u32(setup
, exec
->args
->clear_z
);
245 rcl_u8(setup
, exec
->args
->clear_s
);
247 vc4_tile_coordinates(setup
, 0, 0);
249 rcl_u8(setup
, VC4_PACKET_STORE_TILE_BUFFER_GENERAL
);
250 rcl_u16(setup
, VC4_LOADSTORE_TILE_BUFFER_NONE
);
251 rcl_u32(setup
, 0); /* no address, since we're in None mode */
254 for (y
= min_y_tile
; y
<= max_y_tile
; y
++) {
255 for (x
= min_x_tile
; x
<= max_x_tile
; x
++) {
256 bool first
= (x
== min_x_tile
&& y
== min_y_tile
);
257 bool last
= (x
== max_x_tile
&& y
== max_y_tile
);
258 emit_tile(exec
, setup
, x
, y
, first
, last
);
262 BUG_ON(setup
->next_offset
!= size
);
263 exec
->ct1ca
= setup
->rcl
->paddr
;
264 exec
->ct1ea
= setup
->rcl
->paddr
+ setup
->next_offset
;
269 static int vc4_rcl_surface_setup(struct vc4_exec_info
*exec
,
270 struct drm_gem_cma_object
**obj
,
271 struct drm_vc4_submit_rcl_surface
*surf
)
273 uint8_t tiling
= VC4_GET_FIELD(surf
->bits
,
274 VC4_LOADSTORE_TILE_BUFFER_TILING
);
275 uint8_t buffer
= VC4_GET_FIELD(surf
->bits
,
276 VC4_LOADSTORE_TILE_BUFFER_BUFFER
);
277 uint8_t format
= VC4_GET_FIELD(surf
->bits
,
278 VC4_LOADSTORE_TILE_BUFFER_FORMAT
);
281 if (surf
->pad
!= 0) {
282 DRM_ERROR("Padding unset\n");
286 if (surf
->hindex
== ~0)
289 if (!vc4_use_bo(exec
, surf
->hindex
, VC4_MODE_RENDER
, obj
))
292 if (surf
->bits
& ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK
|
293 VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK
|
294 VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK
)) {
295 DRM_ERROR("Unknown bits in load/store: 0x%04x\n",
300 if (tiling
> VC4_TILING_FORMAT_LT
) {
301 DRM_ERROR("Bad tiling format\n");
305 if (buffer
== VC4_LOADSTORE_TILE_BUFFER_ZS
) {
307 DRM_ERROR("No color format should be set for ZS\n");
311 } else if (buffer
== VC4_LOADSTORE_TILE_BUFFER_COLOR
) {
313 case VC4_LOADSTORE_TILE_BUFFER_BGR565
:
314 case VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER
:
317 case VC4_LOADSTORE_TILE_BUFFER_RGBA8888
:
321 DRM_ERROR("Bad tile buffer format\n");
325 DRM_ERROR("Bad load/store buffer %d.\n", buffer
);
329 if (surf
->offset
& 0xf) {
330 DRM_ERROR("load/store buffer must be 16b aligned.\n");
334 if (!vc4_check_tex_size(exec
, *obj
, surf
->offset
, tiling
,
335 exec
->args
->width
, exec
->args
->height
, cpp
)) {
343 vc4_rcl_ms_surface_setup(struct vc4_exec_info
*exec
,
344 struct drm_gem_cma_object
**obj
,
345 struct drm_vc4_submit_rcl_surface
*surf
)
347 uint8_t tiling
= VC4_GET_FIELD(surf
->bits
,
348 VC4_RENDER_CONFIG_MEMORY_FORMAT
);
349 uint8_t format
= VC4_GET_FIELD(surf
->bits
,
350 VC4_RENDER_CONFIG_FORMAT
);
353 if (surf
->pad
!= 0) {
354 DRM_ERROR("Padding unset\n");
358 if (surf
->bits
& ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK
|
359 VC4_RENDER_CONFIG_FORMAT_MASK
)) {
360 DRM_ERROR("Unknown bits in render config: 0x%04x\n",
365 if (surf
->hindex
== ~0)
368 if (!vc4_use_bo(exec
, surf
->hindex
, VC4_MODE_RENDER
, obj
))
371 if (tiling
> VC4_TILING_FORMAT_LT
) {
372 DRM_ERROR("Bad tiling format\n");
377 case VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED
:
378 case VC4_RENDER_CONFIG_FORMAT_BGR565
:
381 case VC4_RENDER_CONFIG_FORMAT_RGBA8888
:
385 DRM_ERROR("Bad tile buffer format\n");
389 if (!vc4_check_tex_size(exec
, *obj
, surf
->offset
, tiling
,
390 exec
->args
->width
, exec
->args
->height
, cpp
)) {
397 int vc4_get_rcl(struct drm_device
*dev
, struct vc4_exec_info
*exec
)
399 struct vc4_rcl_setup setup
= {0};
400 struct drm_vc4_submit_cl
*args
= exec
->args
;
401 bool has_bin
= args
->bin_cl_size
!= 0;
404 if (args
->min_x_tile
> args
->max_x_tile
||
405 args
->min_y_tile
> args
->max_y_tile
) {
406 DRM_ERROR("Bad render tile set (%d,%d)-(%d,%d)\n",
407 args
->min_x_tile
, args
->min_y_tile
,
408 args
->max_x_tile
, args
->max_y_tile
);
413 (args
->max_x_tile
> exec
->bin_tiles_x
||
414 args
->max_y_tile
> exec
->bin_tiles_y
)) {
415 DRM_ERROR("Render tiles (%d,%d) outside of bin config (%d,%d)\n",
416 args
->max_x_tile
, args
->max_y_tile
,
417 exec
->bin_tiles_x
, exec
->bin_tiles_y
);
421 ret
= vc4_rcl_surface_setup(exec
, &setup
.color_read
, &args
->color_read
);
425 ret
= vc4_rcl_ms_surface_setup(exec
, &setup
.color_ms_write
,
426 &args
->color_ms_write
);
430 ret
= vc4_rcl_surface_setup(exec
, &setup
.zs_read
, &args
->zs_read
);
434 ret
= vc4_rcl_surface_setup(exec
, &setup
.zs_write
, &args
->zs_write
);
438 /* We shouldn't even have the job submitted to us if there's no
439 * surface to write out.
441 if (!setup
.color_ms_write
&& !setup
.zs_write
) {
442 DRM_ERROR("RCL requires color or Z/S write\n");
446 return vc4_create_rcl_bo(dev
, exec
, &setup
);