2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * Command list validator for VC4.
27 * The VC4 has no IOMMU between it and system memory. So, a user with
28 * access to execute command lists could escalate privilege by
29 * overwriting system memory (drawing to it as a framebuffer) or
30 * reading system memory it shouldn't (reading it as a texture, or
31 * uniform data, or vertex data).
33 * This validates command lists to ensure that all accesses are within
34 * the bounds of the GEM objects referenced. It explicitly whitelists
35 * packets, and looks at the offsets in any address fields to make
36 * sure they're constrained within the BOs they reference.
38 * Note that because of the validation that's happening anyway, this
39 * is where GEM relocation processing happens.
43 #include "vc4_packet.h"
45 #define VALIDATE_ARGS \
46 struct vc4_exec_info *exec, \
51 /** Return the width in pixels of a 64-byte microtile. */
64 DRM_ERROR("unknown cpp: %d\n", cpp
);
69 /** Return the height in pixels of a 64-byte microtile. */
81 DRM_ERROR("unknown cpp: %d\n", cpp
);
87 * The texture unit decides what tiling format a particular miplevel is using
88 * this function, so we lay out our miptrees accordingly.
91 size_is_lt(uint32_t width
, uint32_t height
, int cpp
)
93 return (width
<= 4 * utile_width(cpp
) ||
94 height
<= 4 * utile_height(cpp
));
97 struct drm_gem_cma_object
*
98 vc4_use_bo(struct vc4_exec_info
*exec
,
100 enum vc4_bo_mode mode
)
102 struct drm_gem_cma_object
*obj
;
104 if (hindex
>= exec
->bo_count
) {
105 DRM_ERROR("BO index %d greater than BO count %d\n",
106 hindex
, exec
->bo_count
);
109 obj
= exec
->bo
[hindex
].bo
;
111 if (exec
->bo
[hindex
].mode
!= mode
) {
112 if (exec
->bo
[hindex
].mode
== VC4_MODE_UNDECIDED
) {
113 exec
->bo
[hindex
].mode
= mode
;
115 DRM_ERROR("BO index %d reused with mode %d vs %d\n",
116 hindex
, exec
->bo
[hindex
].mode
, mode
);
124 static struct drm_gem_cma_object
*
125 vc4_use_handle(struct vc4_exec_info
*exec
,
126 uint32_t gem_handles_packet_index
,
127 enum vc4_bo_mode mode
)
129 return vc4_use_bo(exec
, exec
->bo_index
[gem_handles_packet_index
], mode
);
133 validate_bin_pos(struct vc4_exec_info
*exec
, void *untrusted
, uint32_t pos
)
135 /* Note that the untrusted pointer passed to these functions is
136 * incremented past the packet byte.
138 return (untrusted
- 1 == exec
->bin_u
+ pos
);
142 gl_shader_rec_size(uint32_t pointer_bits
)
144 uint32_t attribute_count
= pointer_bits
& 7;
145 bool extended
= pointer_bits
& 8;
147 if (attribute_count
== 0)
151 return 100 + attribute_count
* 4;
153 return 36 + attribute_count
* 8;
157 vc4_check_tex_size(struct vc4_exec_info
*exec
, struct drm_gem_cma_object
*fbo
,
158 uint32_t offset
, uint8_t tiling_format
,
159 uint32_t width
, uint32_t height
, uint8_t cpp
)
161 uint32_t aligned_width
, aligned_height
, stride
, size
;
162 uint32_t utile_w
= utile_width(cpp
);
163 uint32_t utile_h
= utile_height(cpp
);
165 /* The shaded vertex format stores signed 12.4 fixed point
166 * (-2048,2047) offsets from the viewport center, so we should
167 * never have a render target larger than 4096. The texture
168 * unit can only sample from 2048x2048, so it's even more
169 * restricted. This lets us avoid worrying about overflow in
172 if (width
> 4096 || height
> 4096) {
173 DRM_ERROR("Surface dimesions (%d,%d) too large", width
, height
);
177 switch (tiling_format
) {
178 case VC4_TILING_FORMAT_LINEAR
:
179 aligned_width
= round_up(width
, utile_w
);
180 aligned_height
= height
;
182 case VC4_TILING_FORMAT_T
:
183 aligned_width
= round_up(width
, utile_w
* 8);
184 aligned_height
= round_up(height
, utile_h
* 8);
186 case VC4_TILING_FORMAT_LT
:
187 aligned_width
= round_up(width
, utile_w
);
188 aligned_height
= round_up(height
, utile_h
);
191 DRM_ERROR("buffer tiling %d unsupported\n", tiling_format
);
195 stride
= aligned_width
* cpp
;
196 size
= stride
* aligned_height
;
198 if (size
+ offset
< size
||
199 size
+ offset
> fbo
->base
.size
) {
200 DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %d)\n",
202 aligned_width
, aligned_height
,
203 size
, offset
, fbo
->base
.size
);
212 validate_flush(VALIDATE_ARGS
)
214 if (!validate_bin_pos(exec
, untrusted
, exec
->args
->bin_cl_size
- 1)) {
215 DRM_ERROR("Bin CL must end with VC4_PACKET_FLUSH\n");
218 exec
->found_flush
= true;
224 validate_start_tile_binning(VALIDATE_ARGS
)
226 if (exec
->found_start_tile_binning_packet
) {
227 DRM_ERROR("Duplicate VC4_PACKET_START_TILE_BINNING\n");
230 exec
->found_start_tile_binning_packet
= true;
232 if (!exec
->found_tile_binning_mode_config_packet
) {
233 DRM_ERROR("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
241 validate_increment_semaphore(VALIDATE_ARGS
)
243 if (!validate_bin_pos(exec
, untrusted
, exec
->args
->bin_cl_size
- 2)) {
244 DRM_ERROR("Bin CL must end with "
245 "VC4_PACKET_INCREMENT_SEMAPHORE\n");
248 exec
->found_increment_semaphore_packet
= true;
254 validate_indexed_prim_list(VALIDATE_ARGS
)
256 struct drm_gem_cma_object
*ib
;
257 uint32_t length
= *(uint32_t *)(untrusted
+ 1);
258 uint32_t offset
= *(uint32_t *)(untrusted
+ 5);
259 uint32_t max_index
= *(uint32_t *)(untrusted
+ 9);
260 uint32_t index_size
= (*(uint8_t *)(untrusted
+ 0) >> 4) ? 2 : 1;
261 struct vc4_shader_state
*shader_state
;
263 /* Check overflow condition */
264 if (exec
->shader_state_count
== 0) {
265 DRM_ERROR("shader state must precede primitives\n");
268 shader_state
= &exec
->shader_state
[exec
->shader_state_count
- 1];
270 if (max_index
> shader_state
->max_index
)
271 shader_state
->max_index
= max_index
;
273 ib
= vc4_use_handle(exec
, 0, VC4_MODE_RENDER
);
277 if (offset
> ib
->base
.size
||
278 (ib
->base
.size
- offset
) / index_size
< length
) {
279 DRM_ERROR("IB access overflow (%d + %d*%d > %d)\n",
280 offset
, length
, index_size
, ib
->base
.size
);
284 *(uint32_t *)(validated
+ 5) = ib
->paddr
+ offset
;
290 validate_gl_array_primitive(VALIDATE_ARGS
)
292 uint32_t length
= *(uint32_t *)(untrusted
+ 1);
293 uint32_t base_index
= *(uint32_t *)(untrusted
+ 5);
295 struct vc4_shader_state
*shader_state
;
297 /* Check overflow condition */
298 if (exec
->shader_state_count
== 0) {
299 DRM_ERROR("shader state must precede primitives\n");
302 shader_state
= &exec
->shader_state
[exec
->shader_state_count
- 1];
304 if (length
+ base_index
< length
) {
305 DRM_ERROR("primitive vertex count overflow\n");
308 max_index
= length
+ base_index
- 1;
310 if (max_index
> shader_state
->max_index
)
311 shader_state
->max_index
= max_index
;
317 validate_gl_shader_state(VALIDATE_ARGS
)
319 uint32_t i
= exec
->shader_state_count
++;
321 if (i
>= exec
->shader_state_size
) {
322 DRM_ERROR("More requests for shader states than declared\n");
326 exec
->shader_state
[i
].addr
= *(uint32_t *)untrusted
;
327 exec
->shader_state
[i
].max_index
= 0;
329 if (exec
->shader_state
[i
].addr
& ~0xf) {
330 DRM_ERROR("high bits set in GL shader rec reference\n");
334 *(uint32_t *)validated
= (exec
->shader_rec_p
+
335 exec
->shader_state
[i
].addr
);
337 exec
->shader_rec_p
+=
338 roundup(gl_shader_rec_size(exec
->shader_state
[i
].addr
), 16);
344 validate_tile_binning_config(VALIDATE_ARGS
)
346 struct drm_device
*dev
= exec
->exec_bo
->base
.dev
;
348 uint32_t tile_state_size
, tile_alloc_size
;
351 if (exec
->found_tile_binning_mode_config_packet
) {
352 DRM_ERROR("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
355 exec
->found_tile_binning_mode_config_packet
= true;
357 exec
->bin_tiles_x
= *(uint8_t *)(untrusted
+ 12);
358 exec
->bin_tiles_y
= *(uint8_t *)(untrusted
+ 13);
359 tile_count
= exec
->bin_tiles_x
* exec
->bin_tiles_y
;
360 flags
= *(uint8_t *)(untrusted
+ 14);
362 if (exec
->bin_tiles_x
== 0 ||
363 exec
->bin_tiles_y
== 0) {
364 DRM_ERROR("Tile binning config of %dx%d too small\n",
365 exec
->bin_tiles_x
, exec
->bin_tiles_y
);
369 if (flags
& (VC4_BIN_CONFIG_DB_NON_MS
|
370 VC4_BIN_CONFIG_TILE_BUFFER_64BIT
|
371 VC4_BIN_CONFIG_MS_MODE_4X
)) {
372 DRM_ERROR("unsupported bining config flags 0x%02x\n", flags
);
376 /* The tile state data array is 48 bytes per tile, and we put it at
377 * the start of a BO containing both it and the tile alloc.
379 tile_state_size
= 48 * tile_count
;
381 /* Since the tile alloc array will follow us, align. */
382 exec
->tile_alloc_offset
= roundup(tile_state_size
, 4096);
384 *(uint8_t *)(validated
+ 14) =
385 ((flags
& ~(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK
|
386 VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK
)) |
387 VC4_BIN_CONFIG_AUTO_INIT_TSDA
|
388 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32
,
389 VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE
) |
390 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128
,
391 VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE
));
393 /* Initial block size. */
394 tile_alloc_size
= 32 * tile_count
;
397 * The initial allocation gets rounded to the next 256 bytes before
398 * the hardware starts fulfilling further allocations.
400 tile_alloc_size
= roundup(tile_alloc_size
, 256);
402 /* Add space for the extra allocations. This is what gets used first,
403 * before overflow memory. It must have at least 4096 bytes, but we
404 * want to avoid overflow memory usage if possible.
406 tile_alloc_size
+= 1024 * 1024;
408 exec
->tile_bo
= drm_gem_cma_create(dev
, exec
->tile_alloc_offset
+
412 list_addtail(&to_vc4_bo(&exec
->tile_bo
->base
)->unref_head
,
415 /* tile alloc address. */
416 *(uint32_t *)(validated
+ 0) = (exec
->tile_bo
->paddr
+
417 exec
->tile_alloc_offset
);
418 /* tile alloc size. */
419 *(uint32_t *)(validated
+ 4) = tile_alloc_size
;
420 /* tile state address. */
421 *(uint32_t *)(validated
+ 8) = exec
->tile_bo
->paddr
;
427 validate_gem_handles(VALIDATE_ARGS
)
429 memcpy(exec
->bo_index
, untrusted
, sizeof(exec
->bo_index
));
433 #define VC4_DEFINE_PACKET(packet, name, func) \
434 [packet] = { packet ## _SIZE, name, func }
436 static const struct cmd_info
{
439 int (*func
)(struct vc4_exec_info
*exec
, void *validated
,
442 VC4_DEFINE_PACKET(VC4_PACKET_HALT
, "halt", NULL
),
443 VC4_DEFINE_PACKET(VC4_PACKET_NOP
, "nop", NULL
),
444 VC4_DEFINE_PACKET(VC4_PACKET_FLUSH
, "flush", validate_flush
),
445 VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL
, "flush all state", NULL
),
446 VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING
, "start tile binning", validate_start_tile_binning
),
447 VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE
, "increment semaphore", validate_increment_semaphore
),
449 VC4_DEFINE_PACKET(VC4_PACKET_GL_INDEXED_PRIMITIVE
, "Indexed Primitive List", validate_indexed_prim_list
),
451 VC4_DEFINE_PACKET(VC4_PACKET_GL_ARRAY_PRIMITIVE
, "Vertex Array Primitives", validate_gl_array_primitive
),
453 /* This is only used by clipped primitives (packets 48 and 49), which
454 * we don't support parsing yet.
456 VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT
, "primitive list format", NULL
),
458 VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE
, "GL Shader State", validate_gl_shader_state
),
459 /* We don't support validating NV shader states. */
461 VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS
, "configuration bits", NULL
),
462 VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS
, "flat shade flags", NULL
),
463 VC4_DEFINE_PACKET(VC4_PACKET_POINT_SIZE
, "point size", NULL
),
464 VC4_DEFINE_PACKET(VC4_PACKET_LINE_WIDTH
, "line width", NULL
),
465 VC4_DEFINE_PACKET(VC4_PACKET_RHT_X_BOUNDARY
, "RHT X boundary", NULL
),
466 VC4_DEFINE_PACKET(VC4_PACKET_DEPTH_OFFSET
, "Depth Offset", NULL
),
467 VC4_DEFINE_PACKET(VC4_PACKET_CLIP_WINDOW
, "Clip Window", NULL
),
468 VC4_DEFINE_PACKET(VC4_PACKET_VIEWPORT_OFFSET
, "Viewport Offset", NULL
),
469 VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_XY_SCALING
, "Clipper XY Scaling", NULL
),
470 /* Note: The docs say this was also 105, but it was 106 in the
471 * initial userland code drop.
473 VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_Z_SCALING
, "Clipper Z Scale and Offset", NULL
),
475 VC4_DEFINE_PACKET(VC4_PACKET_TILE_BINNING_MODE_CONFIG
, "tile binning configuration", validate_tile_binning_config
),
477 VC4_DEFINE_PACKET(VC4_PACKET_GEM_HANDLES
, "GEM handles", validate_gem_handles
),
481 vc4_validate_bin_cl(struct drm_device
*dev
,
484 struct vc4_exec_info
*exec
)
486 uint32_t len
= exec
->args
->bin_cl_size
;
487 uint32_t dst_offset
= 0;
488 uint32_t src_offset
= 0;
490 while (src_offset
< len
) {
491 void *dst_pkt
= validated
+ dst_offset
;
492 void *src_pkt
= unvalidated
+ src_offset
;
493 u8 cmd
= *(uint8_t *)src_pkt
;
494 const struct cmd_info
*info
;
496 if (cmd
> ARRAY_SIZE(cmd_info
)) {
497 DRM_ERROR("0x%08x: packet %d out of bounds\n",
502 info
= &cmd_info
[cmd
];
504 DRM_ERROR("0x%08x: packet %d invalid\n",
510 DRM_INFO("0x%08x: packet %d (%s) size %d processing...\n",
511 src_offset
, cmd
, info
->name
, info
->len
);
514 if (src_offset
+ info
->len
> len
) {
515 DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x "
516 "exceeds bounds (0x%08x)\n",
517 src_offset
, cmd
, info
->name
, info
->len
,
522 if (cmd
!= VC4_PACKET_GEM_HANDLES
)
523 memcpy(dst_pkt
, src_pkt
, info
->len
);
525 if (info
->func
&& info
->func(exec
,
528 DRM_ERROR("0x%08x: packet %d (%s) failed to "
530 src_offset
, cmd
, info
->name
);
534 src_offset
+= info
->len
;
535 /* GEM handle loading doesn't produce HW packets. */
536 if (cmd
!= VC4_PACKET_GEM_HANDLES
)
537 dst_offset
+= info
->len
;
539 /* When the CL hits halt, it'll stop reading anything else. */
540 if (cmd
== VC4_PACKET_HALT
)
544 exec
->ct0ea
= exec
->ct0ca
+ dst_offset
;
546 if (!exec
->found_start_tile_binning_packet
) {
547 DRM_ERROR("Bin CL missing VC4_PACKET_START_TILE_BINNING\n");
551 /* The bin CL must be ended with INCREMENT_SEMAPHORE and FLUSH. The
552 * semaphore is used to trigger the render CL to start up, and the
553 * FLUSH is what caps the bin lists with
554 * VC4_PACKET_RETURN_FROM_SUB_LIST (so they jump back to the main
555 * render CL when they get called to) and actually triggers the queued
556 * semaphore increment.
558 if (!exec
->found_increment_semaphore_packet
|| !exec
->found_flush
) {
559 DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + "
560 "VC4_PACKET_FLUSH\n");
568 reloc_tex(struct vc4_exec_info
*exec
,
569 void *uniform_data_u
,
570 struct vc4_texture_sample_info
*sample
,
571 uint32_t texture_handle_index
)
574 struct drm_gem_cma_object
*tex
;
575 uint32_t p0
= *(uint32_t *)(uniform_data_u
+ sample
->p_offset
[0]);
576 uint32_t p1
= *(uint32_t *)(uniform_data_u
+ sample
->p_offset
[1]);
577 uint32_t p2
= (sample
->p_offset
[2] != ~0 ?
578 *(uint32_t *)(uniform_data_u
+ sample
->p_offset
[2]) : 0);
579 uint32_t p3
= (sample
->p_offset
[3] != ~0 ?
580 *(uint32_t *)(uniform_data_u
+ sample
->p_offset
[3]) : 0);
581 uint32_t *validated_p0
= exec
->uniforms_v
+ sample
->p_offset
[0];
582 uint32_t offset
= p0
& VC4_TEX_P0_OFFSET_MASK
;
583 uint32_t miplevels
= VC4_GET_FIELD(p0
, VC4_TEX_P0_MIPLVLS
);
584 uint32_t width
= VC4_GET_FIELD(p1
, VC4_TEX_P1_WIDTH
);
585 uint32_t height
= VC4_GET_FIELD(p1
, VC4_TEX_P1_HEIGHT
);
586 uint32_t cpp
, tiling_format
, utile_w
, utile_h
;
588 uint32_t cube_map_stride
= 0;
589 enum vc4_texture_data_type type
;
591 tex
= vc4_use_bo(exec
, texture_handle_index
, VC4_MODE_RENDER
);
595 if (sample
->is_direct
) {
596 uint32_t remaining_size
= tex
->base
.size
- p0
;
597 if (p0
> tex
->base
.size
- 4) {
598 DRM_ERROR("UBO offset greater than UBO size\n");
601 if (p1
> remaining_size
- 4) {
602 DRM_ERROR("UBO clamp would allow reads outside of UBO\n");
605 *validated_p0
= tex
->paddr
+ p0
;
614 if (p0
& VC4_TEX_P0_CMMODE_MASK
) {
615 if (VC4_GET_FIELD(p2
, VC4_TEX_P2_PTYPE
) ==
616 VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE
)
617 cube_map_stride
= p2
& VC4_TEX_P2_CMST_MASK
;
618 if (VC4_GET_FIELD(p3
, VC4_TEX_P2_PTYPE
) ==
619 VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE
) {
620 if (cube_map_stride
) {
621 DRM_ERROR("Cube map stride set twice\n");
625 cube_map_stride
= p3
& VC4_TEX_P2_CMST_MASK
;
627 if (!cube_map_stride
) {
628 DRM_ERROR("Cube map stride not set\n");
633 type
= (VC4_GET_FIELD(p0
, VC4_TEX_P0_TYPE
) |
634 (VC4_GET_FIELD(p1
, VC4_TEX_P1_TYPE4
) << 4));
637 case VC4_TEXTURE_TYPE_RGBA8888
:
638 case VC4_TEXTURE_TYPE_RGBX8888
:
639 case VC4_TEXTURE_TYPE_RGBA32R
:
642 case VC4_TEXTURE_TYPE_RGBA4444
:
643 case VC4_TEXTURE_TYPE_RGBA5551
:
644 case VC4_TEXTURE_TYPE_RGB565
:
645 case VC4_TEXTURE_TYPE_LUMALPHA
:
646 case VC4_TEXTURE_TYPE_S16F
:
647 case VC4_TEXTURE_TYPE_S16
:
650 case VC4_TEXTURE_TYPE_LUMINANCE
:
651 case VC4_TEXTURE_TYPE_ALPHA
:
652 case VC4_TEXTURE_TYPE_S8
:
655 case VC4_TEXTURE_TYPE_ETC1
:
656 case VC4_TEXTURE_TYPE_BW1
:
657 case VC4_TEXTURE_TYPE_A4
:
658 case VC4_TEXTURE_TYPE_A1
:
659 case VC4_TEXTURE_TYPE_RGBA64
:
660 case VC4_TEXTURE_TYPE_YUV422R
:
662 DRM_ERROR("Texture format %d unsupported\n", type
);
665 utile_w
= utile_width(cpp
);
666 utile_h
= utile_height(cpp
);
668 if (type
== VC4_TEXTURE_TYPE_RGBA32R
) {
669 tiling_format
= VC4_TILING_FORMAT_LINEAR
;
671 if (size_is_lt(width
, height
, cpp
))
672 tiling_format
= VC4_TILING_FORMAT_LT
;
674 tiling_format
= VC4_TILING_FORMAT_T
;
677 if (!vc4_check_tex_size(exec
, tex
, offset
+ cube_map_stride
* 5,
678 tiling_format
, width
, height
, cpp
)) {
682 /* The mipmap levels are stored before the base of the texture. Make
683 * sure there is actually space in the BO.
685 for (i
= 1; i
<= miplevels
; i
++) {
686 uint32_t level_width
= max(width
>> i
, 1u);
687 uint32_t level_height
= max(height
>> i
, 1u);
688 uint32_t aligned_width
, aligned_height
;
691 /* Once the levels get small enough, they drop from T to LT. */
692 if (tiling_format
== VC4_TILING_FORMAT_T
&&
693 size_is_lt(level_width
, level_height
, cpp
)) {
694 tiling_format
= VC4_TILING_FORMAT_LT
;
697 switch (tiling_format
) {
698 case VC4_TILING_FORMAT_T
:
699 aligned_width
= round_up(level_width
, utile_w
* 8);
700 aligned_height
= round_up(level_height
, utile_h
* 8);
702 case VC4_TILING_FORMAT_LT
:
703 aligned_width
= round_up(level_width
, utile_w
);
704 aligned_height
= round_up(level_height
, utile_h
);
707 aligned_width
= round_up(level_width
, utile_w
);
708 aligned_height
= level_height
;
712 level_size
= aligned_width
* cpp
* aligned_height
;
714 if (offset
< level_size
) {
715 DRM_ERROR("Level %d (%dx%d -> %dx%d) size %db "
716 "overflowed buffer bounds (offset %d)\n",
717 i
, level_width
, level_height
,
718 aligned_width
, aligned_height
,
723 offset
-= level_size
;
726 *validated_p0
= tex
->paddr
+ p0
;
730 DRM_INFO("Texture p0 at %d: 0x%08x\n", sample
->p_offset
[0], p0
);
731 DRM_INFO("Texture p1 at %d: 0x%08x\n", sample
->p_offset
[1], p1
);
732 DRM_INFO("Texture p2 at %d: 0x%08x\n", sample
->p_offset
[2], p2
);
733 DRM_INFO("Texture p3 at %d: 0x%08x\n", sample
->p_offset
[3], p3
);
738 validate_gl_shader_rec(struct drm_device
*dev
,
739 struct vc4_exec_info
*exec
,
740 struct vc4_shader_state
*state
)
742 uint32_t *src_handles
;
744 static const uint32_t shader_reloc_offsets
[] = {
749 uint32_t shader_reloc_count
= ARRAY_SIZE(shader_reloc_offsets
);
750 struct drm_gem_cma_object
*bo
[shader_reloc_count
+ 8];
751 uint32_t nr_attributes
, nr_relocs
, packet_size
;
754 nr_attributes
= state
->addr
& 0x7;
755 if (nr_attributes
== 0)
757 packet_size
= gl_shader_rec_size(state
->addr
);
759 nr_relocs
= ARRAY_SIZE(shader_reloc_offsets
) + nr_attributes
;
760 if (nr_relocs
* 4 > exec
->shader_rec_size
) {
761 DRM_ERROR("overflowed shader recs reading %d handles "
762 "from %d bytes left\n",
763 nr_relocs
, exec
->shader_rec_size
);
766 src_handles
= exec
->shader_rec_u
;
767 exec
->shader_rec_u
+= nr_relocs
* 4;
768 exec
->shader_rec_size
-= nr_relocs
* 4;
770 if (packet_size
> exec
->shader_rec_size
) {
771 DRM_ERROR("overflowed shader recs copying %db packet "
772 "from %d bytes left\n",
773 packet_size
, exec
->shader_rec_size
);
776 pkt_u
= exec
->shader_rec_u
;
777 pkt_v
= exec
->shader_rec_v
;
778 memcpy(pkt_v
, pkt_u
, packet_size
);
779 exec
->shader_rec_u
+= packet_size
;
780 /* Shader recs have to be aligned to 16 bytes (due to the attribute
781 * flags being in the low bytes), so round the next validated shader
782 * rec address up. This should be safe, since we've got so many
783 * relocations in a shader rec packet.
785 BUG_ON(roundup(packet_size
, 16) - packet_size
> nr_relocs
* 4);
786 exec
->shader_rec_v
+= roundup(packet_size
, 16);
787 exec
->shader_rec_size
-= packet_size
;
789 for (i
= 0; i
< shader_reloc_count
; i
++) {
790 bo
[i
] = vc4_use_bo(exec
, src_handles
[i
], VC4_MODE_SHADER
);
794 for (i
= shader_reloc_count
; i
< nr_relocs
; i
++) {
795 bo
[i
] = vc4_use_bo(exec
, src_handles
[i
], VC4_MODE_RENDER
);
800 for (i
= 0; i
< shader_reloc_count
; i
++) {
801 struct vc4_validated_shader_info
*validated_shader
;
802 uint32_t o
= shader_reloc_offsets
[i
];
803 uint32_t src_offset
= *(uint32_t *)(pkt_u
+ o
);
804 uint32_t *texture_handles_u
;
805 void *uniform_data_u
;
808 *(uint32_t *)(pkt_v
+ o
) = bo
[i
]->paddr
+ src_offset
;
810 if (src_offset
!= 0) {
811 DRM_ERROR("Shaders must be at offset 0 of "
816 validated_shader
= to_vc4_bo(&bo
[i
]->base
)->validated_shader
;
817 if (!validated_shader
)
820 if (validated_shader
->uniforms_src_size
>
821 exec
->uniforms_size
) {
822 DRM_ERROR("Uniforms src buffer overflow\n");
826 texture_handles_u
= exec
->uniforms_u
;
827 uniform_data_u
= (texture_handles_u
+
828 validated_shader
->num_texture_samples
);
830 memcpy(exec
->uniforms_v
, uniform_data_u
,
831 validated_shader
->uniforms_size
);
834 tex
< validated_shader
->num_texture_samples
;
838 &validated_shader
->texture_samples
[tex
],
839 texture_handles_u
[tex
])) {
844 *(uint32_t *)(pkt_v
+ o
+ 4) = exec
->uniforms_p
;
846 exec
->uniforms_u
+= validated_shader
->uniforms_src_size
;
847 exec
->uniforms_v
+= validated_shader
->uniforms_size
;
848 exec
->uniforms_p
+= validated_shader
->uniforms_size
;
851 for (i
= 0; i
< nr_attributes
; i
++) {
852 struct drm_gem_cma_object
*vbo
=
853 bo
[ARRAY_SIZE(shader_reloc_offsets
) + i
];
854 uint32_t o
= 36 + i
* 8;
855 uint32_t offset
= *(uint32_t *)(pkt_u
+ o
+ 0);
856 uint32_t attr_size
= *(uint8_t *)(pkt_u
+ o
+ 4) + 1;
857 uint32_t stride
= *(uint8_t *)(pkt_u
+ o
+ 5);
860 if (state
->addr
& 0x8)
861 stride
|= (*(uint32_t *)(pkt_u
+ 100 + i
* 4)) & ~0xff;
863 if (vbo
->base
.size
< offset
||
864 vbo
->base
.size
- offset
< attr_size
) {
865 DRM_ERROR("BO offset overflow (%d + %d > %d)\n",
866 offset
, attr_size
, vbo
->base
.size
);
871 max_index
= ((vbo
->base
.size
- offset
- attr_size
) /
873 if (state
->max_index
> max_index
) {
874 DRM_ERROR("primitives use index %d out of supplied %d\n",
875 state
->max_index
, max_index
);
880 *(uint32_t *)(pkt_v
+ o
) = vbo
->paddr
+ offset
;
887 vc4_validate_shader_recs(struct drm_device
*dev
,
888 struct vc4_exec_info
*exec
)
893 for (i
= 0; i
< exec
->shader_state_count
; i
++) {
894 ret
= validate_gl_shader_rec(dev
, exec
, &exec
->shader_state
[i
]);