src/gallium/drivers/vc4/kernel/vc4_validate.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * Command list validator for VC4.
  26  *
  27  * The VC4 has no IOMMU between it and system memory.  So, a user with
  28  * access to execute command lists could escalate privilege by
  29  * overwriting system memory (drawing to it as a framebuffer) or
  30  * reading system memory it shouldn't (reading it as a texture, or
  31  * uniform data, or vertex data).
  32  *
  33  * This validates command lists to ensure that all accesses are within
  34  * the bounds of the GEM objects referenced.  It explicitly whitelists
  35  * packets, and looks at the offsets in any address fields to make
  36  * sure they're constrained within the BOs they reference.
  37  *
  38  * Note that because of the validation that's happening anyway, this
  39  * is where GEM relocation processing happens.
  40  */
  41
  42 #include "vc4_drv.h"
  43 #include "vc4_packet.h"
  44
  45 #define VALIDATE_ARGS \
  46         struct vc4_exec_info *exec,                     \
  47         void *validated,                                \
  48         void *untrusted
  49
  50
  51 /** Return the width in pixels of a 64-byte microtile. */
  52 static uint32_t
  53 utile_width(int cpp)
  54 {
  55         switch (cpp) {
  56         case 1:
  57         case 2:
  58                 return 8;
  59         case 4:
  60                 return 4;
  61         case 8:
  62                 return 2;
  63         default:
  64                 DRM_ERROR("unknown cpp: %d\n", cpp);
  65                 return 1;
  66         }
  67 }
  68
  69 /** Return the height in pixels of a 64-byte microtile. */
  70 static uint32_t
  71 utile_height(int cpp)
  72 {
  73         switch (cpp) {
  74         case 1:
  75                 return 8;
  76         case 2:
  77         case 4:
  78         case 8:
  79                 return 4;
  80         default:
  81                 DRM_ERROR("unknown cpp: %d\n", cpp);
  82                 return 1;
  83         }
  84 }
  85
  86 /**
  87  * The texture unit decides what tiling format a particular miplevel is using
  88  * this function, so we lay out our miptrees accordingly.
  89  */
  90 static bool
  91 size_is_lt(uint32_t width, uint32_t height, int cpp)
  92 {
  93         return (width <= 4 * utile_width(cpp) ||
  94                 height <= 4 * utile_height(cpp));
  95 }
  96
  97 struct drm_gem_cma_object *
  98 vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
  99 {
 100         struct drm_gem_cma_object *obj;
 101         struct drm_vc4_bo *bo;
 102
 103         if (hindex >= exec->bo_count) {
 104                 DRM_ERROR("BO index %d greater than BO count %d\n",
 105                           hindex, exec->bo_count);
 106                 return NULL;
 107         }
 108         obj = exec->bo[hindex];
 109         bo = to_vc4_bo(&obj->base);
 110
 111         if (bo->validated_shader) {
 112                 DRM_ERROR("Trying to use shader BO as something other than "
 113                           "a shader\n");
 114                 return NULL;
 115         }
 116
 117         return obj;
 118 }
 119
 120 static struct drm_gem_cma_object *
 121 vc4_use_handle(struct vc4_exec_info *exec, uint32_t gem_handles_packet_index)
 122 {
 123         return vc4_use_bo(exec, exec->bo_index[gem_handles_packet_index]);
 124 }
 125
 126 static bool
 127 validate_bin_pos(struct vc4_exec_info *exec, void *untrusted, uint32_t pos)
 128 {
 129         /* Note that the untrusted pointer passed to these functions is
 130          * incremented past the packet byte.
 131          */
 132         return (untrusted - 1 == exec->bin_u + pos);
 133 }
 134
 135 static uint32_t
 136 gl_shader_rec_size(uint32_t pointer_bits)
 137 {
 138         uint32_t attribute_count = pointer_bits & 7;
 139         bool extended = pointer_bits & 8;
 140
 141         if (attribute_count == 0)
 142                 attribute_count = 8;
 143
 144         if (extended)
 145                 return 100 + attribute_count * 4;
 146         else
 147                 return 36 + attribute_count * 8;
 148 }
 149
 150 bool
 151 vc4_check_tex_size(struct vc4_exec_info *exec, struct drm_gem_cma_object *fbo,
 152                    uint32_t offset, uint8_t tiling_format,
 153                    uint32_t width, uint32_t height, uint8_t cpp)
 154 {
 155         uint32_t aligned_width, aligned_height, stride, size;
 156         uint32_t utile_w = utile_width(cpp);
 157         uint32_t utile_h = utile_height(cpp);
 158
 159         /* The shaded vertex format stores signed 12.4 fixed point
 160          * (-2048,2047) offsets from the viewport center, so we should
 161          * never have a render target larger than 4096.  The texture
 162          * unit can only sample from 2048x2048, so it's even more
 163          * restricted.  This lets us avoid worrying about overflow in
 164          * our math.
 165          */
 166         if (width > 4096 || height > 4096) {
 167                 DRM_ERROR("Surface dimesions (%d,%d) too large", width, height);
 168                 return false;
 169         }
 170
 171         switch (tiling_format) {
 172         case VC4_TILING_FORMAT_LINEAR:
 173                 aligned_width = round_up(width, utile_w);
 174                 aligned_height = height;
 175                 break;
 176         case VC4_TILING_FORMAT_T:
 177                 aligned_width = round_up(width, utile_w * 8);
 178                 aligned_height = round_up(height, utile_h * 8);
 179                 break;
 180         case VC4_TILING_FORMAT_LT:
 181                 aligned_width = round_up(width, utile_w);
 182                 aligned_height = round_up(height, utile_h);
 183                 break;
 184         default:
 185                 DRM_ERROR("buffer tiling %d unsupported\n", tiling_format);
 186                 return false;
 187         }
 188
 189         stride = aligned_width * cpp;
 190         size = stride * aligned_height;
 191
 192         if (size + offset < size ||
 193             size + offset > fbo->base.size) {
 194                 DRM_ERROR("Overflow in %dx%d (%dx%d) fbo size (%d + %d > %d)\n",
 195                           width, height,
 196                           aligned_width, aligned_height,
 197                           size, offset, fbo->base.size);
 198                 return false;
 199         }
 200
 201         return true;
 202 }
 203
 204
 205 static int
 206 validate_flush(VALIDATE_ARGS)
 207 {
 208         if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 1)) {
 209                 DRM_ERROR("Bin CL must end with VC4_PACKET_FLUSH\n");
 210                 return false;
 211         }
 212         exec->found_flush = true;
 213
 214         return 0;
 215 }
 216
 217 static int
 218 validate_start_tile_binning(VALIDATE_ARGS)
 219 {
 220         if (exec->found_start_tile_binning_packet) {
 221                 DRM_ERROR("Duplicate VC4_PACKET_START_TILE_BINNING\n");
 222                 return -EINVAL;
 223         }
 224         exec->found_start_tile_binning_packet = true;
 225
 226         if (!exec->found_tile_binning_mode_config_packet) {
 227                 DRM_ERROR("missing VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
 228                 return -EINVAL;
 229         }
 230
 231         return 0;
 232 }
 233
 234 static int
 235 validate_increment_semaphore(VALIDATE_ARGS)
 236 {
 237         if (!validate_bin_pos(exec, untrusted, exec->args->bin_cl_size - 2)) {
 238                 DRM_ERROR("Bin CL must end with "
 239                           "VC4_PACKET_INCREMENT_SEMAPHORE\n");
 240                 return -EINVAL;
 241         }
 242         exec->found_increment_semaphore_packet = true;
 243
 244         return 0;
 245 }
 246
 247 static int
 248 validate_indexed_prim_list(VALIDATE_ARGS)
 249 {
 250         struct drm_gem_cma_object *ib;
 251         uint32_t length = *(uint32_t *)(untrusted + 1);
 252         uint32_t offset = *(uint32_t *)(untrusted + 5);
 253         uint32_t max_index = *(uint32_t *)(untrusted + 9);
 254         uint32_t index_size = (*(uint8_t *)(untrusted + 0) >> 4) ? 2 : 1;
 255         struct vc4_shader_state *shader_state;
 256
 257         /* Check overflow condition */
 258         if (exec->shader_state_count == 0) {
 259                 DRM_ERROR("shader state must precede primitives\n");
 260                 return -EINVAL;
 261         }
 262         shader_state = &exec->shader_state[exec->shader_state_count - 1];
 263
 264         if (max_index > shader_state->max_index)
 265                 shader_state->max_index = max_index;
 266
 267         ib = vc4_use_handle(exec, 0);
 268         if (!ib)
 269                 return -EINVAL;
 270
 271         if (offset > ib->base.size ||
 272             (ib->base.size - offset) / index_size < length) {
 273                 DRM_ERROR("IB access overflow (%d + %d*%d > %d)\n",
 274                           offset, length, index_size, ib->base.size);
 275                 return -EINVAL;
 276         }
 277
 278         *(uint32_t *)(validated + 5) = ib->paddr + offset;
 279
 280         return 0;
 281 }
 282
 283 static int
 284 validate_gl_array_primitive(VALIDATE_ARGS)
 285 {
 286         uint32_t length = *(uint32_t *)(untrusted + 1);
 287         uint32_t base_index = *(uint32_t *)(untrusted + 5);
 288         uint32_t max_index;
 289         struct vc4_shader_state *shader_state;
 290
 291         /* Check overflow condition */
 292         if (exec->shader_state_count == 0) {
 293                 DRM_ERROR("shader state must precede primitives\n");
 294                 return -EINVAL;
 295         }
 296         shader_state = &exec->shader_state[exec->shader_state_count - 1];
 297
 298         if (length + base_index < length) {
 299                 DRM_ERROR("primitive vertex count overflow\n");
 300                 return -EINVAL;
 301         }
 302         max_index = length + base_index - 1;
 303
 304         if (max_index > shader_state->max_index)
 305                 shader_state->max_index = max_index;
 306
 307         return 0;
 308 }
 309
 310 static int
 311 validate_gl_shader_state(VALIDATE_ARGS)
 312 {
 313         uint32_t i = exec->shader_state_count++;
 314
 315         if (i >= exec->shader_state_size) {
 316                 DRM_ERROR("More requests for shader states than declared\n");
 317                 return -EINVAL;
 318         }
 319
 320         exec->shader_state[i].addr = *(uint32_t *)untrusted;
 321         exec->shader_state[i].max_index = 0;
 322
 323         if (exec->shader_state[i].addr & ~0xf) {
 324                 DRM_ERROR("high bits set in GL shader rec reference\n");
 325                 return -EINVAL;
 326         }
 327
 328         *(uint32_t *)validated = (exec->shader_rec_p +
 329                                   exec->shader_state[i].addr);
 330
 331         exec->shader_rec_p +=
 332                 roundup(gl_shader_rec_size(exec->shader_state[i].addr), 16);
 333
 334         return 0;
 335 }
 336
 337 static int
 338 validate_tile_binning_config(VALIDATE_ARGS)
 339 {
 340         struct drm_device *dev = exec->exec_bo->base.dev;
 341         uint8_t flags;
 342         uint32_t tile_state_size, tile_alloc_size;
 343         uint32_t tile_count;
 344
 345         if (exec->found_tile_binning_mode_config_packet) {
 346                 DRM_ERROR("Duplicate VC4_PACKET_TILE_BINNING_MODE_CONFIG\n");
 347                 return -EINVAL;
 348         }
 349         exec->found_tile_binning_mode_config_packet = true;
 350
 351         exec->bin_tiles_x = *(uint8_t *)(untrusted + 12);
 352         exec->bin_tiles_y = *(uint8_t *)(untrusted + 13);
 353         tile_count = exec->bin_tiles_x * exec->bin_tiles_y;
 354         flags = *(uint8_t *)(untrusted + 14);
 355
 356         if (exec->bin_tiles_x == 0 ||
 357             exec->bin_tiles_y == 0) {
 358                 DRM_ERROR("Tile binning config of %dx%d too small\n",
 359                           exec->bin_tiles_x, exec->bin_tiles_y);
 360                 return -EINVAL;
 361         }
 362
 363         if (flags & (VC4_BIN_CONFIG_DB_NON_MS |
 364                      VC4_BIN_CONFIG_TILE_BUFFER_64BIT |
 365                      VC4_BIN_CONFIG_MS_MODE_4X)) {
 366                 DRM_ERROR("unsupported bining config flags 0x%02x\n", flags);
 367                 return -EINVAL;
 368         }
 369
 370         /* The tile state data array is 48 bytes per tile, and we put it at
 371          * the start of a BO containing both it and the tile alloc.
 372          */
 373         tile_state_size = 48 * tile_count;
 374
 375         /* Since the tile alloc array will follow us, align. */
 376         exec->tile_alloc_offset = roundup(tile_state_size, 4096);
 377
 378         *(uint8_t *)(validated + 14) =
 379                 ((flags & ~(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK |
 380                             VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK)) |
 381                  VC4_BIN_CONFIG_AUTO_INIT_TSDA |
 382                  VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32,
 383                                VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE) |
 384                  VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128,
 385                                VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE));
 386
 387         /* Initial block size. */
 388         tile_alloc_size = 32 * tile_count;
 389
 390         /*
 391          * The initial allocation gets rounded to the next 256 bytes before
 392          * the hardware starts fulfilling further allocations.
 393          */
 394         tile_alloc_size = roundup(tile_alloc_size, 256);
 395
 396         /* Add space for the extra allocations.  This is what gets used first,
 397          * before overflow memory.  It must have at least 4096 bytes, but we
 398          * want to avoid overflow memory usage if possible.
 399          */
 400         tile_alloc_size += 1024 * 1024;
 401
 402         exec->tile_bo = drm_gem_cma_create(dev, exec->tile_alloc_offset +
 403                                            tile_alloc_size);
 404         if (!exec->tile_bo)
 405                 return -ENOMEM;
 406         list_addtail(&to_vc4_bo(&exec->tile_bo->base)->unref_head,
 407                      &exec->unref_list);
 408
 409         /* tile alloc address. */
 410         *(uint32_t *)(validated + 0) = (exec->tile_bo->paddr +
 411                                         exec->tile_alloc_offset);
 412         /* tile alloc size. */
 413         *(uint32_t *)(validated + 4) = tile_alloc_size;
 414         /* tile state address. */
 415         *(uint32_t *)(validated + 8) = exec->tile_bo->paddr;
 416
 417         return 0;
 418 }
 419
 420 static int
 421 validate_gem_handles(VALIDATE_ARGS)
 422 {
 423         memcpy(exec->bo_index, untrusted, sizeof(exec->bo_index));
 424         return 0;
 425 }
 426
 427 #define VC4_DEFINE_PACKET(packet, name, func) \
 428         [packet] = { packet ## _SIZE, name, func }
 429
 430 static const struct cmd_info {
 431         uint16_t len;
 432         const char *name;
 433         int (*func)(struct vc4_exec_info *exec, void *validated,
 434                     void *untrusted);
 435 } cmd_info[] = {
 436         VC4_DEFINE_PACKET(VC4_PACKET_HALT, "halt", NULL),
 437         VC4_DEFINE_PACKET(VC4_PACKET_NOP, "nop", NULL),
 438         VC4_DEFINE_PACKET(VC4_PACKET_FLUSH, "flush", validate_flush),
 439         VC4_DEFINE_PACKET(VC4_PACKET_FLUSH_ALL, "flush all state", NULL),
 440         VC4_DEFINE_PACKET(VC4_PACKET_START_TILE_BINNING, "start tile binning", validate_start_tile_binning),
 441         VC4_DEFINE_PACKET(VC4_PACKET_INCREMENT_SEMAPHORE, "increment semaphore", validate_increment_semaphore),
 442
 443         VC4_DEFINE_PACKET(VC4_PACKET_GL_INDEXED_PRIMITIVE, "Indexed Primitive List", validate_indexed_prim_list),
 444
 445         VC4_DEFINE_PACKET(VC4_PACKET_GL_ARRAY_PRIMITIVE, "Vertex Array Primitives", validate_gl_array_primitive),
 446
 447         /* This is only used by clipped primitives (packets 48 and 49), which
 448          * we don't support parsing yet.
 449          */
 450         VC4_DEFINE_PACKET(VC4_PACKET_PRIMITIVE_LIST_FORMAT, "primitive list format", NULL),
 451
 452         VC4_DEFINE_PACKET(VC4_PACKET_GL_SHADER_STATE, "GL Shader State", validate_gl_shader_state),
 453         /* We don't support validating NV shader states. */
 454
 455         VC4_DEFINE_PACKET(VC4_PACKET_CONFIGURATION_BITS, "configuration bits", NULL),
 456         VC4_DEFINE_PACKET(VC4_PACKET_FLAT_SHADE_FLAGS, "flat shade flags", NULL),
 457         VC4_DEFINE_PACKET(VC4_PACKET_POINT_SIZE, "point size", NULL),
 458         VC4_DEFINE_PACKET(VC4_PACKET_LINE_WIDTH, "line width", NULL),
 459         VC4_DEFINE_PACKET(VC4_PACKET_RHT_X_BOUNDARY, "RHT X boundary", NULL),
 460         VC4_DEFINE_PACKET(VC4_PACKET_DEPTH_OFFSET, "Depth Offset", NULL),
 461         VC4_DEFINE_PACKET(VC4_PACKET_CLIP_WINDOW, "Clip Window", NULL),
 462         VC4_DEFINE_PACKET(VC4_PACKET_VIEWPORT_OFFSET, "Viewport Offset", NULL),
 463         VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_XY_SCALING, "Clipper XY Scaling", NULL),
 464         /* Note: The docs say this was also 105, but it was 106 in the
 465          * initial userland code drop.
 466          */
 467         VC4_DEFINE_PACKET(VC4_PACKET_CLIPPER_Z_SCALING, "Clipper Z Scale and Offset", NULL),
 468
 469         VC4_DEFINE_PACKET(VC4_PACKET_TILE_BINNING_MODE_CONFIG, "tile binning configuration", validate_tile_binning_config),
 470
 471         VC4_DEFINE_PACKET(VC4_PACKET_GEM_HANDLES, "GEM handles", validate_gem_handles),
 472 };
 473
 474 int
 475 vc4_validate_bin_cl(struct drm_device *dev,
 476                     void *validated,
 477                     void *unvalidated,
 478                     struct vc4_exec_info *exec)
 479 {
 480         uint32_t len = exec->args->bin_cl_size;
 481         uint32_t dst_offset = 0;
 482         uint32_t src_offset = 0;
 483
 484         while (src_offset < len) {
 485                 void *dst_pkt = validated + dst_offset;
 486                 void *src_pkt = unvalidated + src_offset;
 487                 u8 cmd = *(uint8_t *)src_pkt;
 488                 const struct cmd_info *info;
 489
 490                 if (cmd > ARRAY_SIZE(cmd_info)) {
 491                         DRM_ERROR("0x%08x: packet %d out of bounds\n",
 492                                   src_offset, cmd);
 493                         return -EINVAL;
 494                 }
 495
 496                 info = &cmd_info[cmd];
 497                 if (!info->name) {
 498                         DRM_ERROR("0x%08x: packet %d invalid\n",
 499                                   src_offset, cmd);
 500                         return -EINVAL;
 501                 }
 502
 503 #if 0
 504                 DRM_INFO("0x%08x: packet %d (%s) size %d processing...\n",
 505                          src_offset, cmd, info->name, info->len);
 506 #endif
 507
 508                 if (src_offset + info->len > len) {
 509                         DRM_ERROR("0x%08x: packet %d (%s) length 0x%08x "
 510                                   "exceeds bounds (0x%08x)\n",
 511                                   src_offset, cmd, info->name, info->len,
 512                                   src_offset + len);
 513                         return -EINVAL;
 514                 }
 515
 516                 if (cmd != VC4_PACKET_GEM_HANDLES)
 517                         memcpy(dst_pkt, src_pkt, info->len);
 518
 519                 if (info->func && info->func(exec,
 520                                              dst_pkt + 1,
 521                                              src_pkt + 1)) {
 522                         DRM_ERROR("0x%08x: packet %d (%s) failed to "
 523                                   "validate\n",
 524                                   src_offset, cmd, info->name);
 525                         return -EINVAL;
 526                 }
 527
 528                 src_offset += info->len;
 529                 /* GEM handle loading doesn't produce HW packets. */
 530                 if (cmd != VC4_PACKET_GEM_HANDLES)
 531                         dst_offset += info->len;
 532
 533                 /* When the CL hits halt, it'll stop reading anything else. */
 534                 if (cmd == VC4_PACKET_HALT)
 535                         break;
 536         }
 537
 538         exec->ct0ea = exec->ct0ca + dst_offset;
 539
 540         if (!exec->found_start_tile_binning_packet) {
 541                 DRM_ERROR("Bin CL missing VC4_PACKET_START_TILE_BINNING\n");
 542                 return -EINVAL;
 543         }
 544
 545         /* The bin CL must be ended with INCREMENT_SEMAPHORE and FLUSH.  The
 546          * semaphore is used to trigger the render CL to start up, and the
 547          * FLUSH is what caps the bin lists with
 548          * VC4_PACKET_RETURN_FROM_SUB_LIST (so they jump back to the main
 549          * render CL when they get called to) and actually triggers the queued
 550          * semaphore increment.
 551          */
 552         if (!exec->found_increment_semaphore_packet || !exec->found_flush) {
 553                 DRM_ERROR("Bin CL missing VC4_PACKET_INCREMENT_SEMAPHORE + "
 554                           "VC4_PACKET_FLUSH\n");
 555                 return -EINVAL;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static bool
 562 reloc_tex(struct vc4_exec_info *exec,
 563           void *uniform_data_u,
 564           struct vc4_texture_sample_info *sample,
 565           uint32_t texture_handle_index)
 566
 567 {
 568         struct drm_gem_cma_object *tex;
 569         uint32_t p0 = *(uint32_t *)(uniform_data_u + sample->p_offset[0]);
 570         uint32_t p1 = *(uint32_t *)(uniform_data_u + sample->p_offset[1]);
 571         uint32_t p2 = (sample->p_offset[2] != ~0 ?
 572                        *(uint32_t *)(uniform_data_u + sample->p_offset[2]) : 0);
 573         uint32_t p3 = (sample->p_offset[3] != ~0 ?
 574                        *(uint32_t *)(uniform_data_u + sample->p_offset[3]) : 0);
 575         uint32_t *validated_p0 = exec->uniforms_v + sample->p_offset[0];
 576         uint32_t offset = p0 & VC4_TEX_P0_OFFSET_MASK;
 577         uint32_t miplevels = VC4_GET_FIELD(p0, VC4_TEX_P0_MIPLVLS);
 578         uint32_t width = VC4_GET_FIELD(p1, VC4_TEX_P1_WIDTH);
 579         uint32_t height = VC4_GET_FIELD(p1, VC4_TEX_P1_HEIGHT);
 580         uint32_t cpp, tiling_format, utile_w, utile_h;
 581         uint32_t i;
 582         uint32_t cube_map_stride = 0;
 583         enum vc4_texture_data_type type;
 584
 585         tex = vc4_use_bo(exec, texture_handle_index);
 586         if (!tex)
 587                 return false;
 588
 589         if (sample->is_direct) {
 590                 uint32_t remaining_size = tex->base.size - p0;
 591                 if (p0 > tex->base.size - 4) {
 592                         DRM_ERROR("UBO offset greater than UBO size\n");
 593                         goto fail;
 594                 }
 595                 if (p1 > remaining_size - 4) {
 596                         DRM_ERROR("UBO clamp would allow reads outside of UBO\n");
 597                         goto fail;
 598                 }
 599                 *validated_p0 = tex->paddr + p0;
 600                 return true;
 601         }
 602
 603         if (width == 0)
 604                 width = 2048;
 605         if (height == 0)
 606                 height = 2048;
 607
 608         if (p0 & VC4_TEX_P0_CMMODE_MASK) {
 609                 if (VC4_GET_FIELD(p2, VC4_TEX_P2_PTYPE) ==
 610                     VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE)
 611                         cube_map_stride = p2 & VC4_TEX_P2_CMST_MASK;
 612                 if (VC4_GET_FIELD(p3, VC4_TEX_P2_PTYPE) ==
 613                     VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE) {
 614                         if (cube_map_stride) {
 615                                 DRM_ERROR("Cube map stride set twice\n");
 616                                 goto fail;
 617                         }
 618
 619                         cube_map_stride = p3 & VC4_TEX_P2_CMST_MASK;
 620                 }
 621                 if (!cube_map_stride) {
 622                         DRM_ERROR("Cube map stride not set\n");
 623                         goto fail;
 624                 }
 625         }
 626
 627         type = (VC4_GET_FIELD(p0, VC4_TEX_P0_TYPE) |
 628                 (VC4_GET_FIELD(p1, VC4_TEX_P1_TYPE4) << 4));
 629
 630         switch (type) {
 631         case VC4_TEXTURE_TYPE_RGBA8888:
 632         case VC4_TEXTURE_TYPE_RGBX8888:
 633         case VC4_TEXTURE_TYPE_RGBA32R:
 634                 cpp = 4;
 635                 break;
 636         case VC4_TEXTURE_TYPE_RGBA4444:
 637         case VC4_TEXTURE_TYPE_RGBA5551:
 638         case VC4_TEXTURE_TYPE_RGB565:
 639         case VC4_TEXTURE_TYPE_LUMALPHA:
 640         case VC4_TEXTURE_TYPE_S16F:
 641         case VC4_TEXTURE_TYPE_S16:
 642                 cpp = 2;
 643                 break;
 644         case VC4_TEXTURE_TYPE_LUMINANCE:
 645         case VC4_TEXTURE_TYPE_ALPHA:
 646         case VC4_TEXTURE_TYPE_S8:
 647                 cpp = 1;
 648                 break;
 649         case VC4_TEXTURE_TYPE_ETC1:
 650         case VC4_TEXTURE_TYPE_BW1:
 651         case VC4_TEXTURE_TYPE_A4:
 652         case VC4_TEXTURE_TYPE_A1:
 653         case VC4_TEXTURE_TYPE_RGBA64:
 654         case VC4_TEXTURE_TYPE_YUV422R:
 655         default:
 656                 DRM_ERROR("Texture format %d unsupported\n", type);
 657                 goto fail;
 658         }
 659         utile_w = utile_width(cpp);
 660         utile_h = utile_height(cpp);
 661
 662         if (type == VC4_TEXTURE_TYPE_RGBA32R) {
 663                 tiling_format = VC4_TILING_FORMAT_LINEAR;
 664         } else {
 665                 if (size_is_lt(width, height, cpp))
 666                         tiling_format = VC4_TILING_FORMAT_LT;
 667                 else
 668                         tiling_format = VC4_TILING_FORMAT_T;
 669         }
 670
 671         if (!vc4_check_tex_size(exec, tex, offset + cube_map_stride * 5,
 672                                 tiling_format, width, height, cpp)) {
 673                 goto fail;
 674         }
 675
 676         /* The mipmap levels are stored before the base of the texture.  Make
 677          * sure there is actually space in the BO.
 678          */
 679         for (i = 1; i <= miplevels; i++) {
 680                 uint32_t level_width = max(width >> i, 1u);
 681                 uint32_t level_height = max(height >> i, 1u);
 682                 uint32_t aligned_width, aligned_height;
 683                 uint32_t level_size;
 684
 685                 /* Once the levels get small enough, they drop from T to LT. */
 686                 if (tiling_format == VC4_TILING_FORMAT_T &&
 687                     size_is_lt(level_width, level_height, cpp)) {
 688                         tiling_format = VC4_TILING_FORMAT_LT;
 689                 }
 690
 691                 switch (tiling_format) {
 692                 case VC4_TILING_FORMAT_T:
 693                         aligned_width = round_up(level_width, utile_w * 8);
 694                         aligned_height = round_up(level_height, utile_h * 8);
 695                         break;
 696                 case VC4_TILING_FORMAT_LT:
 697                         aligned_width = round_up(level_width, utile_w);
 698                         aligned_height = round_up(level_height, utile_h);
 699                         break;
 700                 default:
 701                         aligned_width = round_up(level_width, utile_w);
 702                         aligned_height = level_height;
 703                         break;
 704                 }
 705
 706                 level_size = aligned_width * cpp * aligned_height;
 707
 708                 if (offset < level_size) {
 709                         DRM_ERROR("Level %d (%dx%d -> %dx%d) size %db "
 710                                   "overflowed buffer bounds (offset %d)\n",
 711                                   i, level_width, level_height,
 712                                   aligned_width, aligned_height,
 713                                   level_size, offset);
 714                         goto fail;
 715                 }
 716
 717                 offset -= level_size;
 718         }
 719
 720         *validated_p0 = tex->paddr + p0;
 721
 722         return true;
 723  fail:
 724         DRM_INFO("Texture p0 at %d: 0x%08x\n", sample->p_offset[0], p0);
 725         DRM_INFO("Texture p1 at %d: 0x%08x\n", sample->p_offset[1], p1);
 726         DRM_INFO("Texture p2 at %d: 0x%08x\n", sample->p_offset[2], p2);
 727         DRM_INFO("Texture p3 at %d: 0x%08x\n", sample->p_offset[3], p3);
 728         return false;
 729 }
 730
 731 static int
 732 validate_gl_shader_rec(struct drm_device *dev,
 733                        struct vc4_exec_info *exec,
 734                        struct vc4_shader_state *state)
 735 {
 736         uint32_t *src_handles;
 737         void *pkt_u, *pkt_v;
 738         static const uint32_t shader_reloc_offsets[] = {
 739                 4, /* fs */
 740                 16, /* vs */
 741                 28, /* cs */
 742         };
 743         uint32_t shader_reloc_count = ARRAY_SIZE(shader_reloc_offsets);
 744         struct drm_gem_cma_object *bo[shader_reloc_count + 8];
 745         uint32_t nr_attributes, nr_relocs, packet_size;
 746         int i;
 747
 748         nr_attributes = state->addr & 0x7;
 749         if (nr_attributes == 0)
 750                 nr_attributes = 8;
 751         packet_size = gl_shader_rec_size(state->addr);
 752
 753         nr_relocs = ARRAY_SIZE(shader_reloc_offsets) + nr_attributes;
 754         if (nr_relocs * 4 > exec->shader_rec_size) {
 755                 DRM_ERROR("overflowed shader recs reading %d handles "
 756                           "from %d bytes left\n",
 757                           nr_relocs, exec->shader_rec_size);
 758                 return -EINVAL;
 759         }
 760         src_handles = exec->shader_rec_u;
 761         exec->shader_rec_u += nr_relocs * 4;
 762         exec->shader_rec_size -= nr_relocs * 4;
 763
 764         if (packet_size > exec->shader_rec_size) {
 765                 DRM_ERROR("overflowed shader recs copying %db packet "
 766                           "from %d bytes left\n",
 767                           packet_size, exec->shader_rec_size);
 768                 return -EINVAL;
 769         }
 770         pkt_u = exec->shader_rec_u;
 771         pkt_v = exec->shader_rec_v;
 772         memcpy(pkt_v, pkt_u, packet_size);
 773         exec->shader_rec_u += packet_size;
 774         /* Shader recs have to be aligned to 16 bytes (due to the attribute
 775          * flags being in the low bytes), so round the next validated shader
 776          * rec address up.  This should be safe, since we've got so many
 777          * relocations in a shader rec packet.
 778          */
 779         BUG_ON(roundup(packet_size, 16) - packet_size > nr_relocs * 4);
 780         exec->shader_rec_v += roundup(packet_size, 16);
 781         exec->shader_rec_size -= packet_size;
 782
 783         for (i = 0; i < shader_reloc_count; i++) {
 784                 if (src_handles[i] > exec->bo_count) {
 785                         DRM_ERROR("Shader handle %d too big\n", src_handles[i]);
 786                         return false;
 787                 }
 788
 789                 bo[i] = exec->bo[src_handles[i]];
 790                 if (!bo[i])
 791                         return false;
 792         }
 793         for (i = shader_reloc_count; i < nr_relocs; i++) {
 794                 bo[i] = vc4_use_bo(exec, src_handles[i]);
 795                 if (!bo[i])
 796                         return false;
 797         }
 798
 799         for (i = 0; i < shader_reloc_count; i++) {
 800                 struct vc4_validated_shader_info *validated_shader;
 801                 uint32_t o = shader_reloc_offsets[i];
 802                 uint32_t src_offset = *(uint32_t *)(pkt_u + o);
 803                 uint32_t *texture_handles_u;
 804                 void *uniform_data_u;
 805                 uint32_t tex;
 806
 807                 *(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset;
 808
 809                 if (src_offset != 0) {
 810                         DRM_ERROR("Shaders must be at offset 0 of "
 811                                   "the BO.\n");
 812                         return -EINVAL;
 813                 }
 814
 815                 validated_shader = to_vc4_bo(&bo[i]->base)->validated_shader;
 816                 if (!validated_shader)
 817                         return -EINVAL;
 818
 819                 if (validated_shader->uniforms_src_size >
 820                     exec->uniforms_size) {
 821                         DRM_ERROR("Uniforms src buffer overflow\n");
 822                         return -EINVAL;
 823                 }
 824
 825                 texture_handles_u = exec->uniforms_u;
 826                 uniform_data_u = (texture_handles_u +
 827                                   validated_shader->num_texture_samples);
 828
 829                 memcpy(exec->uniforms_v, uniform_data_u,
 830                        validated_shader->uniforms_size);
 831
 832                 for (tex = 0;
 833                      tex < validated_shader->num_texture_samples;
 834                      tex++) {
 835                         if (!reloc_tex(exec,
 836                                        uniform_data_u,
 837                                        &validated_shader->texture_samples[tex],
 838                                        texture_handles_u[tex])) {
 839                                 return -EINVAL;
 840                         }
 841                 }
 842
 843                 *(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p;
 844
 845                 exec->uniforms_u += validated_shader->uniforms_src_size;
 846                 exec->uniforms_v += validated_shader->uniforms_size;
 847                 exec->uniforms_p += validated_shader->uniforms_size;
 848         }
 849
 850         for (i = 0; i < nr_attributes; i++) {
 851                 struct drm_gem_cma_object *vbo =
 852                         bo[ARRAY_SIZE(shader_reloc_offsets) + i];
 853                 uint32_t o = 36 + i * 8;
 854                 uint32_t offset = *(uint32_t *)(pkt_u + o + 0);
 855                 uint32_t attr_size = *(uint8_t *)(pkt_u + o + 4) + 1;
 856                 uint32_t stride = *(uint8_t *)(pkt_u + o + 5);
 857                 uint32_t max_index;
 858
 859                 if (state->addr & 0x8)
 860                         stride |= (*(uint32_t *)(pkt_u + 100 + i * 4)) & ~0xff;
 861
 862                 if (vbo->base.size < offset ||
 863                     vbo->base.size - offset < attr_size) {
 864                         DRM_ERROR("BO offset overflow (%d + %d > %d)\n",
 865                                   offset, attr_size, vbo->base.size);
 866                         return -EINVAL;
 867                 }
 868
 869                 if (stride != 0) {
 870                         max_index = ((vbo->base.size - offset - attr_size) /
 871                                      stride);
 872                         if (state->max_index > max_index) {
 873                                 DRM_ERROR("primitives use index %d out of supplied %d\n",
 874                                           state->max_index, max_index);
 875                                 return -EINVAL;
 876                         }
 877                 }
 878
 879                 *(uint32_t *)(pkt_v + o) = vbo->paddr + offset;
 880         }
 881
 882         return 0;
 883 }
 884
 885 int
 886 vc4_validate_shader_recs(struct drm_device *dev,
 887                          struct vc4_exec_info *exec)
 888 {
 889         uint32_t i;
 890         int ret = 0;
 891
 892         for (i = 0; i < exec->shader_state_count; i++) {
 893                 ret = validate_gl_shader_rec(dev, exec, &exec->shader_state[i]);
 894                 if (ret)
 895                         return ret;
 896         }
 897
 898         return ret;
 899 }