2 * Copyright © 2014 Broadcom
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5 * copy of this software and associated documentation files (the "Software"),
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11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * DOC: Shader validator for VC4.
27 * The VC4 has no IOMMU between it and system memory. So, a user with access
28 * to execute shaders could escalate privilege by overwriting system memory
29 * (using the VPM write address register in the general-purpose DMA mode) or
30 * reading system memory it shouldn't (reading it as a texture, or uniform
31 * data, or vertex data).
33 * This walks over a shader starting from some offset within a BO, ensuring
34 * that its accesses are appropriately bounded, and recording how many texture
35 * accesses are made and where so that we can do relocations for them in the
38 * The kernel API has shaders stored in user-mapped BOs. The BOs will be
39 * forcibly unmapped from the process before validation, and any cache of
40 * validated state will be flushed if the mapping is faulted back in.
42 * Storing the shaders in BOs means that the validation process will be slow
43 * due to uncached reads, but since shaders are long-lived and shader BOs are
44 * never actually modified, this shouldn't be a problem.
49 #include "vc4_qpu_defines.h"
51 struct vc4_shader_validation_state
{
52 struct vc4_texture_sample_info tmu_setup
[2];
53 int tmu_write_count
[2];
55 /* For registers that were last written to by a MIN instruction with
56 * one argument being a uniform, the address of the uniform.
59 * This is used for the validation of direct address memory reads.
61 uint32_t live_clamp_offsets
[32 + 32 + 4];
65 waddr_to_live_reg_index(uint32_t waddr
, bool is_b
)
72 } else if (waddr
<= QPU_W_ACC3
) {
74 return 64 + waddr
- QPU_W_ACC0
;
81 is_tmu_submit(uint32_t waddr
)
83 return (waddr
== QPU_W_TMU0_S
||
84 waddr
== QPU_W_TMU1_S
);
88 is_tmu_write(uint32_t waddr
)
90 return (waddr
>= QPU_W_TMU0_S
&&
91 waddr
<= QPU_W_TMU1_B
);
95 record_validated_texture_sample(struct vc4_validated_shader_info
*validated_shader
,
96 struct vc4_shader_validation_state
*validation_state
,
99 uint32_t s
= validated_shader
->num_texture_samples
;
101 struct vc4_texture_sample_info
*temp_samples
;
103 temp_samples
= krealloc(validated_shader
->texture_samples
,
104 (s
+ 1) * sizeof(*temp_samples
),
109 memcpy(&temp_samples
[s
],
110 &validation_state
->tmu_setup
[tmu
],
111 sizeof(*temp_samples
));
113 validated_shader
->num_texture_samples
= s
+ 1;
114 validated_shader
->texture_samples
= temp_samples
;
116 for (i
= 0; i
< 4; i
++)
117 validation_state
->tmu_setup
[tmu
].p_offset
[i
] = ~0;
123 check_tmu_write(uint64_t inst
,
124 struct vc4_validated_shader_info
*validated_shader
,
125 struct vc4_shader_validation_state
*validation_state
,
128 uint32_t waddr
= (is_mul
?
129 QPU_GET_FIELD(inst
, QPU_WADDR_MUL
) :
130 QPU_GET_FIELD(inst
, QPU_WADDR_ADD
));
131 uint32_t raddr_a
= QPU_GET_FIELD(inst
, QPU_RADDR_A
);
132 uint32_t raddr_b
= QPU_GET_FIELD(inst
, QPU_RADDR_B
);
133 int tmu
= waddr
> QPU_W_TMU0_B
;
134 bool submit
= is_tmu_submit(waddr
);
135 bool is_direct
= submit
&& validation_state
->tmu_write_count
[tmu
] == 0;
138 uint32_t add_a
= QPU_GET_FIELD(inst
, QPU_ADD_A
);
139 uint32_t add_b
= QPU_GET_FIELD(inst
, QPU_ADD_B
);
140 uint32_t clamp_offset
= ~0;
142 /* Make sure that this texture load is an add of the base
143 * address of the UBO to a clamped offset within the UBO.
146 QPU_GET_FIELD(inst
, QPU_OP_ADD
) != QPU_A_ADD
) {
147 DRM_ERROR("direct TMU load wasn't an add\n");
151 /* We assert that the the clamped address is the first
152 * argument, and the UBO base address is the second argument.
153 * This is arbitrary, but simpler than supporting flipping the
156 if (add_a
== QPU_MUX_A
) {
157 clamp_offset
= validation_state
->live_clamp_offsets
[raddr_a
];
158 } else if (add_a
== QPU_MUX_B
) {
159 clamp_offset
= validation_state
->live_clamp_offsets
[32 + raddr_b
];
160 } else if (add_a
<= QPU_MUX_R4
) {
161 clamp_offset
= validation_state
->live_clamp_offsets
[64 + add_a
];
164 if (clamp_offset
== ~0) {
165 DRM_ERROR("direct TMU load wasn't clamped\n");
169 /* Store the clamp value's offset in p1 (see reloc_tex() in
172 validation_state
->tmu_setup
[tmu
].p_offset
[1] =
175 if (!(add_b
== QPU_MUX_A
&& raddr_a
== QPU_R_UNIF
) &&
176 !(add_b
== QPU_MUX_B
&& raddr_b
== QPU_R_UNIF
)) {
177 DRM_ERROR("direct TMU load didn't add to a uniform\n");
181 validation_state
->tmu_setup
[tmu
].is_direct
= true;
183 if (raddr_a
== QPU_R_UNIF
|| raddr_b
== QPU_R_UNIF
) {
184 DRM_ERROR("uniform read in the same instruction as "
190 if (validation_state
->tmu_write_count
[tmu
] >= 4) {
191 DRM_ERROR("TMU%d got too many parameters before dispatch\n",
195 validation_state
->tmu_setup
[tmu
].p_offset
[validation_state
->tmu_write_count
[tmu
]] =
196 validated_shader
->uniforms_size
;
197 validation_state
->tmu_write_count
[tmu
]++;
198 /* Since direct uses a RADDR uniform reference, it will get counted in
199 * check_instruction_reads()
202 validated_shader
->uniforms_size
+= 4;
205 if (!record_validated_texture_sample(validated_shader
,
206 validation_state
, tmu
)) {
210 validation_state
->tmu_write_count
[tmu
] = 0;
217 check_register_write(uint64_t inst
,
218 struct vc4_validated_shader_info
*validated_shader
,
219 struct vc4_shader_validation_state
*validation_state
,
222 uint32_t waddr
= (is_mul
?
223 QPU_GET_FIELD(inst
, QPU_WADDR_MUL
) :
224 QPU_GET_FIELD(inst
, QPU_WADDR_ADD
));
225 bool is_b
= is_mul
!= ((inst
& QPU_WS
) != 0);
226 uint32_t live_reg_index
;
229 case QPU_W_UNIFORMS_ADDRESS
:
230 /* XXX: We'll probably need to support this for reladdr, but
231 * it's definitely a security-related one.
233 DRM_ERROR("uniforms address load unsupported\n");
236 case QPU_W_TLB_COLOR_MS
:
237 case QPU_W_TLB_COLOR_ALL
:
239 /* These only interact with the tile buffer, not main memory,
252 return check_tmu_write(inst
, validated_shader
, validation_state
,
256 case QPU_W_TMU_NOSWAP
:
257 case QPU_W_TLB_ALPHA_MASK
:
258 case QPU_W_MUTEX_RELEASE
:
259 /* XXX: I haven't thought about these, so don't support them
262 DRM_ERROR("Unsupported waddr %d\n", waddr
);
266 DRM_ERROR("General VPM DMA unsupported\n");
270 case QPU_W_VPMVCD_SETUP
:
271 /* We allow VPM setup in general, even including VPM DMA
272 * configuration setup, because the (unsafe) DMA can only be
273 * triggered by QPU_W_VPM_ADDR writes.
277 case QPU_W_TLB_STENCIL_SETUP
:
281 /* Clear out the live offset clamp tracking for the written register.
282 * If this particular instruction is setting up an offset clamp, it'll
283 * get tracked immediately after we return.
285 live_reg_index
= waddr_to_live_reg_index(waddr
, is_b
);
286 if (live_reg_index
!= ~0)
287 validation_state
->live_clamp_offsets
[live_reg_index
] = ~0;
293 track_live_clamps(uint64_t inst
,
294 struct vc4_validated_shader_info
*validated_shader
,
295 struct vc4_shader_validation_state
*validation_state
)
297 uint32_t waddr_add
= QPU_GET_FIELD(inst
, QPU_WADDR_ADD
);
298 uint32_t add_b
= QPU_GET_FIELD(inst
, QPU_ADD_B
);
299 uint32_t raddr_a
= QPU_GET_FIELD(inst
, QPU_RADDR_A
);
300 uint32_t raddr_b
= QPU_GET_FIELD(inst
, QPU_RADDR_B
);
301 bool is_b
= inst
& QPU_WS
;
302 uint32_t live_reg_index
;
304 if (QPU_GET_FIELD(inst
, QPU_OP_ADD
) != QPU_A_MIN
)
307 if (!(add_b
== QPU_MUX_A
&& raddr_a
== QPU_R_UNIF
) &&
308 !(add_b
== QPU_MUX_B
&& raddr_b
== QPU_R_UNIF
)) {
312 live_reg_index
= waddr_to_live_reg_index(waddr_add
, is_b
);
313 if (live_reg_index
!= ~0) {
314 validation_state
->live_clamp_offsets
[live_reg_index
] =
315 validated_shader
->uniforms_size
;
320 check_instruction_writes(uint64_t inst
,
321 struct vc4_validated_shader_info
*validated_shader
,
322 struct vc4_shader_validation_state
*validation_state
)
324 uint32_t waddr_add
= QPU_GET_FIELD(inst
, QPU_WADDR_ADD
);
325 uint32_t waddr_mul
= QPU_GET_FIELD(inst
, QPU_WADDR_MUL
);
328 if (is_tmu_write(waddr_add
) && is_tmu_write(waddr_mul
)) {
329 DRM_ERROR("ADD and MUL both set up textures\n");
333 ok
= (check_register_write(inst
, validated_shader
, validation_state
, false) &&
334 check_register_write(inst
, validated_shader
, validation_state
, true));
336 track_live_clamps(inst
, validated_shader
, validation_state
);
342 check_instruction_reads(uint64_t inst
,
343 struct vc4_validated_shader_info
*validated_shader
)
345 uint32_t raddr_a
= QPU_GET_FIELD(inst
, QPU_RADDR_A
);
346 uint32_t raddr_b
= QPU_GET_FIELD(inst
, QPU_RADDR_B
);
348 if (raddr_a
== QPU_R_UNIF
||
349 raddr_b
== QPU_R_UNIF
) {
350 /* This can't overflow the uint32_t, because we're reading 8
351 * bytes of instruction to increment by 4 here, so we'd
354 validated_shader
->uniforms_size
+= 4;
360 struct vc4_validated_shader_info
*
361 vc4_validate_shader(struct drm_gem_cma_object
*shader_obj
,
362 uint32_t start_offset
)
364 bool found_shader_end
= false;
365 int shader_end_ip
= 0;
368 struct vc4_validated_shader_info
*validated_shader
;
369 struct vc4_shader_validation_state validation_state
;
372 memset(&validation_state
, 0, sizeof(validation_state
));
374 for (i
= 0; i
< 8; i
++)
375 validation_state
.tmu_setup
[i
/ 4].p_offset
[i
% 4] = ~0;
376 for (i
= 0; i
< ARRAY_SIZE(validation_state
.live_clamp_offsets
); i
++)
377 validation_state
.live_clamp_offsets
[i
] = ~0;
379 if (start_offset
+ sizeof(uint64_t) > shader_obj
->base
.size
) {
380 DRM_ERROR("shader starting at %d outside of BO sized %d\n",
382 shader_obj
->base
.size
);
385 shader
= shader_obj
->vaddr
+ start_offset
;
386 max_ip
= (shader_obj
->base
.size
- start_offset
) / sizeof(uint64_t);
388 validated_shader
= kcalloc(sizeof(*validated_shader
), 1, GFP_KERNEL
);
389 if (!validated_shader
)
392 for (ip
= 0; ip
< max_ip
; ip
++) {
393 uint64_t inst
= shader
[ip
];
394 uint32_t sig
= QPU_GET_FIELD(inst
, QPU_SIG
);
398 case QPU_SIG_WAIT_FOR_SCOREBOARD
:
399 case QPU_SIG_SCOREBOARD_UNLOCK
:
400 case QPU_SIG_COLOR_LOAD
:
401 case QPU_SIG_LOAD_TMU0
:
402 case QPU_SIG_LOAD_TMU1
:
403 case QPU_SIG_PROG_END
:
404 if (!check_instruction_writes(inst
, validated_shader
,
405 &validation_state
)) {
406 DRM_ERROR("Bad write at ip %d\n", ip
);
410 if (!check_instruction_reads(inst
, validated_shader
))
413 if (sig
== QPU_SIG_PROG_END
) {
414 found_shader_end
= true;
420 case QPU_SIG_LOAD_IMM
:
421 if (!check_instruction_writes(inst
, validated_shader
,
422 &validation_state
)) {
423 DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip
);
429 DRM_ERROR("Unsupported QPU signal %d at "
430 "instruction %d\n", sig
, ip
);
434 /* There are two delay slots after program end is signaled
435 * that are still executed, then we're finished.
437 if (found_shader_end
&& ip
== shader_end_ip
+ 2)
442 DRM_ERROR("shader starting at %d failed to terminate before "
443 "shader BO end at %d\n",
445 shader_obj
->base
.size
);
449 /* Again, no chance of integer overflow here because the worst case
450 * scenario is 8 bytes of uniforms plus handles per 8-byte
453 validated_shader
->uniforms_src_size
=
454 (validated_shader
->uniforms_size
+
455 4 * validated_shader
->num_texture_samples
);
457 return validated_shader
;
460 kfree(validated_shader
);