src/gallium/drivers/vc4/kernel/vc4_validate_shaders.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Shader validator for VC4.
  26  *
  27  * The VC4 has no IOMMU between it and system memory, so a user with
  28  * access to execute shaders could escalate privilege by overwriting
  29  * system memory (using the VPM write address register in the
  30  * general-purpose DMA mode) or reading system memory it shouldn't
  31  * (reading it as a texture, or uniform data, or vertex data).
  32  *
  33  * This walks over a shader BO, ensuring that its accesses are
  34  * appropriately bounded, and recording how many texture accesses are
  35  * made and where so that we can do relocations for them in the
  36  * uniform stream.
  37  */
  38
  39 #include "vc4_drv.h"
  40 #include "vc4_qpu.h"
  41 #include "vc4_qpu_defines.h"
  42
  43 struct vc4_shader_validation_state {
  44         /* Current IP being validated. */
  45         uint32_t ip;
  46
  47         /* IP at the end of the BO, do not read shader[max_ip] */
  48         uint32_t max_ip;
  49
  50         uint64_t *shader;
  51
  52         struct vc4_texture_sample_info tmu_setup[2];
  53         int tmu_write_count[2];
  54
  55         /* For registers that were last written to by a MIN instruction with
  56          * one argument being a uniform, the address of the uniform.
  57          * Otherwise, ~0.
  58          *
  59          * This is used for the validation of direct address memory reads.
  60          */
  61         uint32_t live_min_clamp_offsets[32 + 32 + 4];
  62         bool live_max_clamp_regs[32 + 32 + 4];
  63 };
  64
  65 static uint32_t
  66 waddr_to_live_reg_index(uint32_t waddr, bool is_b)
  67 {
  68         if (waddr < 32) {
  69                 if (is_b)
  70                         return 32 + waddr;
  71                 else
  72                         return waddr;
  73         } else if (waddr <= QPU_W_ACC3) {
  74                 return 64 + waddr - QPU_W_ACC0;
  75         } else {
  76                 return ~0;
  77         }
  78 }
  79
  80 static uint32_t
  81 raddr_add_a_to_live_reg_index(uint64_t inst)
  82 {
  83         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
  84         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
  85         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
  86         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
  87
  88         if (add_a == QPU_MUX_A)
  89                 return raddr_a;
  90         else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM)
  91                 return 32 + raddr_b;
  92         else if (add_a <= QPU_MUX_R3)
  93                 return 64 + add_a;
  94         else
  95                 return ~0;
  96 }
  97
  98 static bool
  99 is_tmu_submit(uint32_t waddr)
 100 {
 101         return (waddr == QPU_W_TMU0_S ||
 102                 waddr == QPU_W_TMU1_S);
 103 }
 104
 105 static bool
 106 is_tmu_write(uint32_t waddr)
 107 {
 108         return (waddr >= QPU_W_TMU0_S &&
 109                 waddr <= QPU_W_TMU1_B);
 110 }
 111
 112 static bool
 113 record_texture_sample(struct vc4_validated_shader_info *validated_shader,
 114                       struct vc4_shader_validation_state *validation_state,
 115                       int tmu)
 116 {
 117         uint32_t s = validated_shader->num_texture_samples;
 118         int i;
 119         struct vc4_texture_sample_info *temp_samples;
 120
 121         temp_samples = krealloc(validated_shader->texture_samples,
 122                                 (s + 1) * sizeof(*temp_samples),
 123                                 GFP_KERNEL);
 124         if (!temp_samples)
 125                 return false;
 126
 127         memcpy(&temp_samples[s],
 128                &validation_state->tmu_setup[tmu],
 129                sizeof(*temp_samples));
 130
 131         validated_shader->num_texture_samples = s + 1;
 132         validated_shader->texture_samples = temp_samples;
 133
 134         for (i = 0; i < 4; i++)
 135                 validation_state->tmu_setup[tmu].p_offset[i] = ~0;
 136
 137         return true;
 138 }
 139
 140 static bool
 141 check_tmu_write(struct vc4_validated_shader_info *validated_shader,
 142                 struct vc4_shader_validation_state *validation_state,
 143                 bool is_mul)
 144 {
 145         uint64_t inst = validation_state->shader[validation_state->ip];
 146         uint32_t waddr = (is_mul ?
 147                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
 148                           QPU_GET_FIELD(inst, QPU_WADDR_ADD));
 149         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 150         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 151         int tmu = waddr > QPU_W_TMU0_B;
 152         bool submit = is_tmu_submit(waddr);
 153         bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0;
 154         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 155
 156         if (is_direct) {
 157                 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 158                 uint32_t clamp_reg, clamp_offset;
 159
 160                 if (sig == QPU_SIG_SMALL_IMM) {
 161                         DRM_ERROR("direct TMU read used small immediate\n");
 162                         return false;
 163                 }
 164
 165                 /* Make sure that this texture load is an add of the base
 166                  * address of the UBO to a clamped offset within the UBO.
 167                  */
 168                 if (is_mul ||
 169                     QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
 170                         DRM_ERROR("direct TMU load wasn't an add\n");
 171                         return false;
 172                 }
 173
 174                 /* We assert that the clamped address is the first
 175                  * argument, and the UBO base address is the second argument.
 176                  * This is arbitrary, but simpler than supporting flipping the
 177                  * two either way.
 178                  */
 179                 clamp_reg = raddr_add_a_to_live_reg_index(inst);
 180                 if (clamp_reg == ~0) {
 181                         DRM_ERROR("direct TMU load wasn't clamped\n");
 182                         return false;
 183                 }
 184
 185                 clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg];
 186                 if (clamp_offset == ~0) {
 187                         DRM_ERROR("direct TMU load wasn't clamped\n");
 188                         return false;
 189                 }
 190
 191                 /* Store the clamp value's offset in p1 (see reloc_tex() in
 192                  * vc4_validate.c).
 193                  */
 194                 validation_state->tmu_setup[tmu].p_offset[1] =
 195                         clamp_offset;
 196
 197                 if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
 198                     !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
 199                         DRM_ERROR("direct TMU load didn't add to a uniform\n");
 200                         return false;
 201                 }
 202
 203                 validation_state->tmu_setup[tmu].is_direct = true;
 204         } else {
 205                 if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM &&
 206                                               raddr_b == QPU_R_UNIF)) {
 207                         DRM_ERROR("uniform read in the same instruction as "
 208                                   "texture setup.\n");
 209                         return false;
 210                 }
 211         }
 212
 213         if (validation_state->tmu_write_count[tmu] >= 4) {
 214                 DRM_ERROR("TMU%d got too many parameters before dispatch\n",
 215                           tmu);
 216                 return false;
 217         }
 218         validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] =
 219                 validated_shader->uniforms_size;
 220         validation_state->tmu_write_count[tmu]++;
 221         /* Since direct uses a RADDR uniform reference, it will get counted in
 222          * check_instruction_reads()
 223          */
 224         if (!is_direct)
 225                 validated_shader->uniforms_size += 4;
 226
 227         if (submit) {
 228                 if (!record_texture_sample(validated_shader,
 229                                            validation_state, tmu)) {
 230                         return false;
 231                 }
 232
 233                 validation_state->tmu_write_count[tmu] = 0;
 234         }
 235
 236         return true;
 237 }
 238
 239 static bool
 240 check_reg_write(struct vc4_validated_shader_info *validated_shader,
 241                 struct vc4_shader_validation_state *validation_state,
 242                 bool is_mul)
 243 {
 244         uint64_t inst = validation_state->shader[validation_state->ip];
 245         uint32_t waddr = (is_mul ?
 246                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
 247                           QPU_GET_FIELD(inst, QPU_WADDR_ADD));
 248
 249         switch (waddr) {
 250         case QPU_W_UNIFORMS_ADDRESS:
 251                 /* XXX: We'll probably need to support this for reladdr, but
 252                  * it's definitely a security-related one.
 253                  */
 254                 DRM_ERROR("uniforms address load unsupported\n");
 255                 return false;
 256
 257         case QPU_W_TLB_COLOR_MS:
 258         case QPU_W_TLB_COLOR_ALL:
 259         case QPU_W_TLB_Z:
 260                 /* These only interact with the tile buffer, not main memory,
 261                  * so they're safe.
 262                  */
 263                 return true;
 264
 265         case QPU_W_TMU0_S:
 266         case QPU_W_TMU0_T:
 267         case QPU_W_TMU0_R:
 268         case QPU_W_TMU0_B:
 269         case QPU_W_TMU1_S:
 270         case QPU_W_TMU1_T:
 271         case QPU_W_TMU1_R:
 272         case QPU_W_TMU1_B:
 273                 return check_tmu_write(validated_shader, validation_state,
 274                                        is_mul);
 275
 276         case QPU_W_HOST_INT:
 277         case QPU_W_TMU_NOSWAP:
 278         case QPU_W_TLB_ALPHA_MASK:
 279         case QPU_W_MUTEX_RELEASE:
 280                 /* XXX: I haven't thought about these, so don't support them
 281                  * for now.
 282                  */
 283                 DRM_ERROR("Unsupported waddr %d\n", waddr);
 284                 return false;
 285
 286         case QPU_W_VPM_ADDR:
 287                 DRM_ERROR("General VPM DMA unsupported\n");
 288                 return false;
 289
 290         case QPU_W_VPM:
 291         case QPU_W_VPMVCD_SETUP:
 292                 /* We allow VPM setup in general, even including VPM DMA
 293                  * configuration setup, because the (unsafe) DMA can only be
 294                  * triggered by QPU_W_VPM_ADDR writes.
 295                  */
 296                 return true;
 297
 298         case QPU_W_TLB_STENCIL_SETUP:
 299                 return true;
 300         }
 301
 302         return true;
 303 }
 304
 305 static void
 306 track_live_clamps(struct vc4_validated_shader_info *validated_shader,
 307                   struct vc4_shader_validation_state *validation_state)
 308 {
 309         uint64_t inst = validation_state->shader[validation_state->ip];
 310         uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
 311         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 312         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 313         uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
 314         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
 315         uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 316         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 317         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 318         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 319         bool ws = inst & QPU_WS;
 320         uint32_t lri_add_a, lri_add, lri_mul;
 321         bool add_a_is_min_0;
 322
 323         /* Check whether OP_ADD's A argumennt comes from a live MAX(x, 0),
 324          * before we clear previous live state.
 325          */
 326         lri_add_a = raddr_add_a_to_live_reg_index(inst);
 327         add_a_is_min_0 = (lri_add_a != ~0 &&
 328                           validation_state->live_max_clamp_regs[lri_add_a]);
 329
 330         /* Clear live state for registers written by our instruction. */
 331         lri_add = waddr_to_live_reg_index(waddr_add, ws);
 332         lri_mul = waddr_to_live_reg_index(waddr_mul, !ws);
 333         if (lri_mul != ~0) {
 334                 validation_state->live_max_clamp_regs[lri_mul] = false;
 335                 validation_state->live_min_clamp_offsets[lri_mul] = ~0;
 336         }
 337         if (lri_add != ~0) {
 338                 validation_state->live_max_clamp_regs[lri_add] = false;
 339                 validation_state->live_min_clamp_offsets[lri_add] = ~0;
 340         } else {
 341                 /* Nothing further to do for live tracking, since only ADDs
 342                  * generate new live clamp registers.
 343                  */
 344                 return;
 345         }
 346
 347         /* Now, handle remaining live clamp tracking for the ADD operation. */
 348
 349         if (cond_add != QPU_COND_ALWAYS)
 350                 return;
 351
 352         if (op_add == QPU_A_MAX) {
 353                 /* Track live clamps of a value to a minimum of 0 (in either
 354                  * arg).
 355                  */
 356                 if (sig != QPU_SIG_SMALL_IMM || raddr_b != 0 ||
 357                     (add_a != QPU_MUX_B && add_b != QPU_MUX_B)) {
 358                         return;
 359                 }
 360
 361                 validation_state->live_max_clamp_regs[lri_add] = true;
 362         } else if (op_add == QPU_A_MIN) {
 363                 /* Track live clamps of a value clamped to a minimum of 0 and
 364                  * a maximum of some uniform's offset.
 365                  */
 366                 if (!add_a_is_min_0)
 367                         return;
 368
 369                 if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
 370                     !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF &&
 371                       sig != QPU_SIG_SMALL_IMM)) {
 372                         return;
 373                 }
 374
 375                 validation_state->live_min_clamp_offsets[lri_add] =
 376                         validated_shader->uniforms_size;
 377         }
 378 }
 379
 380 static bool
 381 check_instruction_writes(struct vc4_validated_shader_info *validated_shader,
 382                          struct vc4_shader_validation_state *validation_state)
 383 {
 384         uint64_t inst = validation_state->shader[validation_state->ip];
 385         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 386         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 387         bool ok;
 388
 389         if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) {
 390                 DRM_ERROR("ADD and MUL both set up textures\n");
 391                 return false;
 392         }
 393
 394         ok = (check_reg_write(validated_shader, validation_state, false) &&
 395               check_reg_write(validated_shader, validation_state, true));
 396
 397         track_live_clamps(validated_shader, validation_state);
 398
 399         return ok;
 400 }
 401
 402 static bool
 403 check_instruction_reads(uint64_t inst,
 404                         struct vc4_validated_shader_info *validated_shader)
 405 {
 406         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 407         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 408         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 409
 410         if (raddr_a == QPU_R_UNIF ||
 411             (raddr_b == QPU_R_UNIF && sig != QPU_SIG_SMALL_IMM)) {
 412                 /* This can't overflow the uint32_t, because we're reading 8
 413                  * bytes of instruction to increment by 4 here, so we'd
 414                  * already be OOM.
 415                  */
 416                 validated_shader->uniforms_size += 4;
 417         }
 418
 419         return true;
 420 }
 421
 422 struct vc4_validated_shader_info *
 423 vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
 424 {
 425         bool found_shader_end = false;
 426         int shader_end_ip = 0;
 427         uint32_t ip;
 428         struct vc4_validated_shader_info *validated_shader;
 429         struct vc4_shader_validation_state validation_state;
 430         int i;
 431
 432         memset(&validation_state, 0, sizeof(validation_state));
 433         validation_state.shader = shader_obj->vaddr;
 434         validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);
 435
 436         for (i = 0; i < 8; i++)
 437                 validation_state.tmu_setup[i / 4].p_offset[i % 4] = ~0;
 438         for (i = 0; i < ARRAY_SIZE(validation_state.live_min_clamp_offsets); i++)
 439                 validation_state.live_min_clamp_offsets[i] = ~0;
 440
 441         validated_shader = kcalloc(1, sizeof(*validated_shader), GFP_KERNEL);
 442         if (!validated_shader)
 443                 return NULL;
 444
 445         for (ip = 0; ip < validation_state.max_ip; ip++) {
 446                 uint64_t inst = validation_state.shader[ip];
 447                 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 448
 449                 validation_state.ip = ip;
 450
 451                 switch (sig) {
 452                 case QPU_SIG_NONE:
 453                 case QPU_SIG_WAIT_FOR_SCOREBOARD:
 454                 case QPU_SIG_SCOREBOARD_UNLOCK:
 455                 case QPU_SIG_COLOR_LOAD:
 456                 case QPU_SIG_LOAD_TMU0:
 457                 case QPU_SIG_LOAD_TMU1:
 458                 case QPU_SIG_PROG_END:
 459                 case QPU_SIG_SMALL_IMM:
 460                         if (!check_instruction_writes(validated_shader,
 461                                                       &validation_state)) {
 462                                 DRM_ERROR("Bad write at ip %d\n", ip);
 463                                 goto fail;
 464                         }
 465
 466                         if (!check_instruction_reads(inst, validated_shader))
 467                                 goto fail;
 468
 469                         if (sig == QPU_SIG_PROG_END) {
 470                                 found_shader_end = true;
 471                                 shader_end_ip = ip;
 472                         }
 473
 474                         break;
 475
 476                 case QPU_SIG_LOAD_IMM:
 477                         if (!check_instruction_writes(validated_shader,
 478                                                       &validation_state)) {
 479                                 DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
 480                                 goto fail;
 481                         }
 482                         break;
 483
 484                 default:
 485                         DRM_ERROR("Unsupported QPU signal %d at "
 486                                   "instruction %d\n", sig, ip);
 487                         goto fail;
 488                 }
 489
 490                 /* There are two delay slots after program end is signaled
 491                  * that are still executed, then we're finished.
 492                  */
 493                 if (found_shader_end && ip == shader_end_ip + 2)
 494                         break;
 495         }
 496
 497         if (ip == validation_state.max_ip) {
 498                 DRM_ERROR("shader failed to terminate before "
 499                           "shader BO end at %zd\n",
 500                           shader_obj->base.size);
 501                 goto fail;
 502         }
 503
 504         /* Again, no chance of integer overflow here because the worst case
 505          * scenario is 8 bytes of uniforms plus handles per 8-byte
 506          * instruction.
 507          */
 508         validated_shader->uniforms_src_size =
 509                 (validated_shader->uniforms_size +
 510                  4 * validated_shader->num_texture_samples);
 511
 512         return validated_shader;
 513
 514 fail:
 515         if (validated_shader) {
 516                 kfree(validated_shader->texture_samples);
 517                 kfree(validated_shader);
 518         }
 519         return NULL;
 520 }