src/gallium/drivers/vc4/kernel/vc4_validate_shaders.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Shader validator for VC4.
  26  *
  27  * The VC4 has no IOMMU between it and system memory.  So, a user with access
  28  * to execute shaders could escalate privilege by overwriting system memory
  29  * (using the VPM write address register in the general-purpose DMA mode) or
  30  * reading system memory it shouldn't (reading it as a texture, or uniform
  31  * data, or vertex data).
  32  *
  33  * This walks over a shader starting from some offset within a BO, ensuring
  34  * that its accesses are appropriately bounded, and recording how many texture
  35  * accesses are made and where so that we can do relocations for them in the
  36  * uniform stream.
  37  *
  38  * The kernel API has shaders stored in user-mapped BOs.  The BOs will be
  39  * forcibly unmapped from the process before validation, and any cache of
  40  * validated state will be flushed if the mapping is faulted back in.
  41  *
  42  * Storing the shaders in BOs means that the validation process will be slow
  43  * due to uncached reads, but since shaders are long-lived and shader BOs are
  44  * never actually modified, this shouldn't be a problem.
  45  */
  46
  47 #include "vc4_drv.h"
  48 #include "vc4_qpu.h"
  49 #include "vc4_qpu_defines.h"
  50
  51 struct vc4_shader_validation_state {
  52         struct vc4_texture_sample_info tmu_setup[2];
  53         int tmu_write_count[2];
  54
  55         /* For registers that were last written to by a MIN instruction with
  56          * one argument being a uniform, the address of the uniform.
  57          * Otherwise, ~0.
  58          *
  59          * This is used for the validation of direct address memory reads.
  60          */
  61         uint32_t live_clamp_offsets[32 + 32 + 4];
  62 };
  63
  64 static uint32_t
  65 waddr_to_live_reg_index(uint32_t waddr, bool is_b)
  66 {
  67         if (waddr < 32) {
  68                 if (is_b)
  69                         return 32 + waddr;
  70                 else
  71                         return waddr;
  72         } else if (waddr <= QPU_W_ACC3) {
  73
  74                 return 64 + waddr - QPU_W_ACC0;
  75         } else {
  76                 return ~0;
  77         }
  78 }
  79
  80 static uint32_t
  81 raddr_add_a_to_live_reg_index(uint64_t inst)
  82 {
  83         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
  84         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
  85         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
  86
  87         if (add_a == QPU_MUX_A) {
  88                 return raddr_a;
  89         } else if (add_a == QPU_MUX_B) {
  90                 return 32 + raddr_b;
  91         } else if (add_a <= QPU_MUX_R4) {
  92                 return 64 + add_a;
  93         } else {
  94                 return ~0;
  95         }
  96 }
  97
  98 static bool
  99 is_tmu_submit(uint32_t waddr)
 100 {
 101         return (waddr == QPU_W_TMU0_S ||
 102                 waddr == QPU_W_TMU1_S);
 103 }
 104
 105 static bool
 106 is_tmu_write(uint32_t waddr)
 107 {
 108         return (waddr >= QPU_W_TMU0_S &&
 109                 waddr <= QPU_W_TMU1_B);
 110 }
 111
 112 static bool
 113 record_validated_texture_sample(struct vc4_validated_shader_info *validated_shader,
 114                                 struct vc4_shader_validation_state *validation_state,
 115                                 int tmu)
 116 {
 117         uint32_t s = validated_shader->num_texture_samples;
 118         int i;
 119         struct vc4_texture_sample_info *temp_samples;
 120
 121         temp_samples = krealloc(validated_shader->texture_samples,
 122                                 (s + 1) * sizeof(*temp_samples),
 123                                 GFP_KERNEL);
 124         if (!temp_samples)
 125                 return false;
 126
 127         memcpy(&temp_samples[s],
 128                &validation_state->tmu_setup[tmu],
 129                sizeof(*temp_samples));
 130
 131         validated_shader->num_texture_samples = s + 1;
 132         validated_shader->texture_samples = temp_samples;
 133
 134         for (i = 0; i < 4; i++)
 135                 validation_state->tmu_setup[tmu].p_offset[i] = ~0;
 136
 137         return true;
 138 }
 139
 140 static bool
 141 check_tmu_write(uint64_t inst,
 142                 struct vc4_validated_shader_info *validated_shader,
 143                 struct vc4_shader_validation_state *validation_state,
 144                 bool is_mul)
 145 {
 146         uint32_t waddr = (is_mul ?
 147                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
 148                           QPU_GET_FIELD(inst, QPU_WADDR_ADD));
 149         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 150         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 151         int tmu = waddr > QPU_W_TMU0_B;
 152         bool submit = is_tmu_submit(waddr);
 153         bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0;
 154         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 155
 156         if (is_direct) {
 157                 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 158                 uint32_t clamp_reg, clamp_offset;
 159
 160                 if (sig == QPU_SIG_SMALL_IMM) {
 161                         DRM_ERROR("direct TMU read used small immediate\n");
 162                         return false;
 163                 }
 164
 165                 /* Make sure that this texture load is an add of the base
 166                  * address of the UBO to a clamped offset within the UBO.
 167                  */
 168                 if (is_mul ||
 169                     QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
 170                         DRM_ERROR("direct TMU load wasn't an add\n");
 171                         return false;
 172                 }
 173
 174                 /* We assert that the the clamped address is the first
 175                  * argument, and the UBO base address is the second argument.
 176                  * This is arbitrary, but simpler than supporting flipping the
 177                  * two either way.
 178                  */
 179                 clamp_reg = raddr_add_a_to_live_reg_index(inst);
 180                 if (clamp_reg == ~0) {
 181                         DRM_ERROR("direct TMU load wasn't clamped\n");
 182                         return false;
 183                 }
 184
 185                 clamp_offset = validation_state->live_clamp_offsets[clamp_reg];
 186                 if (clamp_offset == ~0) {
 187                         DRM_ERROR("direct TMU load wasn't clamped\n");
 188                         return false;
 189                 }
 190
 191                 /* Store the clamp value's offset in p1 (see reloc_tex() in
 192                  * vc4_validate.c).
 193                  */
 194                 validation_state->tmu_setup[tmu].p_offset[1] =
 195                         clamp_offset;
 196
 197                 if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
 198                     !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
 199                         DRM_ERROR("direct TMU load didn't add to a uniform\n");
 200                         return false;
 201                 }
 202
 203                 validation_state->tmu_setup[tmu].is_direct = true;
 204         } else {
 205                 if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM &&
 206                                               raddr_b == QPU_R_UNIF)) {
 207                         DRM_ERROR("uniform read in the same instruction as "
 208                                   "texture setup.\n");
 209                         return false;
 210                 }
 211         }
 212
 213         if (validation_state->tmu_write_count[tmu] >= 4) {
 214                 DRM_ERROR("TMU%d got too many parameters before dispatch\n",
 215                           tmu);
 216                 return false;
 217         }
 218         validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] =
 219                 validated_shader->uniforms_size;
 220         validation_state->tmu_write_count[tmu]++;
 221         /* Since direct uses a RADDR uniform reference, it will get counted in
 222          * check_instruction_reads()
 223          */
 224         if (!is_direct)
 225                 validated_shader->uniforms_size += 4;
 226
 227         if (submit) {
 228                 if (!record_validated_texture_sample(validated_shader,
 229                                                      validation_state, tmu)) {
 230                         return false;
 231                 }
 232
 233                 validation_state->tmu_write_count[tmu] = 0;
 234         }
 235
 236         return true;
 237 }
 238
 239 static bool
 240 check_register_write(uint64_t inst,
 241                      struct vc4_validated_shader_info *validated_shader,
 242                      struct vc4_shader_validation_state *validation_state,
 243                      bool is_mul)
 244 {
 245         uint32_t waddr = (is_mul ?
 246                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
 247                           QPU_GET_FIELD(inst, QPU_WADDR_ADD));
 248         bool is_b = is_mul != ((inst & QPU_WS) != 0);
 249         uint32_t live_reg_index;
 250
 251         switch (waddr) {
 252         case QPU_W_UNIFORMS_ADDRESS:
 253                 /* XXX: We'll probably need to support this for reladdr, but
 254                  * it's definitely a security-related one.
 255                  */
 256                 DRM_ERROR("uniforms address load unsupported\n");
 257                 return false;
 258
 259         case QPU_W_TLB_COLOR_MS:
 260         case QPU_W_TLB_COLOR_ALL:
 261         case QPU_W_TLB_Z:
 262                 /* These only interact with the tile buffer, not main memory,
 263                  * so they're safe.
 264                  */
 265                 return true;
 266
 267         case QPU_W_TMU0_S:
 268         case QPU_W_TMU0_T:
 269         case QPU_W_TMU0_R:
 270         case QPU_W_TMU0_B:
 271         case QPU_W_TMU1_S:
 272         case QPU_W_TMU1_T:
 273         case QPU_W_TMU1_R:
 274         case QPU_W_TMU1_B:
 275                 return check_tmu_write(inst, validated_shader, validation_state,
 276                                        is_mul);
 277
 278         case QPU_W_HOST_INT:
 279         case QPU_W_TMU_NOSWAP:
 280         case QPU_W_TLB_ALPHA_MASK:
 281         case QPU_W_MUTEX_RELEASE:
 282                 /* XXX: I haven't thought about these, so don't support them
 283                  * for now.
 284                  */
 285                 DRM_ERROR("Unsupported waddr %d\n", waddr);
 286                 return false;
 287
 288         case QPU_W_VPM_ADDR:
 289                 DRM_ERROR("General VPM DMA unsupported\n");
 290                 return false;
 291
 292         case QPU_W_VPM:
 293         case QPU_W_VPMVCD_SETUP:
 294                 /* We allow VPM setup in general, even including VPM DMA
 295                  * configuration setup, because the (unsafe) DMA can only be
 296                  * triggered by QPU_W_VPM_ADDR writes.
 297                  */
 298                 return true;
 299
 300         case QPU_W_TLB_STENCIL_SETUP:
 301                 return true;
 302         }
 303
 304         /* Clear out the live offset clamp tracking for the written register.
 305          * If this particular instruction is setting up an offset clamp, it'll
 306          * get tracked immediately after we return.
 307          */
 308         live_reg_index = waddr_to_live_reg_index(waddr, is_b);
 309         if (live_reg_index != ~0)
 310                 validation_state->live_clamp_offsets[live_reg_index] = ~0;
 311
 312         return true;
 313 }
 314
 315 static void
 316 track_live_clamps(uint64_t inst,
 317                   struct vc4_validated_shader_info *validated_shader,
 318                   struct vc4_shader_validation_state *validation_state)
 319 {
 320         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 321         uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 322         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 323         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 324         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 325         bool is_b = inst & QPU_WS;
 326         uint32_t live_reg_index;
 327
 328         if (QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_MIN)
 329                 return;
 330
 331         if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
 332             !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF &&
 333               sig != QPU_SIG_SMALL_IMM)) {
 334                 return;
 335         }
 336
 337         live_reg_index = waddr_to_live_reg_index(waddr_add, is_b);
 338         if (live_reg_index != ~0) {
 339                 validation_state->live_clamp_offsets[live_reg_index] =
 340                         validated_shader->uniforms_size;
 341         }
 342 }
 343
 344 static bool
 345 check_instruction_writes(uint64_t inst,
 346                          struct vc4_validated_shader_info *validated_shader,
 347                          struct vc4_shader_validation_state *validation_state)
 348 {
 349         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 350         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 351         bool ok;
 352
 353         if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) {
 354                 DRM_ERROR("ADD and MUL both set up textures\n");
 355                 return false;
 356         }
 357
 358         ok = (check_register_write(inst, validated_shader, validation_state, false) &&
 359               check_register_write(inst, validated_shader, validation_state, true));
 360
 361         track_live_clamps(inst, validated_shader, validation_state);
 362
 363         return ok;
 364 }
 365
 366 static bool
 367 check_instruction_reads(uint64_t inst,
 368                         struct vc4_validated_shader_info *validated_shader)
 369 {
 370         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 371         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 372         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 373
 374         if (raddr_a == QPU_R_UNIF ||
 375             (raddr_b == QPU_R_UNIF && sig != QPU_SIG_SMALL_IMM)) {
 376                 /* This can't overflow the uint32_t, because we're reading 8
 377                  * bytes of instruction to increment by 4 here, so we'd
 378                  * already be OOM.
 379                  */
 380                 validated_shader->uniforms_size += 4;
 381         }
 382
 383         return true;
 384 }
 385
 386 struct vc4_validated_shader_info *
 387 vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
 388 {
 389         bool found_shader_end = false;
 390         int shader_end_ip = 0;
 391         uint32_t ip, max_ip;
 392         uint64_t *shader;
 393         struct vc4_validated_shader_info *validated_shader;
 394         struct vc4_shader_validation_state validation_state;
 395         int i;
 396
 397         memset(&validation_state, 0, sizeof(validation_state));
 398
 399         for (i = 0; i < 8; i++)
 400                 validation_state.tmu_setup[i / 4].p_offset[i % 4] = ~0;
 401         for (i = 0; i < ARRAY_SIZE(validation_state.live_clamp_offsets); i++)
 402                 validation_state.live_clamp_offsets[i] = ~0;
 403
 404         shader = shader_obj->vaddr;
 405         max_ip = shader_obj->base.size / sizeof(uint64_t);
 406
 407         validated_shader = kcalloc(sizeof(*validated_shader), 1, GFP_KERNEL);
 408         if (!validated_shader)
 409                 return NULL;
 410
 411         for (ip = 0; ip < max_ip; ip++) {
 412                 uint64_t inst = shader[ip];
 413                 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 414
 415                 switch (sig) {
 416                 case QPU_SIG_NONE:
 417                 case QPU_SIG_WAIT_FOR_SCOREBOARD:
 418                 case QPU_SIG_SCOREBOARD_UNLOCK:
 419                 case QPU_SIG_COLOR_LOAD:
 420                 case QPU_SIG_LOAD_TMU0:
 421                 case QPU_SIG_LOAD_TMU1:
 422                 case QPU_SIG_PROG_END:
 423                 case QPU_SIG_SMALL_IMM:
 424                         if (!check_instruction_writes(inst, validated_shader,
 425                                                       &validation_state)) {
 426                                 DRM_ERROR("Bad write at ip %d\n", ip);
 427                                 goto fail;
 428                         }
 429
 430                         if (!check_instruction_reads(inst, validated_shader))
 431                                 goto fail;
 432
 433                         if (sig == QPU_SIG_PROG_END) {
 434                                 found_shader_end = true;
 435                                 shader_end_ip = ip;
 436                         }
 437
 438                         break;
 439
 440                 case QPU_SIG_LOAD_IMM:
 441                         if (!check_instruction_writes(inst, validated_shader,
 442                                                       &validation_state)) {
 443                                 DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
 444                                 goto fail;
 445                         }
 446                         break;
 447
 448                 default:
 449                         DRM_ERROR("Unsupported QPU signal %d at "
 450                                   "instruction %d\n", sig, ip);
 451                         goto fail;
 452                 }
 453
 454                 /* There are two delay slots after program end is signaled
 455                  * that are still executed, then we're finished.
 456                  */
 457                 if (found_shader_end && ip == shader_end_ip + 2)
 458                         break;
 459         }
 460
 461         if (ip == max_ip) {
 462                 DRM_ERROR("shader failed to terminate before "
 463                           "shader BO end at %d\n",
 464                           shader_obj->base.size);
 465                 goto fail;
 466         }
 467
 468         /* Again, no chance of integer overflow here because the worst case
 469          * scenario is 8 bytes of uniforms plus handles per 8-byte
 470          * instruction.
 471          */
 472         validated_shader->uniforms_src_size =
 473                 (validated_shader->uniforms_size +
 474                  4 * validated_shader->num_texture_samples);
 475
 476         return validated_shader;
 477
 478 fail:
 479         kfree(validated_shader);
 480         return NULL;
 481 }