src/gallium/drivers/vc4/kernel/vc4_validate_shaders.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Shader validator for VC4.
  26  *
  27  * The VC4 has no IOMMU between it and system memory.  So, a user with access
  28  * to execute shaders could escalate privilege by overwriting system memory
  29  * (using the VPM write address register in the general-purpose DMA mode) or
  30  * reading system memory it shouldn't (reading it as a texture, or uniform
  31  * data, or vertex data).
  32  *
  33  * This walks over a shader starting from some offset within a BO, ensuring
  34  * that its accesses are appropriately bounded, and recording how many texture
  35  * accesses are made and where so that we can do relocations for them in the
  36  * uniform stream.
  37  *
  38  * The kernel API has shaders stored in user-mapped BOs.  The BOs will be
  39  * forcibly unmapped from the process before validation, and any cache of
  40  * validated state will be flushed if the mapping is faulted back in.
  41  *
  42  * Storing the shaders in BOs means that the validation process will be slow
  43  * due to uncached reads, but since shaders are long-lived and shader BOs are
  44  * never actually modified, this shouldn't be a problem.
  45  */
  46
  47 #include "vc4_drv.h"
  48 #include "vc4_qpu.h"
  49 #include "vc4_qpu_defines.h"
  50
  51 struct vc4_shader_validation_state {
  52         struct vc4_texture_sample_info tmu_setup[2];
  53         int tmu_write_count[2];
  54
  55         /* For registers that were last written to by a MIN instruction with
  56          * one argument being a uniform, the address of the uniform.
  57          * Otherwise, ~0.
  58          *
  59          * This is used for the validation of direct address memory reads.
  60          */
  61         uint32_t live_min_clamp_offsets[32 + 32 + 4];
  62         bool live_max_clamp_regs[32 + 32 + 4];
  63 };
  64
  65 static uint32_t
  66 waddr_to_live_reg_index(uint32_t waddr, bool is_b)
  67 {
  68         if (waddr < 32) {
  69                 if (is_b)
  70                         return 32 + waddr;
  71                 else
  72                         return waddr;
  73         } else if (waddr <= QPU_W_ACC3) {
  74
  75                 return 64 + waddr - QPU_W_ACC0;
  76         } else {
  77                 return ~0;
  78         }
  79 }
  80
  81 static uint32_t
  82 raddr_add_a_to_live_reg_index(uint64_t inst)
  83 {
  84         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
  85         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
  86         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
  87         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
  88
  89         if (add_a == QPU_MUX_A) {
  90                 return raddr_a;
  91         } else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM) {
  92                 return 32 + raddr_b;
  93         } else if (add_a <= QPU_MUX_R3) {
  94                 return 64 + add_a;
  95         } else {
  96                 return ~0;
  97         }
  98 }
  99
 100 static bool
 101 is_tmu_submit(uint32_t waddr)
 102 {
 103         return (waddr == QPU_W_TMU0_S ||
 104                 waddr == QPU_W_TMU1_S);
 105 }
 106
 107 static bool
 108 is_tmu_write(uint32_t waddr)
 109 {
 110         return (waddr >= QPU_W_TMU0_S &&
 111                 waddr <= QPU_W_TMU1_B);
 112 }
 113
 114 static bool
 115 record_validated_texture_sample(struct vc4_validated_shader_info *validated_shader,
 116                                 struct vc4_shader_validation_state *validation_state,
 117                                 int tmu)
 118 {
 119         uint32_t s = validated_shader->num_texture_samples;
 120         int i;
 121         struct vc4_texture_sample_info *temp_samples;
 122
 123         temp_samples = krealloc(validated_shader->texture_samples,
 124                                 (s + 1) * sizeof(*temp_samples),
 125                                 GFP_KERNEL);
 126         if (!temp_samples)
 127                 return false;
 128
 129         memcpy(&temp_samples[s],
 130                &validation_state->tmu_setup[tmu],
 131                sizeof(*temp_samples));
 132
 133         validated_shader->num_texture_samples = s + 1;
 134         validated_shader->texture_samples = temp_samples;
 135
 136         for (i = 0; i < 4; i++)
 137                 validation_state->tmu_setup[tmu].p_offset[i] = ~0;
 138
 139         return true;
 140 }
 141
 142 static bool
 143 check_tmu_write(uint64_t inst,
 144                 struct vc4_validated_shader_info *validated_shader,
 145                 struct vc4_shader_validation_state *validation_state,
 146                 bool is_mul)
 147 {
 148         uint32_t waddr = (is_mul ?
 149                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
 150                           QPU_GET_FIELD(inst, QPU_WADDR_ADD));
 151         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 152         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 153         int tmu = waddr > QPU_W_TMU0_B;
 154         bool submit = is_tmu_submit(waddr);
 155         bool is_direct = submit && validation_state->tmu_write_count[tmu] == 0;
 156         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 157
 158         if (is_direct) {
 159                 uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 160                 uint32_t clamp_reg, clamp_offset;
 161
 162                 if (sig == QPU_SIG_SMALL_IMM) {
 163                         DRM_ERROR("direct TMU read used small immediate\n");
 164                         return false;
 165                 }
 166
 167                 /* Make sure that this texture load is an add of the base
 168                  * address of the UBO to a clamped offset within the UBO.
 169                  */
 170                 if (is_mul ||
 171                     QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
 172                         DRM_ERROR("direct TMU load wasn't an add\n");
 173                         return false;
 174                 }
 175
 176                 /* We assert that the the clamped address is the first
 177                  * argument, and the UBO base address is the second argument.
 178                  * This is arbitrary, but simpler than supporting flipping the
 179                  * two either way.
 180                  */
 181                 clamp_reg = raddr_add_a_to_live_reg_index(inst);
 182                 if (clamp_reg == ~0) {
 183                         DRM_ERROR("direct TMU load wasn't clamped\n");
 184                         return false;
 185                 }
 186
 187                 clamp_offset = validation_state->live_min_clamp_offsets[clamp_reg];
 188                 if (clamp_offset == ~0) {
 189                         DRM_ERROR("direct TMU load wasn't clamped\n");
 190                         return false;
 191                 }
 192
 193                 /* Store the clamp value's offset in p1 (see reloc_tex() in
 194                  * vc4_validate.c).
 195                  */
 196                 validation_state->tmu_setup[tmu].p_offset[1] =
 197                         clamp_offset;
 198
 199                 if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
 200                     !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
 201                         DRM_ERROR("direct TMU load didn't add to a uniform\n");
 202                         return false;
 203                 }
 204
 205                 validation_state->tmu_setup[tmu].is_direct = true;
 206         } else {
 207                 if (raddr_a == QPU_R_UNIF || (sig != QPU_SIG_SMALL_IMM &&
 208                                               raddr_b == QPU_R_UNIF)) {
 209                         DRM_ERROR("uniform read in the same instruction as "
 210                                   "texture setup.\n");
 211                         return false;
 212                 }
 213         }
 214
 215         if (validation_state->tmu_write_count[tmu] >= 4) {
 216                 DRM_ERROR("TMU%d got too many parameters before dispatch\n",
 217                           tmu);
 218                 return false;
 219         }
 220         validation_state->tmu_setup[tmu].p_offset[validation_state->tmu_write_count[tmu]] =
 221                 validated_shader->uniforms_size;
 222         validation_state->tmu_write_count[tmu]++;
 223         /* Since direct uses a RADDR uniform reference, it will get counted in
 224          * check_instruction_reads()
 225          */
 226         if (!is_direct)
 227                 validated_shader->uniforms_size += 4;
 228
 229         if (submit) {
 230                 if (!record_validated_texture_sample(validated_shader,
 231                                                      validation_state, tmu)) {
 232                         return false;
 233                 }
 234
 235                 validation_state->tmu_write_count[tmu] = 0;
 236         }
 237
 238         return true;
 239 }
 240
 241 static bool
 242 check_register_write(uint64_t inst,
 243                      struct vc4_validated_shader_info *validated_shader,
 244                      struct vc4_shader_validation_state *validation_state,
 245                      bool is_mul)
 246 {
 247         uint32_t waddr = (is_mul ?
 248                           QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
 249                           QPU_GET_FIELD(inst, QPU_WADDR_ADD));
 250
 251         switch (waddr) {
 252         case QPU_W_UNIFORMS_ADDRESS:
 253                 /* XXX: We'll probably need to support this for reladdr, but
 254                  * it's definitely a security-related one.
 255                  */
 256                 DRM_ERROR("uniforms address load unsupported\n");
 257                 return false;
 258
 259         case QPU_W_TLB_COLOR_MS:
 260         case QPU_W_TLB_COLOR_ALL:
 261         case QPU_W_TLB_Z:
 262                 /* These only interact with the tile buffer, not main memory,
 263                  * so they're safe.
 264                  */
 265                 return true;
 266
 267         case QPU_W_TMU0_S:
 268         case QPU_W_TMU0_T:
 269         case QPU_W_TMU0_R:
 270         case QPU_W_TMU0_B:
 271         case QPU_W_TMU1_S:
 272         case QPU_W_TMU1_T:
 273         case QPU_W_TMU1_R:
 274         case QPU_W_TMU1_B:
 275                 return check_tmu_write(inst, validated_shader, validation_state,
 276                                        is_mul);
 277
 278         case QPU_W_HOST_INT:
 279         case QPU_W_TMU_NOSWAP:
 280         case QPU_W_TLB_ALPHA_MASK:
 281         case QPU_W_MUTEX_RELEASE:
 282                 /* XXX: I haven't thought about these, so don't support them
 283                  * for now.
 284                  */
 285                 DRM_ERROR("Unsupported waddr %d\n", waddr);
 286                 return false;
 287
 288         case QPU_W_VPM_ADDR:
 289                 DRM_ERROR("General VPM DMA unsupported\n");
 290                 return false;
 291
 292         case QPU_W_VPM:
 293         case QPU_W_VPMVCD_SETUP:
 294                 /* We allow VPM setup in general, even including VPM DMA
 295                  * configuration setup, because the (unsafe) DMA can only be
 296                  * triggered by QPU_W_VPM_ADDR writes.
 297                  */
 298                 return true;
 299
 300         case QPU_W_TLB_STENCIL_SETUP:
 301                 return true;
 302         }
 303
 304         return true;
 305 }
 306
 307 static void
 308 track_live_clamps(uint64_t inst,
 309                   struct vc4_validated_shader_info *validated_shader,
 310                   struct vc4_shader_validation_state *validation_state)
 311 {
 312         uint32_t op_add = QPU_GET_FIELD(inst, QPU_OP_ADD);
 313         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 314         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 315         uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
 316         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
 317         uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 318         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 319         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 320         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 321         bool ws = inst & QPU_WS;
 322         uint32_t lri_add_a, lri_add, lri_mul;
 323         bool add_a_is_min_0;
 324
 325         /* Check whether OP_ADD's A argumennt comes from a live MAX(x, 0),
 326          * before we clear previous live state.
 327          */
 328         lri_add_a = raddr_add_a_to_live_reg_index(inst);
 329         add_a_is_min_0 = (lri_add_a != ~0 &&
 330                           validation_state->live_max_clamp_regs[lri_add_a]);
 331
 332         /* Clear live state for registers written by our instruction. */
 333         lri_add = waddr_to_live_reg_index(waddr_add, ws);
 334         lri_mul = waddr_to_live_reg_index(waddr_mul, !ws);
 335         if (lri_mul != ~0) {
 336                 validation_state->live_max_clamp_regs[lri_mul] = false;
 337                 validation_state->live_min_clamp_offsets[lri_mul] = ~0;
 338         }
 339         if (lri_add != ~0) {
 340                 validation_state->live_max_clamp_regs[lri_add] = false;
 341                 validation_state->live_min_clamp_offsets[lri_add] = ~0;
 342         } else {
 343                 /* Nothing further to do for live tracking, since only ADDs
 344                  * generate new live clamp registers.
 345                  */
 346                 return;
 347         }
 348
 349         /* Now, handle remaining live clamp tracking for the ADD operation. */
 350
 351         if (cond_add != QPU_COND_ALWAYS)
 352                 return;
 353
 354         if (op_add == QPU_A_MAX) {
 355                 /* Track live clamps of a value to a minimum of 0 (in either
 356                  * arg).
 357                  */
 358                 if (sig != QPU_SIG_SMALL_IMM || raddr_b != 0 ||
 359                     (add_a != QPU_MUX_B && add_b != QPU_MUX_B)) {
 360                         return;
 361                 }
 362
 363                 validation_state->live_max_clamp_regs[lri_add] = true;
 364         } if (op_add == QPU_A_MIN) {
 365                 /* Track live clamps of a value clamped to a minimum of 0 and
 366                  * a maximum of some uniform's offset.
 367                  */
 368                 if (!add_a_is_min_0)
 369                         return;
 370
 371                 if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
 372                     !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF &&
 373                       sig != QPU_SIG_SMALL_IMM)) {
 374                         return;
 375                 }
 376
 377                 validation_state->live_min_clamp_offsets[lri_add] =
 378                         validated_shader->uniforms_size;
 379         }
 380 }
 381
 382 static bool
 383 check_instruction_writes(uint64_t inst,
 384                          struct vc4_validated_shader_info *validated_shader,
 385                          struct vc4_shader_validation_state *validation_state)
 386 {
 387         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 388         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 389         bool ok;
 390
 391         if (is_tmu_write(waddr_add) && is_tmu_write(waddr_mul)) {
 392                 DRM_ERROR("ADD and MUL both set up textures\n");
 393                 return false;
 394         }
 395
 396         ok = (check_register_write(inst, validated_shader, validation_state, false) &&
 397               check_register_write(inst, validated_shader, validation_state, true));
 398
 399         track_live_clamps(inst, validated_shader, validation_state);
 400
 401         return ok;
 402 }
 403
 404 static bool
 405 check_instruction_reads(uint64_t inst,
 406                         struct vc4_validated_shader_info *validated_shader)
 407 {
 408         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 409         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 410         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 411
 412         if (raddr_a == QPU_R_UNIF ||
 413             (raddr_b == QPU_R_UNIF && sig != QPU_SIG_SMALL_IMM)) {
 414                 /* This can't overflow the uint32_t, because we're reading 8
 415                  * bytes of instruction to increment by 4 here, so we'd
 416                  * already be OOM.
 417                  */
 418                 validated_shader->uniforms_size += 4;
 419         }
 420
 421         return true;
 422 }
 423
 424 struct vc4_validated_shader_info *
 425 vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
 426 {
 427         bool found_shader_end = false;
 428         int shader_end_ip = 0;
 429         uint32_t ip, max_ip;
 430         uint64_t *shader;
 431         struct vc4_validated_shader_info *validated_shader;
 432         struct vc4_shader_validation_state validation_state;
 433         int i;
 434
 435         memset(&validation_state, 0, sizeof(validation_state));
 436
 437         for (i = 0; i < 8; i++)
 438                 validation_state.tmu_setup[i / 4].p_offset[i % 4] = ~0;
 439         for (i = 0; i < ARRAY_SIZE(validation_state.live_min_clamp_offsets); i++)
 440                 validation_state.live_min_clamp_offsets[i] = ~0;
 441
 442         shader = shader_obj->vaddr;
 443         max_ip = shader_obj->base.size / sizeof(uint64_t);
 444
 445         validated_shader = kcalloc(sizeof(*validated_shader), 1, GFP_KERNEL);
 446         if (!validated_shader)
 447                 return NULL;
 448
 449         for (ip = 0; ip < max_ip; ip++) {
 450                 uint64_t inst = shader[ip];
 451                 uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 452
 453                 switch (sig) {
 454                 case QPU_SIG_NONE:
 455                 case QPU_SIG_WAIT_FOR_SCOREBOARD:
 456                 case QPU_SIG_SCOREBOARD_UNLOCK:
 457                 case QPU_SIG_COLOR_LOAD:
 458                 case QPU_SIG_LOAD_TMU0:
 459                 case QPU_SIG_LOAD_TMU1:
 460                 case QPU_SIG_PROG_END:
 461                 case QPU_SIG_SMALL_IMM:
 462                         if (!check_instruction_writes(inst, validated_shader,
 463                                                       &validation_state)) {
 464                                 DRM_ERROR("Bad write at ip %d\n", ip);
 465                                 goto fail;
 466                         }
 467
 468                         if (!check_instruction_reads(inst, validated_shader))
 469                                 goto fail;
 470
 471                         if (sig == QPU_SIG_PROG_END) {
 472                                 found_shader_end = true;
 473                                 shader_end_ip = ip;
 474                         }
 475
 476                         break;
 477
 478                 case QPU_SIG_LOAD_IMM:
 479                         if (!check_instruction_writes(inst, validated_shader,
 480                                                       &validation_state)) {
 481                                 DRM_ERROR("Bad LOAD_IMM write at ip %d\n", ip);
 482                                 goto fail;
 483                         }
 484                         break;
 485
 486                 default:
 487                         DRM_ERROR("Unsupported QPU signal %d at "
 488                                   "instruction %d\n", sig, ip);
 489                         goto fail;
 490                 }
 491
 492                 /* There are two delay slots after program end is signaled
 493                  * that are still executed, then we're finished.
 494                  */
 495                 if (found_shader_end && ip == shader_end_ip + 2)
 496                         break;
 497         }
 498
 499         if (ip == max_ip) {
 500                 DRM_ERROR("shader failed to terminate before "
 501                           "shader BO end at %d\n",
 502                           shader_obj->base.size);
 503                 goto fail;
 504         }
 505
 506         /* Again, no chance of integer overflow here because the worst case
 507          * scenario is 8 bytes of uniforms plus handles per 8-byte
 508          * instruction.
 509          */
 510         validated_shader->uniforms_src_size =
 511                 (validated_shader->uniforms_size +
 512                  4 * validated_shader->num_texture_samples);
 513
 514         return validated_shader;
 515
 516 fail:
 517         kfree(validated_shader);
 518         return NULL;
 519 }