Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / vc4 / vc4_blit.c
1 /*
2 * Copyright © 2015 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/u_format.h"
25 #include "util/u_surface.h"
26 #include "util/u_blitter.h"
27 #include "vc4_context.h"
28
29 static struct pipe_surface *
30 vc4_get_blit_surface(struct pipe_context *pctx,
31 struct pipe_resource *prsc, unsigned level)
32 {
33 struct pipe_surface tmpl;
34
35 memset(&tmpl, 0, sizeof(tmpl));
36 tmpl.format = prsc->format;
37 tmpl.u.tex.level = level;
38 tmpl.u.tex.first_layer = 0;
39 tmpl.u.tex.last_layer = 0;
40
41 return pctx->create_surface(pctx, prsc, &tmpl);
42 }
43
44 static bool
45 is_tile_unaligned(unsigned size, unsigned tile_size)
46 {
47 return size & (tile_size - 1);
48 }
49
50 static bool
51 vc4_tile_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
52 {
53 struct vc4_context *vc4 = vc4_context(pctx);
54 bool old_msaa = vc4->msaa;
55 int old_tile_width = vc4->tile_width;
56 int old_tile_height = vc4->tile_height;
57 bool msaa = (info->src.resource->nr_samples > 1 ||
58 info->dst.resource->nr_samples > 1);
59 int tile_width = msaa ? 32 : 64;
60 int tile_height = msaa ? 32 : 64;
61
62 if (util_format_is_depth_or_stencil(info->dst.resource->format))
63 return false;
64
65 if (info->scissor_enable)
66 return false;
67
68 if ((info->mask & PIPE_MASK_RGBA) == 0)
69 return false;
70
71 if (info->dst.box.x != info->src.box.x ||
72 info->dst.box.y != info->src.box.y ||
73 info->dst.box.width != info->src.box.width ||
74 info->dst.box.height != info->src.box.height) {
75 return false;
76 }
77
78 int dst_surface_width = u_minify(info->dst.resource->width0,
79 info->dst.level);
80 int dst_surface_height = u_minify(info->dst.resource->height0,
81 info->dst.level);
82 if (is_tile_unaligned(info->dst.box.x, tile_width) ||
83 is_tile_unaligned(info->dst.box.y, tile_height) ||
84 (is_tile_unaligned(info->dst.box.width, tile_width) &&
85 info->dst.box.x + info->dst.box.width != dst_surface_width) ||
86 (is_tile_unaligned(info->dst.box.height, tile_height) &&
87 info->dst.box.y + info->dst.box.height != dst_surface_height)) {
88 return false;
89 }
90
91 if (info->dst.resource->format != info->src.resource->format)
92 return false;
93
94 vc4_flush(pctx);
95
96 if (false) {
97 fprintf(stderr, "RCL blit from %d,%d to %d,%d (%d,%d)\n",
98 info->src.box.x,
99 info->src.box.y,
100 info->dst.box.x,
101 info->dst.box.y,
102 info->dst.box.width,
103 info->dst.box.height);
104 }
105
106 struct pipe_surface *dst_surf =
107 vc4_get_blit_surface(pctx, info->dst.resource, info->dst.level);
108 struct pipe_surface *src_surf =
109 vc4_get_blit_surface(pctx, info->src.resource, info->src.level);
110
111 pipe_surface_reference(&vc4->color_read, src_surf);
112 pipe_surface_reference(&vc4->color_write,
113 dst_surf->texture->nr_samples > 1 ?
114 NULL : dst_surf);
115 pipe_surface_reference(&vc4->msaa_color_write,
116 dst_surf->texture->nr_samples > 1 ?
117 dst_surf : NULL);
118 pipe_surface_reference(&vc4->zs_read, NULL);
119 pipe_surface_reference(&vc4->zs_write, NULL);
120 pipe_surface_reference(&vc4->msaa_zs_write, NULL);
121
122 vc4->draw_min_x = info->dst.box.x;
123 vc4->draw_min_y = info->dst.box.y;
124 vc4->draw_max_x = info->dst.box.x + info->dst.box.width;
125 vc4->draw_max_y = info->dst.box.y + info->dst.box.height;
126 vc4->draw_width = dst_surf->width;
127 vc4->draw_height = dst_surf->height;
128
129 vc4->tile_width = tile_width;
130 vc4->tile_height = tile_height;
131 vc4->msaa = msaa;
132 vc4->needs_flush = true;
133
134 vc4_job_submit(vc4);
135
136 vc4->msaa = old_msaa;
137 vc4->tile_width = old_tile_width;
138 vc4->tile_height = old_tile_height;
139
140 pipe_surface_reference(&dst_surf, NULL);
141 pipe_surface_reference(&src_surf, NULL);
142
143 return true;
144 }
145
146 static bool
147 vc4_render_blit(struct pipe_context *ctx, struct pipe_blit_info *info)
148 {
149 struct vc4_context *vc4 = vc4_context(ctx);
150
151 if (!util_blitter_is_blit_supported(vc4->blitter, info)) {
152 fprintf(stderr, "blit unsupported %s -> %s\n",
153 util_format_short_name(info->src.resource->format),
154 util_format_short_name(info->dst.resource->format));
155 return false;
156 }
157
158 util_blitter_save_vertex_buffer_slot(vc4->blitter, vc4->vertexbuf.vb);
159 util_blitter_save_vertex_elements(vc4->blitter, vc4->vtx);
160 util_blitter_save_vertex_shader(vc4->blitter, vc4->prog.bind_vs);
161 util_blitter_save_rasterizer(vc4->blitter, vc4->rasterizer);
162 util_blitter_save_viewport(vc4->blitter, &vc4->viewport);
163 util_blitter_save_scissor(vc4->blitter, &vc4->scissor);
164 util_blitter_save_fragment_shader(vc4->blitter, vc4->prog.bind_fs);
165 util_blitter_save_blend(vc4->blitter, vc4->blend);
166 util_blitter_save_depth_stencil_alpha(vc4->blitter, vc4->zsa);
167 util_blitter_save_stencil_ref(vc4->blitter, &vc4->stencil_ref);
168 util_blitter_save_sample_mask(vc4->blitter, vc4->sample_mask);
169 util_blitter_save_framebuffer(vc4->blitter, &vc4->framebuffer);
170 util_blitter_save_fragment_sampler_states(vc4->blitter,
171 vc4->fragtex.num_samplers,
172 (void **)vc4->fragtex.samplers);
173 util_blitter_save_fragment_sampler_views(vc4->blitter,
174 vc4->fragtex.num_textures, vc4->fragtex.textures);
175
176 util_blitter_blit(vc4->blitter, info);
177
178 return true;
179 }
180
181 /* Optimal hardware path for blitting pixels.
182 * Scaling, format conversion, up- and downsampling (resolve) are allowed.
183 */
184 void
185 vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
186 {
187 struct pipe_blit_info info = *blit_info;
188
189 if (vc4_tile_blit(pctx, blit_info))
190 return;
191
192 if (util_try_blit_via_copy_region(pctx, &info)) {
193 return; /* done */
194 }
195
196 if (info.mask & PIPE_MASK_S) {
197 fprintf(stderr, "cannot blit stencil, skipping\n");
198 info.mask &= ~PIPE_MASK_S;
199 }
200
201 vc4_render_blit(pctx, &info);
202 }