src/gallium/drivers/vc4/vc4_context.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <xf86drm.h>
  25 #include <err.h>
  26
  27 #include "pipe/p_defines.h"
  28 #include "util/ralloc.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_blitter.h"
  32 #include "indices/u_primconvert.h"
  33 #include "pipe/p_screen.h"
  34
  35 #include "vc4_screen.h"
  36 #include "vc4_context.h"
  37 #include "vc4_resource.h"
  38
  39 /**
  40  * Emits a no-op STORE_TILE_BUFFER_GENERAL.
  41  *
  42  * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of
  43  * some sort before another load is triggered.
  44  */
  45 static void
  46 vc4_store_before_load(struct vc4_context *vc4, bool *coords_emitted)
  47 {
  48         if (!*coords_emitted)
  49                 return;
  50
  51         cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
  52         cl_u8(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE);
  53         cl_u8(&vc4->rcl, (VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
  54                           VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
  55                           VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR));
  56         cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */
  57
  58         *coords_emitted = false;
  59 }
  60
  61 /**
  62  * Emits a PACKET_TILE_COORDINATES if one isn't already pending.
  63  *
  64  * The tile coordinates packet triggers a pending load if there is one, are
  65  * used for clipping during rendering, and determine where loads/stores happen
  66  * relative to their base address.
  67  */
  68 static void
  69 vc4_tile_coordinates(struct vc4_context *vc4, uint32_t x, uint32_t y,
  70                        bool *coords_emitted)
  71 {
  72         if (*coords_emitted)
  73                 return;
  74
  75         cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
  76         cl_u8(&vc4->rcl, x);
  77         cl_u8(&vc4->rcl, y);
  78
  79         *coords_emitted = true;
  80 }
  81
  82 static void
  83 vc4_setup_rcl(struct vc4_context *vc4)
  84 {
  85         struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
  86         struct vc4_resource *ctex = csurf ? vc4_resource(csurf->base.texture) : NULL;
  87         struct vc4_surface *zsurf = vc4_surface(vc4->framebuffer.zsbuf);
  88         struct vc4_resource *ztex = zsurf ? vc4_resource(zsurf->base.texture) : NULL;
  89
  90         if (!csurf)
  91                 vc4->resolve &= ~PIPE_CLEAR_COLOR0;
  92         if (!zsurf)
  93                 vc4->resolve &= ~(PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL);
  94         uint32_t resolve_uncleared = vc4->resolve & ~vc4->cleared;
  95         uint32_t width = vc4->framebuffer.width;
  96         uint32_t height = vc4->framebuffer.height;
  97         uint32_t stride_in_tiles = align(width, 64) / 64;
  98
  99         assert(vc4->draw_min_x != ~0 && vc4->draw_min_y != ~0);
 100         uint32_t min_x_tile = vc4->draw_min_x / 64;
 101         uint32_t min_y_tile = vc4->draw_min_y / 64;
 102         uint32_t max_x_tile = (vc4->draw_max_x - 1) / 64;
 103         uint32_t max_y_tile = (vc4->draw_max_y - 1) / 64;
 104         uint32_t xtiles = max_x_tile - min_x_tile + 1;
 105         uint32_t ytiles = max_y_tile - min_y_tile + 1;
 106
 107 #if 0
 108         fprintf(stderr, "RCL: resolve 0x%x clear 0x%x resolve uncleared 0x%x\n",
 109                 vc4->resolve,
 110                 vc4->cleared,
 111                 resolve_uncleared);
 112 #endif
 113
 114         uint32_t reloc_size = 9;
 115         uint32_t clear_size = 14;
 116         uint32_t config_size = 11 + reloc_size;
 117         uint32_t loadstore_size = 7 + reloc_size;
 118         uint32_t tilecoords_size = 3;
 119         uint32_t branch_size = 5 + reloc_size;
 120         uint32_t color_store_size = 1;
 121         cl_ensure_space(&vc4->rcl,
 122                         clear_size +
 123                         config_size +
 124                         loadstore_size +
 125                         xtiles * ytiles * (loadstore_size * 4 +
 126                                            tilecoords_size * 3 +
 127                                            branch_size +
 128                                            color_store_size));
 129
 130         cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS);
 131         cl_u32(&vc4->rcl, vc4->clear_color[0]);
 132         cl_u32(&vc4->rcl, vc4->clear_color[1]);
 133         cl_u32(&vc4->rcl, vc4->clear_depth);
 134         cl_u8(&vc4->rcl, vc4->clear_stencil);
 135
 136         /* The rendering mode config determines the pointer that's used for
 137          * VC4_PACKET_STORE_MS_TILE_BUFFER address computations.  The kernel
 138          * could handle a no-relocation rendering mode config and deny those
 139          * packets, but instead we just tell the kernel we're doing our color
 140          * rendering to the Z buffer, and just don't emit any of those
 141          * packets.
 142          */
 143         struct vc4_surface *render_surf = csurf ? csurf : zsurf;
 144         struct vc4_resource *render_tex = vc4_resource(render_surf->base.texture);
 145         cl_start_reloc(&vc4->rcl, 1);
 146         cl_u8(&vc4->rcl, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
 147         cl_reloc(vc4, &vc4->rcl, render_tex->bo, render_surf->offset);
 148         cl_u16(&vc4->rcl, width);
 149         cl_u16(&vc4->rcl, height);
 150         cl_u16(&vc4->rcl, ((render_surf->tiling <<
 151                             VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) |
 152                            (vc4_rt_format_is_565(render_surf->base.format) ?
 153                             VC4_RENDER_CONFIG_FORMAT_BGR565 :
 154                             VC4_RENDER_CONFIG_FORMAT_RGBA8888) |
 155                            VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE));
 156
 157         /* The tile buffer normally gets cleared when the previous tile is
 158          * stored.  If the clear values changed between frames, then the tile
 159          * buffer has stale clear values in it, so we have to do a store in
 160          * None mode (no writes) so that we trigger the tile buffer clear.
 161          *
 162          * Excess clearing is only a performance cost, since per-tile contents
 163          * will be loaded/stored in the loop below.
 164          */
 165         if (vc4->cleared & (PIPE_CLEAR_COLOR0 |
 166                             PIPE_CLEAR_DEPTH |
 167                             PIPE_CLEAR_STENCIL)) {
 168                 cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
 169                 cl_u8(&vc4->rcl, 0);
 170                 cl_u8(&vc4->rcl, 0);
 171
 172                 cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
 173                 cl_u16(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE);
 174                 cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */
 175         }
 176
 177         uint32_t color_hindex = ctex ? vc4_gem_hindex(vc4, ctex->bo) : 0;
 178         uint32_t depth_hindex = ztex ? vc4_gem_hindex(vc4, ztex->bo) : 0;
 179         uint32_t tile_alloc_hindex = vc4_gem_hindex(vc4, vc4->tile_alloc);
 180
 181         for (int y = min_y_tile; y <= max_y_tile; y++) {
 182                 for (int x = min_x_tile; x <= max_x_tile; x++) {
 183                         bool end_of_frame = (x == max_x_tile &&
 184                                              y == max_y_tile);
 185                         bool coords_emitted = false;
 186
 187                         /* Note that the load doesn't actually occur until the
 188                          * tile coords packet is processed, and only one load
 189                          * may be outstanding at a time.
 190                          */
 191                         if (resolve_uncleared & PIPE_CLEAR_COLOR) {
 192                                 vc4_store_before_load(vc4, &coords_emitted);
 193
 194                                 cl_start_reloc(&vc4->rcl, 1);
 195                                 cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
 196                                 cl_u8(&vc4->rcl,
 197                                       VC4_LOADSTORE_TILE_BUFFER_COLOR |
 198                                       (csurf->tiling <<
 199                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 200                                 cl_u8(&vc4->rcl,
 201                                       vc4_rt_format_is_565(csurf->base.format) ?
 202                                       VC4_LOADSTORE_TILE_BUFFER_BGR565 :
 203                                       VC4_LOADSTORE_TILE_BUFFER_RGBA8888);
 204                                 cl_reloc_hindex(&vc4->rcl, color_hindex,
 205                                                 csurf->offset);
 206
 207                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 208                         }
 209
 210                         if (resolve_uncleared & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 211                                 vc4_store_before_load(vc4, &coords_emitted);
 212
 213                                 cl_start_reloc(&vc4->rcl, 1);
 214                                 cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
 215                                 cl_u8(&vc4->rcl,
 216                                       VC4_LOADSTORE_TILE_BUFFER_ZS |
 217                                       (zsurf->tiling <<
 218                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 219                                 cl_u8(&vc4->rcl, 0);
 220                                 cl_reloc_hindex(&vc4->rcl, depth_hindex,
 221                                                 zsurf->offset);
 222
 223                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 224                         }
 225
 226                         /* Clipping depends on tile coordinates having been
 227                          * emitted, so make sure it's happened even if
 228                          * everything was cleared to start.
 229                          */
 230                         vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 231
 232                         /* Wait for the binner before jumping to the first
 233                          * tile's lists.
 234                          */
 235                         if (x == min_x_tile && y == min_y_tile)
 236                                 cl_u8(&vc4->rcl, VC4_PACKET_WAIT_ON_SEMAPHORE);
 237
 238                         cl_start_reloc(&vc4->rcl, 1);
 239                         cl_u8(&vc4->rcl, VC4_PACKET_BRANCH_TO_SUB_LIST);
 240                         cl_reloc_hindex(&vc4->rcl, tile_alloc_hindex,
 241                                         (y * stride_in_tiles + x) * 32);
 242
 243                         if (vc4->resolve & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 244                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 245
 246                                 cl_start_reloc(&vc4->rcl, 1);
 247                                 cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
 248                                 cl_u8(&vc4->rcl,
 249                                       VC4_LOADSTORE_TILE_BUFFER_ZS |
 250                                       (zsurf->tiling <<
 251                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 252                                 cl_u8(&vc4->rcl,
 253                                       VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR);
 254                                 cl_reloc_hindex(&vc4->rcl, depth_hindex,
 255                                                 zsurf->offset |
 256                                                 ((end_of_frame &&
 257                                                   !(vc4->resolve & PIPE_CLEAR_COLOR0)) ?
 258                                                  VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
 259
 260                                 coords_emitted = false;
 261                         }
 262
 263                         if (vc4->resolve & PIPE_CLEAR_COLOR0) {
 264                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 265                                 if (end_of_frame) {
 266                                         cl_u8(&vc4->rcl,
 267                                               VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
 268                                 } else {
 269                                         cl_u8(&vc4->rcl,
 270                                               VC4_PACKET_STORE_MS_TILE_BUFFER);
 271                                 }
 272
 273                                 coords_emitted = false;
 274                         }
 275
 276                         /* One of the bits needs to have been set that would
 277                          * have triggered an EOF.
 278                          */
 279                         assert(vc4->resolve & (PIPE_CLEAR_COLOR0 |
 280                                                PIPE_CLEAR_DEPTH |
 281                                                PIPE_CLEAR_STENCIL));
 282                         /* Any coords emitted must also have been consumed by
 283                          * a store.
 284                          */
 285                         assert(!coords_emitted);
 286                 }
 287         }
 288
 289         if (vc4->resolve & PIPE_CLEAR_COLOR0)
 290                 ctex->writes++;
 291
 292         if (vc4->resolve & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))
 293                 ztex->writes++;
 294 }
 295
 296 static void
 297 vc4_draw_reset(struct vc4_context *vc4)
 298 {
 299         struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
 300         for (int i = 0; i < (vc4->bo_handles.next -
 301                              vc4->bo_handles.base) / 4; i++) {
 302                 vc4_bo_unreference(&referenced_bos[i]);
 303         }
 304         vc4_reset_cl(&vc4->bcl);
 305         vc4_reset_cl(&vc4->rcl);
 306         vc4_reset_cl(&vc4->shader_rec);
 307         vc4_reset_cl(&vc4->uniforms);
 308         vc4_reset_cl(&vc4->bo_handles);
 309         vc4_reset_cl(&vc4->bo_pointers);
 310         vc4->shader_rec_count = 0;
 311
 312         vc4->needs_flush = false;
 313         vc4->draw_call_queued = false;
 314
 315         /* We have no hardware context saved between our draw calls, so we
 316          * need to flag the next draw as needing all state emitted.  Emitting
 317          * all state at the start of our draws is also what ensures that we
 318          * return to the state we need after a previous tile has finished.
 319          */
 320         vc4->dirty = ~0;
 321         vc4->resolve = 0;
 322         vc4->cleared = 0;
 323
 324         vc4->draw_min_x = ~0;
 325         vc4->draw_min_y = ~0;
 326         vc4->draw_max_x = 0;
 327         vc4->draw_max_y = 0;
 328 }
 329
 330 void
 331 vc4_flush(struct pipe_context *pctx)
 332 {
 333         struct vc4_context *vc4 = vc4_context(pctx);
 334
 335         if (!vc4->needs_flush)
 336                 return;
 337
 338         /* The RCL setup would choke if the draw bounds cause no drawing, so
 339          * just drop the drawing if that's the case.
 340          */
 341         if (vc4->draw_max_x <= vc4->draw_min_x ||
 342             vc4->draw_max_y <= vc4->draw_min_y) {
 343                 vc4_draw_reset(vc4);
 344                 return;
 345         }
 346
 347         /* Increment the semaphore indicating that binning is done and
 348          * unblocking the render thread.  Note that this doesn't act until the
 349          * FLUSH completes.
 350          */
 351         cl_u8(&vc4->bcl, VC4_PACKET_INCREMENT_SEMAPHORE);
 352         /* The FLUSH caps all of our bin lists with a VC4_PACKET_RETURN. */
 353         cl_u8(&vc4->bcl, VC4_PACKET_FLUSH);
 354
 355         vc4_setup_rcl(vc4);
 356
 357         if (vc4_debug & VC4_DEBUG_CL) {
 358                 fprintf(stderr, "BCL:\n");
 359                 vc4_dump_cl(vc4->bcl.base, vc4->bcl.size, false);
 360                 fprintf(stderr, "RCL:\n");
 361                 vc4_dump_cl(vc4->rcl.base, vc4->rcl.size, true);
 362         }
 363
 364         struct drm_vc4_submit_cl submit;
 365         memset(&submit, 0, sizeof(submit));
 366
 367         submit.bo_handles = vc4->bo_handles.base;
 368         submit.bo_handle_count = (vc4->bo_handles.next -
 369                                   vc4->bo_handles.base) / 4;
 370         submit.bin_cl = vc4->bcl.base;
 371         submit.bin_cl_size = vc4->bcl.next - vc4->bcl.base;
 372         submit.render_cl = vc4->rcl.base;
 373         submit.render_cl_size = vc4->rcl.next - vc4->rcl.base;
 374         submit.shader_rec = vc4->shader_rec.base;
 375         submit.shader_rec_size = vc4->shader_rec.next - vc4->shader_rec.base;
 376         submit.shader_rec_count = vc4->shader_rec_count;
 377         submit.uniforms = vc4->uniforms.base;
 378         submit.uniforms_size = vc4->uniforms.next - vc4->uniforms.base;
 379
 380         if (!(vc4_debug & VC4_DEBUG_NORAST)) {
 381                 int ret;
 382
 383 #ifndef USE_VC4_SIMULATOR
 384                 ret = drmIoctl(vc4->fd, DRM_IOCTL_VC4_SUBMIT_CL, &submit);
 385 #else
 386                 ret = vc4_simulator_flush(vc4, &submit);
 387 #endif
 388                 if (ret) {
 389                         fprintf(stderr, "VC4 submit failed\n");
 390                         abort();
 391                 }
 392         }
 393
 394         vc4->last_emit_seqno = submit.seqno;
 395
 396         if (vc4_debug & VC4_DEBUG_ALWAYS_SYNC) {
 397                 if (!vc4_wait_seqno(vc4->screen, vc4->last_emit_seqno,
 398                                     PIPE_TIMEOUT_INFINITE)) {
 399                         fprintf(stderr, "Wait failed.\n");
 400                         abort();
 401                 }
 402         }
 403
 404         vc4_draw_reset(vc4);
 405 }
 406
 407 static void
 408 vc4_pipe_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
 409                unsigned flags)
 410 {
 411         struct vc4_context *vc4 = vc4_context(pctx);
 412
 413         vc4_flush(pctx);
 414
 415         if (fence) {
 416                 struct vc4_fence *f = vc4_fence_create(vc4->screen,
 417                                                        vc4->last_emit_seqno);
 418                 *fence = (struct pipe_fence_handle *)f;
 419         }
 420 }
 421
 422 /**
 423  * Flushes the current command lists if they reference the given BO.
 424  *
 425  * This helps avoid flushing the command buffers when unnecessary.
 426  */
 427 bool
 428 vc4_cl_references_bo(struct pipe_context *pctx, struct vc4_bo *bo)
 429 {
 430         struct vc4_context *vc4 = vc4_context(pctx);
 431
 432         if (!vc4->needs_flush)
 433                 return false;
 434
 435         /* Walk all the referenced BOs in the drawing command list to see if
 436          * they match.
 437          */
 438         struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
 439         for (int i = 0; i < (vc4->bo_handles.next -
 440                              vc4->bo_handles.base) / 4; i++) {
 441                 if (referenced_bos[i] == bo) {
 442                         return true;
 443                 }
 444         }
 445
 446         /* Also check for the Z/color buffers, since the references to those
 447          * are only added immediately before submit.
 448          */
 449         struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
 450         if (csurf) {
 451                 struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
 452                 if (ctex->bo == bo) {
 453                         return true;
 454                 }
 455         }
 456
 457         struct vc4_surface *zsurf = vc4_surface(vc4->framebuffer.zsbuf);
 458         if (zsurf) {
 459                 struct vc4_resource *ztex =
 460                         vc4_resource(zsurf->base.texture);
 461                 if (ztex->bo == bo) {
 462                         return true;
 463                 }
 464         }
 465
 466         return false;
 467 }
 468
 469 static void
 470 vc4_invalidate_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
 471 {
 472         struct vc4_context *vc4 = vc4_context(pctx);
 473         struct pipe_surface *zsurf = vc4->framebuffer.zsbuf;
 474
 475         if (zsurf && zsurf->texture == prsc)
 476                 vc4->resolve &= ~(PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL);
 477 }
 478
 479 static void
 480 vc4_context_destroy(struct pipe_context *pctx)
 481 {
 482         struct vc4_context *vc4 = vc4_context(pctx);
 483
 484         if (vc4->blitter)
 485                 util_blitter_destroy(vc4->blitter);
 486
 487         if (vc4->primconvert)
 488                 util_primconvert_destroy(vc4->primconvert);
 489
 490         util_slab_destroy(&vc4->transfer_pool);
 491
 492         pipe_surface_reference(&vc4->framebuffer.cbufs[0], NULL);
 493         pipe_surface_reference(&vc4->framebuffer.zsbuf, NULL);
 494         vc4_bo_unreference(&vc4->tile_alloc);
 495         vc4_bo_unreference(&vc4->tile_state);
 496
 497         vc4_program_fini(pctx);
 498
 499         ralloc_free(vc4);
 500 }
 501
 502 struct pipe_context *
 503 vc4_context_create(struct pipe_screen *pscreen, void *priv)
 504 {
 505         struct vc4_screen *screen = vc4_screen(pscreen);
 506         struct vc4_context *vc4;
 507
 508         /* Prevent dumping of the shaders built during context setup. */
 509         uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
 510         vc4_debug &= ~VC4_DEBUG_SHADERDB;
 511
 512         vc4 = rzalloc(NULL, struct vc4_context);
 513         if (vc4 == NULL)
 514                 return NULL;
 515         struct pipe_context *pctx = &vc4->base;
 516
 517         vc4->screen = screen;
 518
 519         pctx->screen = pscreen;
 520         pctx->priv = priv;
 521         pctx->destroy = vc4_context_destroy;
 522         pctx->flush = vc4_pipe_flush;
 523         pctx->invalidate_resource = vc4_invalidate_resource;
 524
 525         vc4_draw_init(pctx);
 526         vc4_state_init(pctx);
 527         vc4_program_init(pctx);
 528         vc4_query_init(pctx);
 529         vc4_resource_context_init(pctx);
 530
 531         vc4_init_cl(vc4, &vc4->bcl);
 532         vc4_init_cl(vc4, &vc4->rcl);
 533         vc4_init_cl(vc4, &vc4->shader_rec);
 534         vc4_init_cl(vc4, &vc4->uniforms);
 535         vc4_init_cl(vc4, &vc4->bo_handles);
 536         vc4_init_cl(vc4, &vc4->bo_pointers);
 537         vc4_draw_reset(vc4);
 538
 539         vc4->fd = screen->fd;
 540
 541         util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer),
 542                          16, UTIL_SLAB_SINGLETHREADED);
 543         vc4->blitter = util_blitter_create(pctx);
 544         if (!vc4->blitter)
 545                 goto fail;
 546
 547         vc4->primconvert = util_primconvert_create(pctx,
 548                                                    (1 << PIPE_PRIM_QUADS) - 1);
 549         if (!vc4->primconvert)
 550                 goto fail;
 551
 552         vc4_debug |= saved_shaderdb_flag;
 553
 554         return &vc4->base;
 555
 556 fail:
 557         pctx->destroy(pctx);
 558         return NULL;
 559 }