src/gallium/drivers/vc4/vc4_context.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <xf86drm.h>
  25 #include <err.h>
  26
  27 #include "pipe/p_defines.h"
  28 #include "util/ralloc.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_blitter.h"
  32 #include "indices/u_primconvert.h"
  33 #include "pipe/p_screen.h"
  34
  35 #include "vc4_screen.h"
  36 #include "vc4_context.h"
  37 #include "vc4_resource.h"
  38
  39 /**
  40  * Emits a no-op STORE_TILE_BUFFER_GENERAL.
  41  *
  42  * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of
  43  * some sort before another load is triggered.
  44  */
  45 static void
  46 vc4_store_before_load(struct vc4_context *vc4, bool *coords_emitted)
  47 {
  48         if (!*coords_emitted)
  49                 return;
  50
  51         cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
  52         cl_u8(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE);
  53         cl_u8(&vc4->rcl, (VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
  54                           VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
  55                           VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR));
  56         cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */
  57
  58         *coords_emitted = false;
  59 }
  60
  61 /**
  62  * Emits a PACKET_TILE_COORDINATES if one isn't already pending.
  63  *
  64  * The tile coordinates packet triggers a pending load if there is one, are
  65  * used for clipping during rendering, and determine where loads/stores happen
  66  * relative to their base address.
  67  */
  68 static void
  69 vc4_tile_coordinates(struct vc4_context *vc4, uint32_t x, uint32_t y,
  70                        bool *coords_emitted)
  71 {
  72         if (*coords_emitted)
  73                 return;
  74
  75         cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
  76         cl_u8(&vc4->rcl, x);
  77         cl_u8(&vc4->rcl, y);
  78
  79         *coords_emitted = true;
  80 }
  81
  82 static void
  83 vc4_setup_rcl(struct vc4_context *vc4)
  84 {
  85         struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
  86         struct vc4_resource *ctex = csurf ? vc4_resource(csurf->base.texture) : NULL;
  87         struct vc4_surface *zsurf = vc4_surface(vc4->framebuffer.zsbuf);
  88         struct vc4_resource *ztex = zsurf ? vc4_resource(zsurf->base.texture) : NULL;
  89
  90         if (!csurf)
  91                 vc4->resolve &= ~PIPE_CLEAR_COLOR0;
  92         if (!zsurf)
  93                 vc4->resolve &= ~(PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL);
  94         uint32_t resolve_uncleared = vc4->resolve & ~vc4->cleared;
  95         uint32_t width = vc4->framebuffer.width;
  96         uint32_t height = vc4->framebuffer.height;
  97         uint32_t stride_in_tiles = align(width, 64) / 64;
  98
  99         assert(vc4->draw_min_x != ~0 && vc4->draw_min_y != ~0);
 100         uint32_t min_x_tile = vc4->draw_min_x / 64;
 101         uint32_t min_y_tile = vc4->draw_min_y / 64;
 102         uint32_t max_x_tile = (vc4->draw_max_x - 1) / 64;
 103         uint32_t max_y_tile = (vc4->draw_max_y - 1) / 64;
 104         uint32_t xtiles = max_x_tile - min_x_tile + 1;
 105         uint32_t ytiles = max_y_tile - min_y_tile + 1;
 106
 107 #if 0
 108         fprintf(stderr, "RCL: resolve 0x%x clear 0x%x resolve uncleared 0x%x\n",
 109                 vc4->resolve,
 110                 vc4->cleared,
 111                 resolve_uncleared);
 112 #endif
 113
 114         uint32_t reloc_size = 9;
 115         uint32_t clear_size = 14;
 116         uint32_t config_size = 11 + reloc_size;
 117         uint32_t loadstore_size = 7 + reloc_size;
 118         uint32_t tilecoords_size = 3;
 119         uint32_t branch_size = 5 + reloc_size;
 120         uint32_t color_store_size = 1;
 121         uint32_t semaphore_size = 1;
 122         cl_ensure_space(&vc4->rcl,
 123                         clear_size +
 124                         config_size +
 125                         loadstore_size +
 126                         semaphore_size +
 127                         xtiles * ytiles * (loadstore_size * 4 +
 128                                            tilecoords_size * 3 +
 129                                            branch_size +
 130                                            color_store_size));
 131
 132         cl_u8(&vc4->rcl, VC4_PACKET_CLEAR_COLORS);
 133         cl_u32(&vc4->rcl, vc4->clear_color[0]);
 134         cl_u32(&vc4->rcl, vc4->clear_color[1]);
 135         cl_u32(&vc4->rcl, vc4->clear_depth);
 136         cl_u8(&vc4->rcl, vc4->clear_stencil);
 137
 138         /* The rendering mode config determines the pointer that's used for
 139          * VC4_PACKET_STORE_MS_TILE_BUFFER address computations.  The kernel
 140          * could handle a no-relocation rendering mode config and deny those
 141          * packets, but instead we just tell the kernel we're doing our color
 142          * rendering to the Z buffer, and just don't emit any of those
 143          * packets.
 144          */
 145         struct vc4_surface *render_surf = csurf ? csurf : zsurf;
 146         struct vc4_resource *render_tex = vc4_resource(render_surf->base.texture);
 147         cl_start_reloc(&vc4->rcl, 1);
 148         cl_u8(&vc4->rcl, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
 149         cl_reloc(vc4, &vc4->rcl, render_tex->bo, render_surf->offset);
 150         cl_u16(&vc4->rcl, width);
 151         cl_u16(&vc4->rcl, height);
 152         cl_u16(&vc4->rcl, ((render_surf->tiling <<
 153                             VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) |
 154                            (vc4_rt_format_is_565(render_surf->base.format) ?
 155                             VC4_RENDER_CONFIG_FORMAT_BGR565 :
 156                             VC4_RENDER_CONFIG_FORMAT_RGBA8888)));
 157
 158         /* The tile buffer normally gets cleared when the previous tile is
 159          * stored.  If the clear values changed between frames, then the tile
 160          * buffer has stale clear values in it, so we have to do a store in
 161          * None mode (no writes) so that we trigger the tile buffer clear.
 162          *
 163          * Excess clearing is only a performance cost, since per-tile contents
 164          * will be loaded/stored in the loop below.
 165          */
 166         if (vc4->cleared & (PIPE_CLEAR_COLOR0 |
 167                             PIPE_CLEAR_DEPTH |
 168                             PIPE_CLEAR_STENCIL)) {
 169                 cl_u8(&vc4->rcl, VC4_PACKET_TILE_COORDINATES);
 170                 cl_u8(&vc4->rcl, 0);
 171                 cl_u8(&vc4->rcl, 0);
 172
 173                 cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
 174                 cl_u16(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE);
 175                 cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */
 176         }
 177
 178         uint32_t color_hindex = ctex ? vc4_gem_hindex(vc4, ctex->bo) : 0;
 179         uint32_t depth_hindex = ztex ? vc4_gem_hindex(vc4, ztex->bo) : 0;
 180         uint32_t tile_alloc_hindex = vc4_gem_hindex(vc4, vc4->tile_alloc);
 181
 182         for (int y = min_y_tile; y <= max_y_tile; y++) {
 183                 for (int x = min_x_tile; x <= max_x_tile; x++) {
 184                         bool end_of_frame = (x == max_x_tile &&
 185                                              y == max_y_tile);
 186                         bool coords_emitted = false;
 187
 188                         /* Note that the load doesn't actually occur until the
 189                          * tile coords packet is processed, and only one load
 190                          * may be outstanding at a time.
 191                          */
 192                         if (resolve_uncleared & PIPE_CLEAR_COLOR) {
 193                                 vc4_store_before_load(vc4, &coords_emitted);
 194
 195                                 cl_start_reloc(&vc4->rcl, 1);
 196                                 cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
 197                                 cl_u8(&vc4->rcl,
 198                                       VC4_LOADSTORE_TILE_BUFFER_COLOR |
 199                                       (csurf->tiling <<
 200                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 201                                 cl_u8(&vc4->rcl,
 202                                       vc4_rt_format_is_565(csurf->base.format) ?
 203                                       VC4_LOADSTORE_TILE_BUFFER_BGR565 :
 204                                       VC4_LOADSTORE_TILE_BUFFER_RGBA8888);
 205                                 cl_reloc_hindex(&vc4->rcl, color_hindex,
 206                                                 csurf->offset);
 207
 208                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 209                         }
 210
 211                         if (resolve_uncleared & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 212                                 vc4_store_before_load(vc4, &coords_emitted);
 213
 214                                 cl_start_reloc(&vc4->rcl, 1);
 215                                 cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
 216                                 cl_u8(&vc4->rcl,
 217                                       VC4_LOADSTORE_TILE_BUFFER_ZS |
 218                                       (zsurf->tiling <<
 219                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 220                                 cl_u8(&vc4->rcl, 0);
 221                                 cl_reloc_hindex(&vc4->rcl, depth_hindex,
 222                                                 zsurf->offset);
 223
 224                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 225                         }
 226
 227                         /* Clipping depends on tile coordinates having been
 228                          * emitted, so make sure it's happened even if
 229                          * everything was cleared to start.
 230                          */
 231                         vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 232
 233                         /* Wait for the binner before jumping to the first
 234                          * tile's lists.
 235                          */
 236                         if (x == min_x_tile && y == min_y_tile)
 237                                 cl_u8(&vc4->rcl, VC4_PACKET_WAIT_ON_SEMAPHORE);
 238
 239                         cl_start_reloc(&vc4->rcl, 1);
 240                         cl_u8(&vc4->rcl, VC4_PACKET_BRANCH_TO_SUB_LIST);
 241                         cl_reloc_hindex(&vc4->rcl, tile_alloc_hindex,
 242                                         (y * stride_in_tiles + x) * 32);
 243
 244                         if (vc4->resolve & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 245                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 246
 247                                 cl_start_reloc(&vc4->rcl, 1);
 248                                 cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
 249                                 cl_u8(&vc4->rcl,
 250                                       VC4_LOADSTORE_TILE_BUFFER_ZS |
 251                                       (zsurf->tiling <<
 252                                        VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
 253                                 cl_u8(&vc4->rcl,
 254                                       VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR);
 255                                 cl_reloc_hindex(&vc4->rcl, depth_hindex,
 256                                                 zsurf->offset |
 257                                                 ((end_of_frame &&
 258                                                   !(vc4->resolve & PIPE_CLEAR_COLOR0)) ?
 259                                                  VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
 260
 261                                 coords_emitted = false;
 262                         }
 263
 264                         if (vc4->resolve & PIPE_CLEAR_COLOR0) {
 265                                 vc4_tile_coordinates(vc4, x, y, &coords_emitted);
 266                                 if (end_of_frame) {
 267                                         cl_u8(&vc4->rcl,
 268                                               VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);
 269                                 } else {
 270                                         cl_u8(&vc4->rcl,
 271                                               VC4_PACKET_STORE_MS_TILE_BUFFER);
 272                                 }
 273
 274                                 coords_emitted = false;
 275                         }
 276
 277                         /* One of the bits needs to have been set that would
 278                          * have triggered an EOF.
 279                          */
 280                         assert(vc4->resolve & (PIPE_CLEAR_COLOR0 |
 281                                                PIPE_CLEAR_DEPTH |
 282                                                PIPE_CLEAR_STENCIL));
 283                         /* Any coords emitted must also have been consumed by
 284                          * a store.
 285                          */
 286                         assert(!coords_emitted);
 287                 }
 288         }
 289
 290         if (vc4->resolve & PIPE_CLEAR_COLOR0)
 291                 ctex->writes++;
 292
 293         if (vc4->resolve & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))
 294                 ztex->writes++;
 295 }
 296
 297 static void
 298 vc4_draw_reset(struct vc4_context *vc4)
 299 {
 300         struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
 301         for (int i = 0; i < (vc4->bo_handles.next -
 302                              vc4->bo_handles.base) / 4; i++) {
 303                 vc4_bo_unreference(&referenced_bos[i]);
 304         }
 305         vc4_reset_cl(&vc4->bcl);
 306         vc4_reset_cl(&vc4->rcl);
 307         vc4_reset_cl(&vc4->shader_rec);
 308         vc4_reset_cl(&vc4->uniforms);
 309         vc4_reset_cl(&vc4->bo_handles);
 310         vc4_reset_cl(&vc4->bo_pointers);
 311         vc4->shader_rec_count = 0;
 312
 313         vc4->needs_flush = false;
 314         vc4->draw_call_queued = false;
 315
 316         /* We have no hardware context saved between our draw calls, so we
 317          * need to flag the next draw as needing all state emitted.  Emitting
 318          * all state at the start of our draws is also what ensures that we
 319          * return to the state we need after a previous tile has finished.
 320          */
 321         vc4->dirty = ~0;
 322         vc4->resolve = 0;
 323         vc4->cleared = 0;
 324
 325         vc4->draw_min_x = ~0;
 326         vc4->draw_min_y = ~0;
 327         vc4->draw_max_x = 0;
 328         vc4->draw_max_y = 0;
 329 }
 330
 331 void
 332 vc4_flush(struct pipe_context *pctx)
 333 {
 334         struct vc4_context *vc4 = vc4_context(pctx);
 335
 336         if (!vc4->needs_flush)
 337                 return;
 338
 339         /* The RCL setup would choke if the draw bounds cause no drawing, so
 340          * just drop the drawing if that's the case.
 341          */
 342         if (vc4->draw_max_x <= vc4->draw_min_x ||
 343             vc4->draw_max_y <= vc4->draw_min_y) {
 344                 vc4_draw_reset(vc4);
 345                 return;
 346         }
 347
 348         /* Increment the semaphore indicating that binning is done and
 349          * unblocking the render thread.  Note that this doesn't act until the
 350          * FLUSH completes.
 351          */
 352         cl_u8(&vc4->bcl, VC4_PACKET_INCREMENT_SEMAPHORE);
 353         /* The FLUSH caps all of our bin lists with a VC4_PACKET_RETURN. */
 354         cl_u8(&vc4->bcl, VC4_PACKET_FLUSH);
 355
 356         vc4_setup_rcl(vc4);
 357
 358         if (vc4_debug & VC4_DEBUG_CL) {
 359                 fprintf(stderr, "BCL:\n");
 360                 vc4_dump_cl(vc4->bcl.base, vc4->bcl.next - vc4->bcl.base, false);
 361                 fprintf(stderr, "RCL:\n");
 362                 vc4_dump_cl(vc4->rcl.base, vc4->rcl.next - vc4->rcl.base, true);
 363         }
 364
 365         struct drm_vc4_submit_cl submit;
 366         memset(&submit, 0, sizeof(submit));
 367
 368         submit.bo_handles = (uintptr_t)vc4->bo_handles.base;
 369         submit.bo_handle_count = (vc4->bo_handles.next -
 370                                   vc4->bo_handles.base) / 4;
 371         submit.bin_cl = (uintptr_t)vc4->bcl.base;
 372         submit.bin_cl_size = vc4->bcl.next - vc4->bcl.base;
 373         submit.render_cl = (uintptr_t)vc4->rcl.base;
 374         submit.render_cl_size = vc4->rcl.next - vc4->rcl.base;
 375         submit.shader_rec = (uintptr_t)vc4->shader_rec.base;
 376         submit.shader_rec_size = vc4->shader_rec.next - vc4->shader_rec.base;
 377         submit.shader_rec_count = vc4->shader_rec_count;
 378         submit.uniforms = (uintptr_t)vc4->uniforms.base;
 379         submit.uniforms_size = vc4->uniforms.next - vc4->uniforms.base;
 380
 381         if (!(vc4_debug & VC4_DEBUG_NORAST)) {
 382                 int ret;
 383
 384 #ifndef USE_VC4_SIMULATOR
 385                 ret = drmIoctl(vc4->fd, DRM_IOCTL_VC4_SUBMIT_CL, &submit);
 386 #else
 387                 ret = vc4_simulator_flush(vc4, &submit);
 388 #endif
 389                 if (ret) {
 390                         fprintf(stderr, "VC4 submit failed\n");
 391                         abort();
 392                 }
 393         }
 394
 395         vc4->last_emit_seqno = submit.seqno;
 396
 397         if (vc4_debug & VC4_DEBUG_ALWAYS_SYNC) {
 398                 if (!vc4_wait_seqno(vc4->screen, vc4->last_emit_seqno,
 399                                     PIPE_TIMEOUT_INFINITE)) {
 400                         fprintf(stderr, "Wait failed.\n");
 401                         abort();
 402                 }
 403         }
 404
 405         vc4_draw_reset(vc4);
 406 }
 407
 408 static void
 409 vc4_pipe_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence,
 410                unsigned flags)
 411 {
 412         struct vc4_context *vc4 = vc4_context(pctx);
 413
 414         vc4_flush(pctx);
 415
 416         if (fence) {
 417                 struct vc4_fence *f = vc4_fence_create(vc4->screen,
 418                                                        vc4->last_emit_seqno);
 419                 *fence = (struct pipe_fence_handle *)f;
 420         }
 421 }
 422
 423 /**
 424  * Flushes the current command lists if they reference the given BO.
 425  *
 426  * This helps avoid flushing the command buffers when unnecessary.
 427  */
 428 bool
 429 vc4_cl_references_bo(struct pipe_context *pctx, struct vc4_bo *bo)
 430 {
 431         struct vc4_context *vc4 = vc4_context(pctx);
 432
 433         if (!vc4->needs_flush)
 434                 return false;
 435
 436         /* Walk all the referenced BOs in the drawing command list to see if
 437          * they match.
 438          */
 439         struct vc4_bo **referenced_bos = vc4->bo_pointers.base;
 440         for (int i = 0; i < (vc4->bo_handles.next -
 441                              vc4->bo_handles.base) / 4; i++) {
 442                 if (referenced_bos[i] == bo) {
 443                         return true;
 444                 }
 445         }
 446
 447         /* Also check for the Z/color buffers, since the references to those
 448          * are only added immediately before submit.
 449          */
 450         struct vc4_surface *csurf = vc4_surface(vc4->framebuffer.cbufs[0]);
 451         if (csurf) {
 452                 struct vc4_resource *ctex = vc4_resource(csurf->base.texture);
 453                 if (ctex->bo == bo) {
 454                         return true;
 455                 }
 456         }
 457
 458         struct vc4_surface *zsurf = vc4_surface(vc4->framebuffer.zsbuf);
 459         if (zsurf) {
 460                 struct vc4_resource *ztex =
 461                         vc4_resource(zsurf->base.texture);
 462                 if (ztex->bo == bo) {
 463                         return true;
 464                 }
 465         }
 466
 467         return false;
 468 }
 469
 470 static void
 471 vc4_invalidate_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
 472 {
 473         struct vc4_context *vc4 = vc4_context(pctx);
 474         struct pipe_surface *zsurf = vc4->framebuffer.zsbuf;
 475
 476         if (zsurf && zsurf->texture == prsc)
 477                 vc4->resolve &= ~(PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL);
 478 }
 479
 480 static void
 481 vc4_context_destroy(struct pipe_context *pctx)
 482 {
 483         struct vc4_context *vc4 = vc4_context(pctx);
 484
 485         if (vc4->blitter)
 486                 util_blitter_destroy(vc4->blitter);
 487
 488         if (vc4->primconvert)
 489                 util_primconvert_destroy(vc4->primconvert);
 490
 491         util_slab_destroy(&vc4->transfer_pool);
 492
 493         pipe_surface_reference(&vc4->framebuffer.cbufs[0], NULL);
 494         pipe_surface_reference(&vc4->framebuffer.zsbuf, NULL);
 495         vc4_bo_unreference(&vc4->tile_alloc);
 496         vc4_bo_unreference(&vc4->tile_state);
 497
 498         vc4_program_fini(pctx);
 499
 500         ralloc_free(vc4);
 501 }
 502
 503 struct pipe_context *
 504 vc4_context_create(struct pipe_screen *pscreen, void *priv)
 505 {
 506         struct vc4_screen *screen = vc4_screen(pscreen);
 507         struct vc4_context *vc4;
 508
 509         /* Prevent dumping of the shaders built during context setup. */
 510         uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
 511         vc4_debug &= ~VC4_DEBUG_SHADERDB;
 512
 513         vc4 = rzalloc(NULL, struct vc4_context);
 514         if (vc4 == NULL)
 515                 return NULL;
 516         struct pipe_context *pctx = &vc4->base;
 517
 518         vc4->screen = screen;
 519
 520         pctx->screen = pscreen;
 521         pctx->priv = priv;
 522         pctx->destroy = vc4_context_destroy;
 523         pctx->flush = vc4_pipe_flush;
 524         pctx->invalidate_resource = vc4_invalidate_resource;
 525
 526         vc4_draw_init(pctx);
 527         vc4_state_init(pctx);
 528         vc4_program_init(pctx);
 529         vc4_query_init(pctx);
 530         vc4_resource_context_init(pctx);
 531
 532         vc4_init_cl(vc4, &vc4->bcl);
 533         vc4_init_cl(vc4, &vc4->rcl);
 534         vc4_init_cl(vc4, &vc4->shader_rec);
 535         vc4_init_cl(vc4, &vc4->uniforms);
 536         vc4_init_cl(vc4, &vc4->bo_handles);
 537         vc4_init_cl(vc4, &vc4->bo_pointers);
 538         vc4_draw_reset(vc4);
 539
 540         vc4->fd = screen->fd;
 541
 542         util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer),
 543                          16, UTIL_SLAB_SINGLETHREADED);
 544         vc4->blitter = util_blitter_create(pctx);
 545         if (!vc4->blitter)
 546                 goto fail;
 547
 548         vc4->primconvert = util_primconvert_create(pctx,
 549                                                    (1 << PIPE_PRIM_QUADS) - 1);
 550         if (!vc4->primconvert)
 551                 goto fail;
 552
 553         vc4_debug |= saved_shaderdb_flag;
 554
 555         return &vc4->base;
 556
 557 fail:
 558         pctx->destroy(pctx);
 559         return NULL;
 560 }