src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/slab.h"
  33 #include "xf86drm.h"
  34
  35 #define __user
  36 #include "vc4_drm.h"
  37 #include "vc4_bufmgr.h"
  38 #include "vc4_resource.h"
  39 #include "vc4_cl.h"
  40 #include "vc4_qir.h"
  41
  42 #ifndef DRM_VC4_PARAM_SUPPORTS_ETC1
  43 #define DRM_VC4_PARAM_SUPPORTS_ETC1             4
  44 #endif
  45 #ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS
  46 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS      5
  47 #endif
  48
  49 #ifdef USE_VC4_SIMULATOR
  50 #define using_vc4_simulator true
  51 #else
  52 #define using_vc4_simulator false
  53 #endif
  54
  55 #define VC4_DIRTY_BLEND         (1 <<  0)
  56 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  57 #define VC4_DIRTY_ZSA           (1 <<  2)
  58 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  59 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  60
  61 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  62 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  63 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  64 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  65 #define VC4_DIRTY_STIPPLE       (1 << 11)
  66 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  67 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  68 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  69 #define VC4_DIRTY_VTXBUF        (1 << 15)
  70 #define VC4_DIRTY_INDEXBUF      (1 << 16)
  71 #define VC4_DIRTY_SCISSOR       (1 << 17)
  72 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  73 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
  74 #define VC4_DIRTY_CLIP          (1 << 20)
  75 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
  76 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
  77 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
  78 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
  79 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
  80 #define VC4_DIRTY_FS_INPUTS     (1 << 26)
  81
  82 struct vc4_sampler_view {
  83         struct pipe_sampler_view base;
  84         uint32_t texture_p0;
  85         uint32_t texture_p1;
  86         bool force_first_level;
  87 };
  88
  89 struct vc4_sampler_state {
  90         struct pipe_sampler_state base;
  91         uint32_t texture_p1;
  92 };
  93
  94 struct vc4_texture_stateobj {
  95         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  96         unsigned num_textures;
  97         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  98         unsigned num_samplers;
  99 };
 100
 101 struct vc4_shader_uniform_info {
 102         enum quniform_contents *contents;
 103         uint32_t *data;
 104         uint32_t count;
 105         uint32_t num_texture_samples;
 106 };
 107
 108 struct vc4_uncompiled_shader {
 109         /** A name for this program, so you can track it in shader-db output. */
 110         uint32_t program_id;
 111         /** How many variants of this program were compiled, for shader-db. */
 112         uint32_t compiled_variant_count;
 113         struct pipe_shader_state base;
 114 };
 115
 116 struct vc4_ubo_range {
 117         /**
 118          * offset in bytes from the start of the ubo where this range is
 119          * uploaded.
 120          *
 121          * Only set once used is set.
 122          */
 123         uint32_t dst_offset;
 124
 125         /**
 126          * offset in bytes from the start of the gallium uniforms where the
 127          * data comes from.
 128          */
 129         uint32_t src_offset;
 130
 131         /** size in bytes of this ubo range */
 132         uint32_t size;
 133 };
 134
 135 struct vc4_fs_inputs {
 136         /**
 137          * Array of the meanings of the VPM inputs this shader needs.
 138          *
 139          * It doesn't include those that aren't part of the VPM, like
 140          * point/line coordinates.
 141          */
 142         struct vc4_varying_slot *input_slots;
 143         uint32_t num_inputs;
 144 };
 145
 146 struct vc4_compiled_shader {
 147         uint64_t program_id;
 148         struct vc4_bo *bo;
 149
 150         struct vc4_shader_uniform_info uniforms;
 151
 152         struct vc4_ubo_range *ubo_ranges;
 153         uint32_t num_ubo_ranges;
 154         uint32_t ubo_size;
 155         /**
 156          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
 157          * uniforms have to be rewritten (and therefore the shader state
 158          * reemitted).
 159          */
 160         uint32_t uniform_dirty_bits;
 161
 162         /** bitmask of which inputs are color inputs, for flat shade handling. */
 163         uint32_t color_inputs;
 164
 165         bool disable_early_z;
 166
 167         /* Set if the compile failed, likely due to register allocation
 168          * failure.  In this case, we have no shader to run and should not try
 169          * to do any draws.
 170          */
 171         bool failed;
 172
 173         bool fs_threaded;
 174
 175         uint8_t num_inputs;
 176
 177         /* Byte offsets for the start of the vertex attributes 0-7, and the
 178          * total size as "attribute" 8.
 179          */
 180         uint8_t vattr_offsets[9];
 181         uint8_t vattrs_live;
 182
 183         const struct vc4_fs_inputs *fs_inputs;
 184 };
 185
 186 struct vc4_program_stateobj {
 187         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
 188         struct vc4_compiled_shader *cs, *vs, *fs;
 189 };
 190
 191 struct vc4_constbuf_stateobj {
 192         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 193         uint32_t enabled_mask;
 194         uint32_t dirty_mask;
 195 };
 196
 197 struct vc4_vertexbuf_stateobj {
 198         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 199         unsigned count;
 200         uint32_t enabled_mask;
 201         uint32_t dirty_mask;
 202 };
 203
 204 struct vc4_vertex_stateobj {
 205         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 206         unsigned num_elements;
 207 };
 208
 209 /* Hash table key for vc4->jobs */
 210 struct vc4_job_key {
 211         struct pipe_surface *cbuf;
 212         struct pipe_surface *zsbuf;
 213 };
 214
 215 /**
 216  * A complete bin/render job.
 217  *
 218  * This is all of the state necessary to submit a bin/render to the kernel.
 219  * We want to be able to have multiple in progress at a time, so that we don't
 220  * need to flush an existing CL just to switch to rendering to a new render
 221  * target (which would mean reading back from the old render target when
 222  * starting to render to it again).
 223  */
 224 struct vc4_job {
 225         struct vc4_cl bcl;
 226         struct vc4_cl shader_rec;
 227         struct vc4_cl uniforms;
 228         struct vc4_cl bo_handles;
 229         struct vc4_cl bo_pointers;
 230         uint32_t shader_rec_count;
 231
 232         /** @{ Surfaces to submit rendering for. */
 233         struct pipe_surface *color_read;
 234         struct pipe_surface *color_write;
 235         struct pipe_surface *zs_read;
 236         struct pipe_surface *zs_write;
 237         struct pipe_surface *msaa_color_write;
 238         struct pipe_surface *msaa_zs_write;
 239         /** @} */
 240         /** @{
 241          * Bounding box of the scissor across all queued drawing.
 242          *
 243          * Note that the max values are exclusive.
 244          */
 245         uint32_t draw_min_x;
 246         uint32_t draw_min_y;
 247         uint32_t draw_max_x;
 248         uint32_t draw_max_y;
 249         /** @} */
 250         /** @{
 251          * Width/height of the color framebuffer being rendered to,
 252          * for VC4_TILE_RENDERING_MODE_CONFIG.
 253         */
 254         uint32_t draw_width;
 255         uint32_t draw_height;
 256         /** @} */
 257         /** @{ Tile information, depending on MSAA and float color buffer. */
 258         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 259         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 260
 261         uint32_t tile_width; /** @< Width of a tile. */
 262         uint32_t tile_height; /** @< Height of a tile. */
 263         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 264         bool msaa;
 265         /** @} */
 266
 267         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 268          * first rendering.
 269          */
 270         uint32_t cleared;
 271         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 272          * (either clears or draws).
 273          */
 274         uint32_t resolve;
 275         uint32_t clear_color[2];
 276         uint32_t clear_depth; /**< 24-bit unorm depth */
 277         uint8_t clear_stencil;
 278
 279         /**
 280          * Set if some drawing (triangles, blits, or just a glClear()) has
 281          * been done to the FBO, meaning that we need to
 282          * DRM_IOCTL_VC4_SUBMIT_CL.
 283          */
 284         bool needs_flush;
 285
 286         /**
 287          * Number of draw calls (not counting full buffer clears) queued in
 288          * the current job.
 289          */
 290         uint32_t draw_calls_queued;
 291
 292         struct vc4_job_key key;
 293 };
 294
 295 struct vc4_context {
 296         struct pipe_context base;
 297
 298         int fd;
 299         struct vc4_screen *screen;
 300
 301         /** The 3D rendering job for the currently bound FBO. */
 302         struct vc4_job *job;
 303
 304         /* Map from struct vc4_job_key to the job for that FBO.
 305          */
 306         struct hash_table *jobs;
 307
 308         /**
 309          * Map from vc4_resource to a job writing to that resource.
 310          *
 311          * Primarily for flushing jobs rendering to textures that are now
 312          * being read from.
 313          */
 314         struct hash_table *write_jobs;
 315
 316         struct slab_child_pool transfer_pool;
 317         struct blitter_context *blitter;
 318
 319         /** bitfield of VC4_DIRTY_* */
 320         uint32_t dirty;
 321
 322         struct primconvert_context *primconvert;
 323
 324         struct hash_table *fs_cache, *vs_cache;
 325         struct set *fs_inputs_set;
 326         uint32_t next_uncompiled_program_id;
 327         uint64_t next_compiled_program_id;
 328
 329         struct ra_regs *regs;
 330         unsigned int reg_class_any[2];
 331         unsigned int reg_class_a_or_b[2];
 332         unsigned int reg_class_a_or_b_or_acc[2];
 333         unsigned int reg_class_r0_r3;
 334         unsigned int reg_class_r4_or_a[2];
 335         unsigned int reg_class_a[2];
 336
 337         uint8_t prim_mode;
 338
 339         /** Maximum index buffer valid for the current shader_rec. */
 340         uint32_t max_index;
 341         /** Last index bias baked into the current shader_rec. */
 342         uint32_t last_index_bias;
 343
 344         /** Seqno of the last CL flush's job. */
 345         uint64_t last_emit_seqno;
 346
 347         struct u_upload_mgr *uploader;
 348
 349         /** @{ Current pipeline state objects */
 350         struct pipe_scissor_state scissor;
 351         struct pipe_blend_state *blend;
 352         struct vc4_rasterizer_state *rasterizer;
 353         struct vc4_depth_stencil_alpha_state *zsa;
 354
 355         struct vc4_texture_stateobj verttex, fragtex;
 356
 357         struct vc4_program_stateobj prog;
 358
 359         struct vc4_vertex_stateobj *vtx;
 360
 361         struct {
 362                 struct pipe_blend_color f;
 363                 uint8_t ub[4];
 364         } blend_color;
 365         struct pipe_stencil_ref stencil_ref;
 366         unsigned sample_mask;
 367         struct pipe_framebuffer_state framebuffer;
 368         struct pipe_poly_stipple stipple;
 369         struct pipe_clip_state clip;
 370         struct pipe_viewport_state viewport;
 371         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 372         struct vc4_vertexbuf_stateobj vertexbuf;
 373         struct pipe_index_buffer indexbuf;
 374         /** @} */
 375 };
 376
 377 struct vc4_rasterizer_state {
 378         struct pipe_rasterizer_state base;
 379
 380         /* VC4_CONFIGURATION_BITS */
 381         uint8_t config_bits[3];
 382
 383         float point_size;
 384
 385         /**
 386          * Half-float (1/8/7 bits) value of polygon offset units for
 387          * VC4_PACKET_DEPTH_OFFSET
 388          */
 389         uint16_t offset_units;
 390         /**
 391          * Half-float (1/8/7 bits) value of polygon offset scale for
 392          * VC4_PACKET_DEPTH_OFFSET
 393          */
 394         uint16_t offset_factor;
 395 };
 396
 397 struct vc4_depth_stencil_alpha_state {
 398         struct pipe_depth_stencil_alpha_state base;
 399
 400         /* VC4_CONFIGURATION_BITS */
 401         uint8_t config_bits[3];
 402
 403         /** Uniforms for stencil state.
 404          *
 405          * Index 0 is either the front config, or the front-and-back config.
 406          * Index 1 is the back config if doing separate back stencil.
 407          * Index 2 is the writemask config if it's not a common mask value.
 408          */
 409         uint32_t stencil_uniforms[3];
 410 };
 411
 412 #define perf_debug(...) do {                            \
 413         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
 414                 fprintf(stderr, __VA_ARGS__);           \
 415 } while (0)
 416
 417 static inline struct vc4_context *
 418 vc4_context(struct pipe_context *pcontext)
 419 {
 420         return (struct vc4_context *)pcontext;
 421 }
 422
 423 static inline struct vc4_sampler_view *
 424 vc4_sampler_view(struct pipe_sampler_view *psview)
 425 {
 426         return (struct vc4_sampler_view *)psview;
 427 }
 428
 429 static inline struct vc4_sampler_state *
 430 vc4_sampler_state(struct pipe_sampler_state *psampler)
 431 {
 432         return (struct vc4_sampler_state *)psampler;
 433 }
 434
 435 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 436                                         void *priv, unsigned flags);
 437 void vc4_draw_init(struct pipe_context *pctx);
 438 void vc4_state_init(struct pipe_context *pctx);
 439 void vc4_program_init(struct pipe_context *pctx);
 440 void vc4_program_fini(struct pipe_context *pctx);
 441 void vc4_query_init(struct pipe_context *pctx);
 442 void vc4_simulator_init(struct vc4_screen *screen);
 443 void vc4_simulator_destroy(struct vc4_screen *screen);
 444 int vc4_simulator_flush(struct vc4_context *vc4,
 445                         struct drm_vc4_submit_cl *args,
 446                         struct vc4_job *job);
 447 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
 448 void vc4_simulator_open_from_handle(int fd, uint32_t winsys_stride,
 449                                     int handle, uint32_t size);
 450
 451 static inline int
 452 vc4_ioctl(int fd, unsigned long request, void *arg)
 453 {
 454         if (using_vc4_simulator)
 455                 return vc4_simulator_ioctl(fd, request, arg);
 456         else
 457                 return drmIoctl(fd, request, arg);
 458 }
 459
 460 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
 461 void vc4_write_uniforms(struct vc4_context *vc4,
 462                         struct vc4_compiled_shader *shader,
 463                         struct vc4_constbuf_stateobj *cb,
 464                         struct vc4_texture_stateobj *texstate);
 465
 466 void vc4_flush(struct pipe_context *pctx);
 467 void vc4_job_init(struct vc4_context *vc4);
 468 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 469                             struct pipe_surface *cbuf,
 470                             struct pipe_surface *zsbuf);
 471 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
 472
 473 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
 474 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
 475                                      struct pipe_resource *prsc);
 476 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
 477                                      struct pipe_resource *prsc);
 478 void vc4_emit_state(struct pipe_context *pctx);
 479 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 480 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 481 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 482
 483 bool vc4_rt_format_supported(enum pipe_format f);
 484 bool vc4_rt_format_is_565(enum pipe_format f);
 485 bool vc4_tex_format_supported(enum pipe_format f);
 486 uint8_t vc4_get_tex_format(enum pipe_format f);
 487 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 488 void vc4_init_query_functions(struct vc4_context *vc4);
 489 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 490 void vc4_blitter_save(struct vc4_context *vc4);
 491 #endif /* VC4_CONTEXT_H */