src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/u_slab.h"
  33
  34 #define __user
  35 #include "vc4_drm.h"
  36 #include "vc4_bufmgr.h"
  37 #include "vc4_resource.h"
  38 #include "vc4_cl.h"
  39 #include "vc4_qir.h"
  40
  41 #ifdef USE_VC4_SIMULATOR
  42 #define using_vc4_simulator true
  43 #else
  44 #define using_vc4_simulator false
  45 #endif
  46
  47 #define VC4_DIRTY_BLEND         (1 <<  0)
  48 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  49 #define VC4_DIRTY_ZSA           (1 <<  2)
  50 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  51 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  52 #define VC4_DIRTY_TEXSTATE      (1 <<  5)
  53
  54 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  55 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  56 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  57 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  58 #define VC4_DIRTY_STIPPLE       (1 << 11)
  59 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  60 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  61 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  62 #define VC4_DIRTY_VTXBUF        (1 << 15)
  63 #define VC4_DIRTY_INDEXBUF      (1 << 16)
  64 #define VC4_DIRTY_SCISSOR       (1 << 17)
  65 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  66 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
  67 #define VC4_DIRTY_CLIP          (1 << 20)
  68 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
  69 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
  70 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
  71 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
  72 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
  73
  74 struct vc4_sampler_view {
  75         struct pipe_sampler_view base;
  76         uint32_t texture_p0;
  77         uint32_t texture_p1;
  78 };
  79
  80 struct vc4_sampler_state {
  81         struct pipe_sampler_state base;
  82         uint32_t texture_p1;
  83 };
  84
  85 struct vc4_texture_stateobj {
  86         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  87         unsigned num_textures;
  88         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  89         unsigned num_samplers;
  90         unsigned dirty_samplers;
  91 };
  92
  93 struct vc4_shader_uniform_info {
  94         enum quniform_contents *contents;
  95         uint32_t *data;
  96         uint32_t count;
  97         uint32_t num_texture_samples;
  98 };
  99
 100 struct vc4_uncompiled_shader {
 101         /** A name for this program, so you can track it in shader-db output. */
 102         uint32_t program_id;
 103         /** How many variants of this program were compiled, for shader-db. */
 104         uint32_t compiled_variant_count;
 105         struct pipe_shader_state base;
 106 };
 107
 108 struct vc4_ubo_range {
 109         /**
 110          * offset in bytes from the start of the ubo where this range is
 111          * uploaded.
 112          *
 113          * Only set once used is set.
 114          */
 115         uint32_t dst_offset;
 116
 117         /**
 118          * offset in bytes from the start of the gallium uniforms where the
 119          * data comes from.
 120          */
 121         uint32_t src_offset;
 122
 123         /** size in bytes of this ubo range */
 124         uint32_t size;
 125 };
 126
 127 struct vc4_compiled_shader {
 128         uint64_t program_id;
 129         struct vc4_bo *bo;
 130
 131         struct vc4_shader_uniform_info uniforms;
 132
 133         struct vc4_ubo_range *ubo_ranges;
 134         uint32_t num_ubo_ranges;
 135         uint32_t ubo_size;
 136         /**
 137          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
 138          * uniforms have to be rewritten (and therefore the shader state
 139          * reemitted).
 140          */
 141         uint32_t uniform_dirty_bits;
 142
 143         /** bitmask of which inputs are color inputs, for flat shade handling. */
 144         uint32_t color_inputs;
 145
 146         uint8_t num_inputs;
 147
 148         /* Byte offsets for the start of the vertex attributes 0-7, and the
 149          * total size as "attribute" 8.
 150          */
 151         uint8_t vattr_offsets[9];
 152         uint8_t vattrs_live;
 153
 154         /**
 155          * Array of the meanings of the VPM inputs this shader needs.
 156          *
 157          * It doesn't include those that aren't part of the VPM, like
 158          * point/line coordinates.
 159          */
 160         struct vc4_varying_slot *input_slots;
 161 };
 162
 163 struct vc4_program_stateobj {
 164         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
 165         struct vc4_compiled_shader *cs, *vs, *fs;
 166         uint8_t num_exports;
 167         /* Indexed by slot.  Special vs exports (position and pointsize) are
 168          * not included in this
 169          */
 170         uint8_t export_linkage[VARYING_SLOT_VAR0 + 8];
 171 };
 172
 173 struct vc4_constbuf_stateobj {
 174         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 175         uint32_t enabled_mask;
 176         uint32_t dirty_mask;
 177 };
 178
 179 struct vc4_vertexbuf_stateobj {
 180         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 181         unsigned count;
 182         uint32_t enabled_mask;
 183         uint32_t dirty_mask;
 184 };
 185
 186 struct vc4_vertex_stateobj {
 187         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 188         unsigned num_elements;
 189 };
 190
 191 struct vc4_context {
 192         struct pipe_context base;
 193
 194         int fd;
 195         struct vc4_screen *screen;
 196
 197         struct vc4_cl bcl;
 198         struct vc4_cl shader_rec;
 199         struct vc4_cl uniforms;
 200         struct vc4_cl bo_handles;
 201         struct vc4_cl bo_pointers;
 202         uint32_t shader_rec_count;
 203
 204         /** @{ Surfaces to submit rendering for. */
 205         struct pipe_surface *color_read;
 206         struct pipe_surface *color_write;
 207         struct pipe_surface *zs_read;
 208         struct pipe_surface *zs_write;
 209         struct pipe_surface *msaa_color_write;
 210         struct pipe_surface *msaa_zs_write;
 211         /** @} */
 212         /** @{
 213          * Bounding box of the scissor across all queued drawing.
 214          *
 215          * Note that the max values are exclusive.
 216          */
 217         uint32_t draw_min_x;
 218         uint32_t draw_min_y;
 219         uint32_t draw_max_x;
 220         uint32_t draw_max_y;
 221         /** @} */
 222         /** @{
 223          * Width/height of the color framebuffer being rendered to,
 224          * for VC4_TILE_RENDERING_MODE_CONFIG.
 225         */
 226         uint32_t draw_width;
 227         uint32_t draw_height;
 228         /** @} */
 229         /** @{ Tile information, depending on MSAA and float color buffer. */
 230         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 231         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 232
 233         uint32_t tile_width; /** @< Width of a tile. */
 234         uint32_t tile_height; /** @< Height of a tile. */
 235         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 236         bool msaa;
 237         /** @} */
 238
 239         struct util_slab_mempool transfer_pool;
 240         struct blitter_context *blitter;
 241
 242         /** bitfield of VC4_DIRTY_* */
 243         uint32_t dirty;
 244         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 245          * first rendering.
 246          */
 247         uint32_t cleared;
 248         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 249          * (either clears or draws).
 250          */
 251         uint32_t resolve;
 252         uint32_t clear_color[2];
 253         uint32_t clear_depth; /**< 24-bit unorm depth */
 254         uint8_t clear_stencil;
 255
 256         /**
 257          * Set if some drawing (triangles, blits, or just a glClear()) has
 258          * been done to the FBO, meaning that we need to
 259          * DRM_IOCTL_VC4_SUBMIT_CL.
 260          */
 261         bool needs_flush;
 262
 263         /**
 264          * Number of draw calls (not counting full buffer clears) queued in
 265          * the current job.
 266          */
 267         uint32_t draw_calls_queued;
 268
 269         /** Maximum index buffer valid for the current shader_rec. */
 270         uint32_t max_index;
 271         /** Last index bias baked into the current shader_rec. */
 272         uint32_t last_index_bias;
 273
 274         struct primconvert_context *primconvert;
 275
 276         struct hash_table *fs_cache, *vs_cache;
 277         uint32_t next_uncompiled_program_id;
 278         uint64_t next_compiled_program_id;
 279
 280         struct ra_regs *regs;
 281         unsigned int reg_class_any;
 282         unsigned int reg_class_a_or_b_or_acc;
 283         unsigned int reg_class_r4_or_a;
 284         unsigned int reg_class_a;
 285
 286         uint8_t prim_mode;
 287
 288         /** Seqno of the last CL flush's job. */
 289         uint64_t last_emit_seqno;
 290
 291         struct u_upload_mgr *uploader;
 292
 293         /** @{ Current pipeline state objects */
 294         struct pipe_scissor_state scissor;
 295         struct pipe_blend_state *blend;
 296         struct vc4_rasterizer_state *rasterizer;
 297         struct vc4_depth_stencil_alpha_state *zsa;
 298
 299         struct vc4_texture_stateobj verttex, fragtex;
 300
 301         struct vc4_program_stateobj prog;
 302
 303         struct vc4_vertex_stateobj *vtx;
 304
 305         struct {
 306                 struct pipe_blend_color f;
 307                 uint8_t ub[4];
 308         } blend_color;
 309         struct pipe_stencil_ref stencil_ref;
 310         unsigned sample_mask;
 311         struct pipe_framebuffer_state framebuffer;
 312         struct pipe_poly_stipple stipple;
 313         struct pipe_clip_state clip;
 314         struct pipe_viewport_state viewport;
 315         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 316         struct vc4_vertexbuf_stateobj vertexbuf;
 317         struct pipe_index_buffer indexbuf;
 318         /** @} */
 319 };
 320
 321 struct vc4_rasterizer_state {
 322         struct pipe_rasterizer_state base;
 323
 324         /* VC4_CONFIGURATION_BITS */
 325         uint8_t config_bits[3];
 326
 327         float point_size;
 328
 329         /**
 330          * Half-float (1/8/7 bits) value of polygon offset units for
 331          * VC4_PACKET_DEPTH_OFFSET
 332          */
 333         uint16_t offset_units;
 334         /**
 335          * Half-float (1/8/7 bits) value of polygon offset scale for
 336          * VC4_PACKET_DEPTH_OFFSET
 337          */
 338         uint16_t offset_factor;
 339 };
 340
 341 struct vc4_depth_stencil_alpha_state {
 342         struct pipe_depth_stencil_alpha_state base;
 343
 344         /* VC4_CONFIGURATION_BITS */
 345         uint8_t config_bits[3];
 346
 347         /** Uniforms for stencil state.
 348          *
 349          * Index 0 is either the front config, or the front-and-back config.
 350          * Index 1 is the back config if doing separate back stencil.
 351          * Index 2 is the writemask config if it's not a common mask value.
 352          */
 353         uint32_t stencil_uniforms[3];
 354 };
 355
 356 #define perf_debug(...) do {                            \
 357         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
 358                 fprintf(stderr, __VA_ARGS__);           \
 359 } while (0)
 360
 361 static inline struct vc4_context *
 362 vc4_context(struct pipe_context *pcontext)
 363 {
 364         return (struct vc4_context *)pcontext;
 365 }
 366
 367 static inline struct vc4_sampler_view *
 368 vc4_sampler_view(struct pipe_sampler_view *psview)
 369 {
 370         return (struct vc4_sampler_view *)psview;
 371 }
 372
 373 static inline struct vc4_sampler_state *
 374 vc4_sampler_state(struct pipe_sampler_state *psampler)
 375 {
 376         return (struct vc4_sampler_state *)psampler;
 377 }
 378
 379 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 380                                         void *priv, unsigned flags);
 381 void vc4_draw_init(struct pipe_context *pctx);
 382 void vc4_state_init(struct pipe_context *pctx);
 383 void vc4_program_init(struct pipe_context *pctx);
 384 void vc4_program_fini(struct pipe_context *pctx);
 385 void vc4_query_init(struct pipe_context *pctx);
 386 void vc4_simulator_init(struct vc4_screen *screen);
 387 int vc4_simulator_flush(struct vc4_context *vc4,
 388                         struct drm_vc4_submit_cl *args);
 389
 390 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
 391 void vc4_write_uniforms(struct vc4_context *vc4,
 392                         struct vc4_compiled_shader *shader,
 393                         struct vc4_constbuf_stateobj *cb,
 394                         struct vc4_texture_stateobj *texstate);
 395
 396 void vc4_flush(struct pipe_context *pctx);
 397 void vc4_job_init(struct vc4_context *vc4);
 398 void vc4_job_submit(struct vc4_context *vc4);
 399 void vc4_job_reset(struct vc4_context *vc4);
 400 bool vc4_cl_references_bo(struct pipe_context *pctx, struct vc4_bo *bo,
 401                           bool include_reads);
 402 void vc4_emit_state(struct pipe_context *pctx);
 403 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 404 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 405 void vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 406
 407 bool vc4_rt_format_supported(enum pipe_format f);
 408 bool vc4_rt_format_is_565(enum pipe_format f);
 409 bool vc4_tex_format_supported(enum pipe_format f);
 410 uint8_t vc4_get_tex_format(enum pipe_format f);
 411 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 412 void vc4_init_query_functions(struct vc4_context *vc4);
 413 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 414 #endif /* VC4_CONTEXT_H */