src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/slab.h"
  33 #include "xf86drm.h"
  34
  35 #define __user
  36 #include "vc4_drm.h"
  37 #include "vc4_bufmgr.h"
  38 #include "vc4_resource.h"
  39 #include "vc4_cl.h"
  40 #include "vc4_qir.h"
  41
  42 #ifndef DRM_VC4_PARAM_SUPPORTS_ETC1
  43 #define DRM_VC4_PARAM_SUPPORTS_ETC1             4
  44 #endif
  45 #ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS
  46 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS      5
  47 #endif
  48
  49 #ifdef USE_VC4_SIMULATOR
  50 #define using_vc4_simulator true
  51 #else
  52 #define using_vc4_simulator false
  53 #endif
  54
  55 #define VC4_DIRTY_BLEND         (1 <<  0)
  56 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  57 #define VC4_DIRTY_ZSA           (1 <<  2)
  58 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  59 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  60
  61 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  62 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  63 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  64 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  65 #define VC4_DIRTY_STIPPLE       (1 << 11)
  66 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  67 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  68 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  69 #define VC4_DIRTY_VTXBUF        (1 << 15)
  70
  71 #define VC4_DIRTY_SCISSOR       (1 << 17)
  72 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  73 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
  74 #define VC4_DIRTY_CLIP          (1 << 20)
  75 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
  76 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
  77 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
  78 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
  79 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
  80 #define VC4_DIRTY_FS_INPUTS     (1 << 26)
  81
  82 struct vc4_sampler_view {
  83         struct pipe_sampler_view base;
  84         uint32_t texture_p0;
  85         uint32_t texture_p1;
  86         bool force_first_level;
  87         /**
  88          * Resource containing the actual texture that will be sampled.
  89          *
  90          * We may need to rebase the .base.texture resource to work around the
  91          * lack of GL_TEXTURE_BASE_LEVEL, or to upload the texture as tiled.
  92          */
  93         struct pipe_resource *texture;
  94 };
  95
  96 struct vc4_sampler_state {
  97         struct pipe_sampler_state base;
  98         uint32_t texture_p1;
  99 };
 100
 101 struct vc4_texture_stateobj {
 102         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
 103         unsigned num_textures;
 104         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
 105         unsigned num_samplers;
 106 };
 107
 108 struct vc4_shader_uniform_info {
 109         enum quniform_contents *contents;
 110         uint32_t *data;
 111         uint32_t count;
 112         uint32_t num_texture_samples;
 113 };
 114
 115 struct vc4_uncompiled_shader {
 116         /** A name for this program, so you can track it in shader-db output. */
 117         uint32_t program_id;
 118         /** How many variants of this program were compiled, for shader-db. */
 119         uint32_t compiled_variant_count;
 120         struct pipe_shader_state base;
 121 };
 122
 123 struct vc4_ubo_range {
 124         /**
 125          * offset in bytes from the start of the ubo where this range is
 126          * uploaded.
 127          *
 128          * Only set once used is set.
 129          */
 130         uint32_t dst_offset;
 131
 132         /**
 133          * offset in bytes from the start of the gallium uniforms where the
 134          * data comes from.
 135          */
 136         uint32_t src_offset;
 137
 138         /** size in bytes of this ubo range */
 139         uint32_t size;
 140 };
 141
 142 struct vc4_fs_inputs {
 143         /**
 144          * Array of the meanings of the VPM inputs this shader needs.
 145          *
 146          * It doesn't include those that aren't part of the VPM, like
 147          * point/line coordinates.
 148          */
 149         struct vc4_varying_slot *input_slots;
 150         uint32_t num_inputs;
 151 };
 152
 153 struct vc4_compiled_shader {
 154         uint64_t program_id;
 155         struct vc4_bo *bo;
 156
 157         struct vc4_shader_uniform_info uniforms;
 158
 159         struct vc4_ubo_range *ubo_ranges;
 160         uint32_t num_ubo_ranges;
 161         uint32_t ubo_size;
 162         /**
 163          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
 164          * uniforms have to be rewritten (and therefore the shader state
 165          * reemitted).
 166          */
 167         uint32_t uniform_dirty_bits;
 168
 169         /** bitmask of which inputs are color inputs, for flat shade handling. */
 170         uint32_t color_inputs;
 171
 172         bool disable_early_z;
 173
 174         /* Set if the compile failed, likely due to register allocation
 175          * failure.  In this case, we have no shader to run and should not try
 176          * to do any draws.
 177          */
 178         bool failed;
 179
 180         bool fs_threaded;
 181
 182         uint8_t num_inputs;
 183
 184         /* Byte offsets for the start of the vertex attributes 0-7, and the
 185          * total size as "attribute" 8.
 186          */
 187         uint8_t vattr_offsets[9];
 188         uint8_t vattrs_live;
 189
 190         const struct vc4_fs_inputs *fs_inputs;
 191 };
 192
 193 struct vc4_program_stateobj {
 194         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
 195         struct vc4_compiled_shader *cs, *vs, *fs;
 196 };
 197
 198 struct vc4_constbuf_stateobj {
 199         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 200         uint32_t enabled_mask;
 201         uint32_t dirty_mask;
 202 };
 203
 204 struct vc4_vertexbuf_stateobj {
 205         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 206         unsigned count;
 207         uint32_t enabled_mask;
 208         uint32_t dirty_mask;
 209 };
 210
 211 struct vc4_vertex_stateobj {
 212         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 213         unsigned num_elements;
 214 };
 215
 216 /* Hash table key for vc4->jobs */
 217 struct vc4_job_key {
 218         struct pipe_surface *cbuf;
 219         struct pipe_surface *zsbuf;
 220 };
 221
 222 /**
 223  * A complete bin/render job.
 224  *
 225  * This is all of the state necessary to submit a bin/render to the kernel.
 226  * We want to be able to have multiple in progress at a time, so that we don't
 227  * need to flush an existing CL just to switch to rendering to a new render
 228  * target (which would mean reading back from the old render target when
 229  * starting to render to it again).
 230  */
 231 struct vc4_job {
 232         struct vc4_cl bcl;
 233         struct vc4_cl shader_rec;
 234         struct vc4_cl uniforms;
 235         struct vc4_cl bo_handles;
 236         struct vc4_cl bo_pointers;
 237         uint32_t shader_rec_count;
 238         /**
 239          * Amount of memory used by the BOs in bo_pointers.
 240          *
 241          * Used for checking when we should flush the job early so we don't
 242          * OOM.
 243          */
 244         uint32_t bo_space;
 245
 246         /** @{ Surfaces to submit rendering for. */
 247         struct pipe_surface *color_read;
 248         struct pipe_surface *color_write;
 249         struct pipe_surface *zs_read;
 250         struct pipe_surface *zs_write;
 251         struct pipe_surface *msaa_color_write;
 252         struct pipe_surface *msaa_zs_write;
 253         /** @} */
 254         /** @{
 255          * Bounding box of the scissor across all queued drawing.
 256          *
 257          * Note that the max values are exclusive.
 258          */
 259         uint32_t draw_min_x;
 260         uint32_t draw_min_y;
 261         uint32_t draw_max_x;
 262         uint32_t draw_max_y;
 263         /** @} */
 264         /** @{
 265          * Width/height of the color framebuffer being rendered to,
 266          * for VC4_TILE_RENDERING_MODE_CONFIG.
 267         */
 268         uint32_t draw_width;
 269         uint32_t draw_height;
 270         /** @} */
 271         /** @{ Tile information, depending on MSAA and float color buffer. */
 272         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 273         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 274
 275         uint32_t tile_width; /** @< Width of a tile. */
 276         uint32_t tile_height; /** @< Height of a tile. */
 277         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 278         bool msaa;
 279         /** @} */
 280
 281         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 282          * first rendering.
 283          */
 284         uint32_t cleared;
 285         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 286          * (either clears or draws).
 287          */
 288         uint32_t resolve;
 289         uint32_t clear_color[2];
 290         uint32_t clear_depth; /**< 24-bit unorm depth */
 291         uint8_t clear_stencil;
 292
 293         /**
 294          * Set if some drawing (triangles, blits, or just a glClear()) has
 295          * been done to the FBO, meaning that we need to
 296          * DRM_IOCTL_VC4_SUBMIT_CL.
 297          */
 298         bool needs_flush;
 299
 300         /**
 301          * Number of draw calls (not counting full buffer clears) queued in
 302          * the current job.
 303          */
 304         uint32_t draw_calls_queued;
 305
 306         /** Any flags to be passed in drm_vc4_submit_cl.flags. */
 307         uint32_t flags;
 308
 309         struct vc4_job_key key;
 310 };
 311
 312 struct vc4_context {
 313         struct pipe_context base;
 314
 315         int fd;
 316         struct vc4_screen *screen;
 317
 318         /** The 3D rendering job for the currently bound FBO. */
 319         struct vc4_job *job;
 320
 321         /* Map from struct vc4_job_key to the job for that FBO.
 322          */
 323         struct hash_table *jobs;
 324
 325         /**
 326          * Map from vc4_resource to a job writing to that resource.
 327          *
 328          * Primarily for flushing jobs rendering to textures that are now
 329          * being read from.
 330          */
 331         struct hash_table *write_jobs;
 332
 333         struct slab_child_pool transfer_pool;
 334         struct blitter_context *blitter;
 335
 336         /** bitfield of VC4_DIRTY_* */
 337         uint32_t dirty;
 338
 339         struct primconvert_context *primconvert;
 340
 341         struct hash_table *fs_cache, *vs_cache;
 342         struct set *fs_inputs_set;
 343         uint32_t next_uncompiled_program_id;
 344         uint64_t next_compiled_program_id;
 345
 346         struct ra_regs *regs;
 347         unsigned int reg_class_any[2];
 348         unsigned int reg_class_a_or_b[2];
 349         unsigned int reg_class_a_or_b_or_acc[2];
 350         unsigned int reg_class_r0_r3;
 351         unsigned int reg_class_r4_or_a[2];
 352         unsigned int reg_class_a[2];
 353
 354         uint8_t prim_mode;
 355
 356         /** Maximum index buffer valid for the current shader_rec. */
 357         uint32_t max_index;
 358         /** Last index bias baked into the current shader_rec. */
 359         uint32_t last_index_bias;
 360
 361         /** Seqno of the last CL flush's job. */
 362         uint64_t last_emit_seqno;
 363
 364         struct u_upload_mgr *uploader;
 365
 366         /** @{ Current pipeline state objects */
 367         struct pipe_scissor_state scissor;
 368         struct pipe_blend_state *blend;
 369         struct vc4_rasterizer_state *rasterizer;
 370         struct vc4_depth_stencil_alpha_state *zsa;
 371
 372         struct vc4_texture_stateobj verttex, fragtex;
 373
 374         struct vc4_program_stateobj prog;
 375
 376         struct vc4_vertex_stateobj *vtx;
 377
 378         struct {
 379                 struct pipe_blend_color f;
 380                 uint8_t ub[4];
 381         } blend_color;
 382         struct pipe_stencil_ref stencil_ref;
 383         unsigned sample_mask;
 384         struct pipe_framebuffer_state framebuffer;
 385         struct pipe_poly_stipple stipple;
 386         struct pipe_clip_state clip;
 387         struct pipe_viewport_state viewport;
 388         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 389         struct vc4_vertexbuf_stateobj vertexbuf;
 390         /** @} */
 391 };
 392
 393 struct vc4_rasterizer_state {
 394         struct pipe_rasterizer_state base;
 395
 396         /* VC4_CONFIGURATION_BITS */
 397         uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
 398
 399         struct PACKED {
 400                 uint8_t depth_offset[V3D21_DEPTH_OFFSET_length];
 401                 uint8_t point_size[V3D21_POINT_SIZE_length];
 402                 uint8_t line_width[V3D21_LINE_WIDTH_length];
 403         } packed;
 404
 405         /** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */
 406         uint32_t tile_raster_order_flags;
 407 };
 408
 409 struct vc4_depth_stencil_alpha_state {
 410         struct pipe_depth_stencil_alpha_state base;
 411
 412         /* VC4_CONFIGURATION_BITS */
 413         uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
 414
 415         /** Uniforms for stencil state.
 416          *
 417          * Index 0 is either the front config, or the front-and-back config.
 418          * Index 1 is the back config if doing separate back stencil.
 419          * Index 2 is the writemask config if it's not a common mask value.
 420          */
 421         uint32_t stencil_uniforms[3];
 422 };
 423
 424 #define perf_debug(...) do {                            \
 425         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
 426                 fprintf(stderr, __VA_ARGS__);           \
 427 } while (0)
 428
 429 static inline struct vc4_context *
 430 vc4_context(struct pipe_context *pcontext)
 431 {
 432         return (struct vc4_context *)pcontext;
 433 }
 434
 435 static inline struct vc4_sampler_view *
 436 vc4_sampler_view(struct pipe_sampler_view *psview)
 437 {
 438         return (struct vc4_sampler_view *)psview;
 439 }
 440
 441 static inline struct vc4_sampler_state *
 442 vc4_sampler_state(struct pipe_sampler_state *psampler)
 443 {
 444         return (struct vc4_sampler_state *)psampler;
 445 }
 446
 447 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 448                                         void *priv, unsigned flags);
 449 void vc4_draw_init(struct pipe_context *pctx);
 450 void vc4_state_init(struct pipe_context *pctx);
 451 void vc4_program_init(struct pipe_context *pctx);
 452 void vc4_program_fini(struct pipe_context *pctx);
 453 void vc4_query_init(struct pipe_context *pctx);
 454 void vc4_simulator_init(struct vc4_screen *screen);
 455 void vc4_simulator_destroy(struct vc4_screen *screen);
 456 int vc4_simulator_flush(struct vc4_context *vc4,
 457                         struct drm_vc4_submit_cl *args,
 458                         struct vc4_job *job);
 459 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
 460 void vc4_simulator_open_from_handle(int fd, uint32_t winsys_stride,
 461                                     int handle, uint32_t size);
 462
 463 static inline int
 464 vc4_ioctl(int fd, unsigned long request, void *arg)
 465 {
 466         if (using_vc4_simulator)
 467                 return vc4_simulator_ioctl(fd, request, arg);
 468         else
 469                 return drmIoctl(fd, request, arg);
 470 }
 471
 472 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
 473 void vc4_write_uniforms(struct vc4_context *vc4,
 474                         struct vc4_compiled_shader *shader,
 475                         struct vc4_constbuf_stateobj *cb,
 476                         struct vc4_texture_stateobj *texstate);
 477
 478 void vc4_flush(struct pipe_context *pctx);
 479 void vc4_job_init(struct vc4_context *vc4);
 480 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 481                             struct pipe_surface *cbuf,
 482                             struct pipe_surface *zsbuf);
 483 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
 484
 485 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
 486 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
 487                                      struct pipe_resource *prsc);
 488 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
 489                                      struct pipe_resource *prsc);
 490 void vc4_emit_state(struct pipe_context *pctx);
 491 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 492 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 493 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 494
 495 bool vc4_rt_format_supported(enum pipe_format f);
 496 bool vc4_rt_format_is_565(enum pipe_format f);
 497 bool vc4_tex_format_supported(enum pipe_format f);
 498 uint8_t vc4_get_tex_format(enum pipe_format f);
 499 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 500 void vc4_init_query_functions(struct vc4_context *vc4);
 501 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 502 void vc4_blitter_save(struct vc4_context *vc4);
 503 #endif /* VC4_CONTEXT_H */