src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/slab.h"
  33 #include "xf86drm.h"
  34
  35 #define __user
  36 #include "drm-uapi/vc4_drm.h"
  37 #include "vc4_bufmgr.h"
  38 #include "vc4_resource.h"
  39 #include "vc4_cl.h"
  40 #include "vc4_qir.h"
  41
  42 #ifndef DRM_VC4_PARAM_SUPPORTS_ETC1
  43 #define DRM_VC4_PARAM_SUPPORTS_ETC1             4
  44 #endif
  45 #ifndef DRM_VC4_PARAM_SUPPORTS_THREADED_FS
  46 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS      5
  47 #endif
  48
  49 #ifdef USE_VC4_SIMULATOR
  50 #define using_vc4_simulator true
  51 #else
  52 #define using_vc4_simulator false
  53 #endif
  54
  55 #define VC4_DIRTY_BLEND         (1 <<  0)
  56 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  57 #define VC4_DIRTY_ZSA           (1 <<  2)
  58 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  59 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  60
  61 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  62 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  63 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  64 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  65 #define VC4_DIRTY_STIPPLE       (1 << 11)
  66 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  67 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  68 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  69 #define VC4_DIRTY_VTXBUF        (1 << 15)
  70
  71 #define VC4_DIRTY_SCISSOR       (1 << 17)
  72 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  73 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
  74 #define VC4_DIRTY_CLIP          (1 << 20)
  75 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
  76 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
  77 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
  78 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
  79 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
  80 #define VC4_DIRTY_FS_INPUTS     (1 << 26)
  81 #define VC4_DIRTY_UBO_1_SIZE    (1 << 27)
  82
  83 struct vc4_sampler_view {
  84         struct pipe_sampler_view base;
  85         uint32_t texture_p0;
  86         uint32_t texture_p1;
  87         bool force_first_level;
  88         /**
  89          * Resource containing the actual texture that will be sampled.
  90          *
  91          * We may need to rebase the .base.texture resource to work around the
  92          * lack of GL_TEXTURE_BASE_LEVEL, or to upload the texture as tiled.
  93          */
  94         struct pipe_resource *texture;
  95 };
  96
  97 struct vc4_sampler_state {
  98         struct pipe_sampler_state base;
  99         uint32_t texture_p1;
 100 };
 101
 102 struct vc4_texture_stateobj {
 103         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
 104         unsigned num_textures;
 105         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
 106         unsigned num_samplers;
 107 };
 108
 109 struct vc4_shader_uniform_info {
 110         enum quniform_contents *contents;
 111         uint32_t *data;
 112         uint32_t count;
 113         uint32_t num_texture_samples;
 114 };
 115
 116 struct vc4_uncompiled_shader {
 117         /** A name for this program, so you can track it in shader-db output. */
 118         uint32_t program_id;
 119         /** How many variants of this program were compiled, for shader-db. */
 120         uint32_t compiled_variant_count;
 121         struct pipe_shader_state base;
 122 };
 123
 124 struct vc4_ubo_range {
 125         /**
 126          * offset in bytes from the start of the ubo where this range is
 127          * uploaded.
 128          *
 129          * Only set once used is set.
 130          */
 131         uint32_t dst_offset;
 132
 133         /**
 134          * offset in bytes from the start of the gallium uniforms where the
 135          * data comes from.
 136          */
 137         uint32_t src_offset;
 138
 139         /** size in bytes of this ubo range */
 140         uint32_t size;
 141 };
 142
 143 struct vc4_fs_inputs {
 144         /**
 145          * Array of the meanings of the VPM inputs this shader needs.
 146          *
 147          * It doesn't include those that aren't part of the VPM, like
 148          * point/line coordinates.
 149          */
 150         struct vc4_varying_slot *input_slots;
 151         uint32_t num_inputs;
 152 };
 153
 154 struct vc4_compiled_shader {
 155         uint64_t program_id;
 156         struct vc4_bo *bo;
 157
 158         struct vc4_shader_uniform_info uniforms;
 159
 160         struct vc4_ubo_range *ubo_ranges;
 161         uint32_t num_ubo_ranges;
 162         uint32_t ubo_size;
 163         /**
 164          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
 165          * uniforms have to be rewritten (and therefore the shader state
 166          * reemitted).
 167          */
 168         uint32_t uniform_dirty_bits;
 169
 170         /** bitmask of which inputs are color inputs, for flat shade handling. */
 171         uint32_t color_inputs;
 172
 173         bool disable_early_z;
 174
 175         /* Set if the compile failed, likely due to register allocation
 176          * failure.  In this case, we have no shader to run and should not try
 177          * to do any draws.
 178          */
 179         bool failed;
 180
 181         bool fs_threaded;
 182
 183         uint8_t num_inputs;
 184
 185         /* Byte offsets for the start of the vertex attributes 0-7, and the
 186          * total size as "attribute" 8.
 187          */
 188         uint8_t vattr_offsets[9];
 189         uint8_t vattrs_live;
 190
 191         const struct vc4_fs_inputs *fs_inputs;
 192 };
 193
 194 struct vc4_program_stateobj {
 195         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
 196         struct vc4_compiled_shader *cs, *vs, *fs;
 197 };
 198
 199 struct vc4_constbuf_stateobj {
 200         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 201         uint32_t enabled_mask;
 202         uint32_t dirty_mask;
 203 };
 204
 205 struct vc4_vertexbuf_stateobj {
 206         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 207         unsigned count;
 208         uint32_t enabled_mask;
 209         uint32_t dirty_mask;
 210 };
 211
 212 struct vc4_vertex_stateobj {
 213         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 214         unsigned num_elements;
 215 };
 216
 217 /* Hash table key for vc4->jobs */
 218 struct vc4_job_key {
 219         struct pipe_surface *cbuf;
 220         struct pipe_surface *zsbuf;
 221 };
 222
 223 struct vc4_hwperfmon {
 224         uint32_t id;
 225         uint64_t last_seqno;
 226         uint8_t events[DRM_VC4_MAX_PERF_COUNTERS];
 227         uint64_t counters[DRM_VC4_MAX_PERF_COUNTERS];
 228 };
 229
 230 /**
 231  * A complete bin/render job.
 232  *
 233  * This is all of the state necessary to submit a bin/render to the kernel.
 234  * We want to be able to have multiple in progress at a time, so that we don't
 235  * need to flush an existing CL just to switch to rendering to a new render
 236  * target (which would mean reading back from the old render target when
 237  * starting to render to it again).
 238  */
 239 struct vc4_job {
 240         struct vc4_cl bcl;
 241         struct vc4_cl shader_rec;
 242         struct vc4_cl uniforms;
 243         struct vc4_cl bo_handles;
 244         struct vc4_cl bo_pointers;
 245         uint32_t shader_rec_count;
 246         /**
 247          * Amount of memory used by the BOs in bo_pointers.
 248          *
 249          * Used for checking when we should flush the job early so we don't
 250          * OOM.
 251          */
 252         uint32_t bo_space;
 253
 254         /* Last BO hindex referenced from VC4_PACKET_GEM_HANDLES. */
 255         uint32_t last_gem_handle_hindex;
 256
 257         /** @{ Surfaces to submit rendering for. */
 258         struct pipe_surface *color_read;
 259         struct pipe_surface *color_write;
 260         struct pipe_surface *zs_read;
 261         struct pipe_surface *zs_write;
 262         struct pipe_surface *msaa_color_write;
 263         struct pipe_surface *msaa_zs_write;
 264         /** @} */
 265         /** @{
 266          * Bounding box of the scissor across all queued drawing.
 267          *
 268          * Note that the max values are exclusive.
 269          */
 270         uint32_t draw_min_x;
 271         uint32_t draw_min_y;
 272         uint32_t draw_max_x;
 273         uint32_t draw_max_y;
 274         /** @} */
 275         /** @{
 276          * Width/height of the color framebuffer being rendered to,
 277          * for VC4_TILE_RENDERING_MODE_CONFIG.
 278         */
 279         uint32_t draw_width;
 280         uint32_t draw_height;
 281         /** @} */
 282         /** @{ Tile information, depending on MSAA and float color buffer. */
 283         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 284         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 285
 286         uint32_t tile_width; /** @< Width of a tile. */
 287         uint32_t tile_height; /** @< Height of a tile. */
 288         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 289         bool msaa;
 290         /** @} */
 291
 292         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 293          * first rendering.
 294          */
 295         uint32_t cleared;
 296         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 297          * (either clears or draws).
 298          */
 299         uint32_t resolve;
 300         uint32_t clear_color[2];
 301         uint32_t clear_depth; /**< 24-bit unorm depth */
 302         uint8_t clear_stencil;
 303
 304         /**
 305          * Set if some drawing (triangles, blits, or just a glClear()) has
 306          * been done to the FBO, meaning that we need to
 307          * DRM_IOCTL_VC4_SUBMIT_CL.
 308          */
 309         bool needs_flush;
 310
 311         /**
 312          * Number of draw calls (not counting full buffer clears) queued in
 313          * the current job.
 314          */
 315         uint32_t draw_calls_queued;
 316
 317         /** Any flags to be passed in drm_vc4_submit_cl.flags. */
 318         uint32_t flags;
 319
 320         /* Performance monitor attached to this job. */
 321         struct vc4_hwperfmon *perfmon;
 322
 323         struct vc4_job_key key;
 324 };
 325
 326 struct vc4_context {
 327         struct pipe_context base;
 328
 329         int fd;
 330         struct vc4_screen *screen;
 331
 332         /** The 3D rendering job for the currently bound FBO. */
 333         struct vc4_job *job;
 334
 335         /* Map from struct vc4_job_key to the job for that FBO.
 336          */
 337         struct hash_table *jobs;
 338
 339         /**
 340          * Map from vc4_resource to a job writing to that resource.
 341          *
 342          * Primarily for flushing jobs rendering to textures that are now
 343          * being read from.
 344          */
 345         struct hash_table *write_jobs;
 346
 347         struct slab_child_pool transfer_pool;
 348         struct blitter_context *blitter;
 349
 350         /** bitfield of VC4_DIRTY_* */
 351         uint32_t dirty;
 352
 353         struct primconvert_context *primconvert;
 354
 355         struct hash_table *fs_cache, *vs_cache;
 356         struct set *fs_inputs_set;
 357         uint32_t next_uncompiled_program_id;
 358         uint64_t next_compiled_program_id;
 359
 360         struct ra_regs *regs;
 361         unsigned int reg_class_any[2];
 362         unsigned int reg_class_a_or_b[2];
 363         unsigned int reg_class_a_or_b_or_acc[2];
 364         unsigned int reg_class_r0_r3;
 365         unsigned int reg_class_r4_or_a[2];
 366         unsigned int reg_class_a[2];
 367
 368         uint8_t prim_mode;
 369
 370         /** Maximum index buffer valid for the current shader_rec. */
 371         uint32_t max_index;
 372         /** Last index bias baked into the current shader_rec. */
 373         uint32_t last_index_bias;
 374
 375         /** Seqno of the last CL flush's job. */
 376         uint64_t last_emit_seqno;
 377
 378         struct u_upload_mgr *uploader;
 379
 380         struct pipe_shader_state *yuv_linear_blit_vs;
 381         struct pipe_shader_state *yuv_linear_blit_fs_8bit;
 382         struct pipe_shader_state *yuv_linear_blit_fs_16bit;
 383
 384         /** @{ Current pipeline state objects */
 385         struct pipe_scissor_state scissor;
 386         struct pipe_blend_state *blend;
 387         struct vc4_rasterizer_state *rasterizer;
 388         struct vc4_depth_stencil_alpha_state *zsa;
 389
 390         struct vc4_texture_stateobj verttex, fragtex;
 391
 392         struct vc4_program_stateobj prog;
 393
 394         struct vc4_vertex_stateobj *vtx;
 395
 396         struct {
 397                 struct pipe_blend_color f;
 398                 uint8_t ub[4];
 399         } blend_color;
 400         struct pipe_stencil_ref stencil_ref;
 401         unsigned sample_mask;
 402         struct pipe_framebuffer_state framebuffer;
 403         struct pipe_poly_stipple stipple;
 404         struct pipe_clip_state clip;
 405         struct pipe_viewport_state viewport;
 406         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 407         struct vc4_vertexbuf_stateobj vertexbuf;
 408         struct pipe_debug_callback debug;
 409
 410         struct vc4_hwperfmon *perfmon;
 411         /** @} */
 412
 413         /** Handle of syncobj containing the last submitted job fence. */
 414         uint32_t job_syncobj;
 415
 416         int in_fence_fd;
 417         /** Handle of the syncobj that holds in_fence_fd for submission. */
 418         uint32_t in_syncobj;
 419 };
 420
 421 struct vc4_rasterizer_state {
 422         struct pipe_rasterizer_state base;
 423
 424         /* VC4_CONFIGURATION_BITS */
 425         uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
 426
 427         struct PACKED {
 428                 uint8_t depth_offset[V3D21_DEPTH_OFFSET_length];
 429                 uint8_t point_size[V3D21_POINT_SIZE_length];
 430                 uint8_t line_width[V3D21_LINE_WIDTH_length];
 431         } packed;
 432
 433         /** Raster order flags to be passed in struct drm_vc4_submit_cl.flags. */
 434         uint32_t tile_raster_order_flags;
 435 };
 436
 437 struct vc4_depth_stencil_alpha_state {
 438         struct pipe_depth_stencil_alpha_state base;
 439
 440         /* VC4_CONFIGURATION_BITS */
 441         uint8_t config_bits[V3D21_CONFIGURATION_BITS_length];
 442
 443         /** Uniforms for stencil state.
 444          *
 445          * Index 0 is either the front config, or the front-and-back config.
 446          * Index 1 is the back config if doing separate back stencil.
 447          * Index 2 is the writemask config if it's not a common mask value.
 448          */
 449         uint32_t stencil_uniforms[3];
 450 };
 451
 452 #define perf_debug(...) do {                            \
 453         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
 454                 fprintf(stderr, __VA_ARGS__);           \
 455         if (unlikely(vc4->debug.debug_message))         \
 456                 pipe_debug_message(&vc4->debug, PERF_INFO, __VA_ARGS__);    \
 457 } while (0)
 458
 459 static inline struct vc4_context *
 460 vc4_context(struct pipe_context *pcontext)
 461 {
 462         return (struct vc4_context *)pcontext;
 463 }
 464
 465 static inline struct vc4_sampler_view *
 466 vc4_sampler_view(struct pipe_sampler_view *psview)
 467 {
 468         return (struct vc4_sampler_view *)psview;
 469 }
 470
 471 static inline struct vc4_sampler_state *
 472 vc4_sampler_state(struct pipe_sampler_state *psampler)
 473 {
 474         return (struct vc4_sampler_state *)psampler;
 475 }
 476
 477 int vc4_get_driver_query_group_info(struct pipe_screen *pscreen,
 478                                     unsigned index,
 479                                     struct pipe_driver_query_group_info *info);
 480 int vc4_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
 481                               struct pipe_driver_query_info *info);
 482
 483 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 484                                         void *priv, unsigned flags);
 485 void vc4_draw_init(struct pipe_context *pctx);
 486 void vc4_state_init(struct pipe_context *pctx);
 487 void vc4_program_init(struct pipe_context *pctx);
 488 void vc4_program_fini(struct pipe_context *pctx);
 489 void vc4_query_init(struct pipe_context *pctx);
 490 void vc4_simulator_init(struct vc4_screen *screen);
 491 void vc4_simulator_destroy(struct vc4_screen *screen);
 492 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
 493 void vc4_simulator_open_from_handle(int fd, int handle, uint32_t size);
 494
 495 static inline int
 496 vc4_ioctl(int fd, unsigned long request, void *arg)
 497 {
 498         if (using_vc4_simulator)
 499                 return vc4_simulator_ioctl(fd, request, arg);
 500         else
 501                 return drmIoctl(fd, request, arg);
 502 }
 503
 504 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
 505 void vc4_write_uniforms(struct vc4_context *vc4,
 506                         struct vc4_compiled_shader *shader,
 507                         struct vc4_constbuf_stateobj *cb,
 508                         struct vc4_texture_stateobj *texstate);
 509
 510 void vc4_flush(struct pipe_context *pctx);
 511 int vc4_job_init(struct vc4_context *vc4);
 512 int vc4_fence_context_init(struct vc4_context *vc4);
 513 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 514                             struct pipe_surface *cbuf,
 515                             struct pipe_surface *zsbuf);
 516 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
 517
 518 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
 519 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
 520                                      struct pipe_resource *prsc);
 521 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
 522                                      struct pipe_resource *prsc);
 523 void vc4_emit_state(struct pipe_context *pctx);
 524 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 525 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 526 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 527
 528 bool vc4_rt_format_supported(enum pipe_format f);
 529 bool vc4_rt_format_is_565(enum pipe_format f);
 530 bool vc4_tex_format_supported(enum pipe_format f);
 531 uint8_t vc4_get_tex_format(enum pipe_format f);
 532 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 533 void vc4_init_query_functions(struct vc4_context *vc4);
 534 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 535 void vc4_blitter_save(struct vc4_context *vc4);
 536 #endif /* VC4_CONTEXT_H */