src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/u_slab.h"
  33
  34 #define __user
  35 #include "vc4_drm.h"
  36 #include "vc4_bufmgr.h"
  37 #include "vc4_resource.h"
  38 #include "vc4_cl.h"
  39 #include "vc4_qir.h"
  40
  41 #define VC4_DIRTY_BLEND         (1 <<  0)
  42 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  43 #define VC4_DIRTY_ZSA           (1 <<  2)
  44 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  45 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  46 #define VC4_DIRTY_TEXSTATE      (1 <<  5)
  47 #define VC4_DIRTY_PROG          (1 <<  6)
  48 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  49 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  50 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  51 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  52 #define VC4_DIRTY_STIPPLE       (1 << 11)
  53 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  54 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  55 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  56 #define VC4_DIRTY_VTXBUF        (1 << 15)
  57 #define VC4_DIRTY_INDEXBUF      (1 << 16)
  58 #define VC4_DIRTY_SCISSOR       (1 << 17)
  59 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  60
  61 #define VC4_SHADER_DIRTY_VP     (1 << 0)
  62 #define VC4_SHADER_DIRTY_FP     (1 << 1)
  63
  64 struct vc4_texture_stateobj {
  65         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  66         unsigned num_textures;
  67         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  68         unsigned num_samplers;
  69         unsigned dirty_samplers;
  70 };
  71
  72 struct vc4_shader_uniform_info {
  73         enum quniform_contents *contents;
  74         uint32_t *data;
  75         uint32_t count;
  76         uint32_t num_texture_samples;
  77 };
  78
  79 struct vc4_compiled_shader {
  80         struct vc4_bo *bo;
  81
  82         struct vc4_shader_uniform_info uniforms[2];
  83
  84         uint32_t coord_shader_offset;
  85
  86         /** bitmask of which inputs are color inputs, for flat shade handling. */
  87         uint32_t color_inputs;
  88
  89         uint8_t num_inputs;
  90 };
  91
  92 struct vc4_program_stateobj {
  93         struct pipe_shader_state *bind_vs, *bind_fs;
  94         struct vc4_compiled_shader *vs, *fs;
  95         uint32_t dirty;
  96         uint8_t num_exports;
  97         /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
  98          * for TGSI_SEMANTIC_GENERIC.  Special vs exports (position and point-
  99          * size) are not included in this
 100          */
 101         uint8_t export_linkage[63];
 102 };
 103
 104 struct vc4_constbuf_stateobj {
 105         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 106         uint32_t enabled_mask;
 107         uint32_t dirty_mask;
 108 };
 109
 110 struct vc4_vertexbuf_stateobj {
 111         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 112         unsigned count;
 113         uint32_t enabled_mask;
 114         uint32_t dirty_mask;
 115 };
 116
 117 struct vc4_vertex_stateobj {
 118         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 119         unsigned num_elements;
 120 };
 121
 122 struct vc4_context {
 123         struct pipe_context base;
 124
 125         int fd;
 126         struct vc4_screen *screen;
 127
 128         struct vc4_cl bcl;
 129         struct vc4_cl rcl;
 130         struct vc4_cl shader_rec;
 131         struct vc4_cl uniforms;
 132         struct vc4_cl bo_handles;
 133         struct vc4_cl bo_pointers;
 134         uint32_t shader_rec_count;
 135
 136         struct vc4_bo *tile_alloc;
 137         struct vc4_bo *tile_state;
 138
 139         struct util_slab_mempool transfer_pool;
 140         struct blitter_context *blitter;
 141
 142         /** bitfield of VC4_DIRTY_* */
 143         uint32_t dirty;
 144         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 145          * first rendering.
 146          */
 147         uint32_t cleared;
 148         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 149          * (either clears or draws).
 150          */
 151         uint32_t resolve;
 152         uint32_t clear_color[2];
 153         uint32_t clear_depth; /**< 24-bit unorm depth */
 154         uint8_t clear_stencil;
 155
 156         /**
 157          * Set if some drawing (triangles, blits, or just a glClear()) has
 158          * been done to the FBO, meaning that we need to
 159          * DRM_IOCTL_VC4_SUBMIT_CL.
 160          */
 161         bool needs_flush;
 162
 163         /**
 164          * Set when needs_flush, and the queued rendering is not just composed
 165          * of full-buffer clears.
 166          */
 167         bool draw_call_queued;
 168
 169         struct primconvert_context *primconvert;
 170
 171         struct util_hash_table *fs_cache, *vs_cache;
 172
 173         struct ra_regs *regs;
 174         unsigned int reg_class_any;
 175         unsigned int reg_class_a;
 176
 177         /** @{ Current pipeline state objects */
 178         struct pipe_scissor_state scissor;
 179         struct pipe_blend_state *blend;
 180         struct vc4_rasterizer_state *rasterizer;
 181         struct vc4_depth_stencil_alpha_state *zsa;
 182
 183         struct vc4_texture_stateobj verttex, fragtex;
 184
 185         struct vc4_program_stateobj prog;
 186
 187         struct vc4_vertex_stateobj *vtx;
 188
 189         struct pipe_blend_color blend_color;
 190         struct pipe_stencil_ref stencil_ref;
 191         unsigned sample_mask;
 192         struct pipe_framebuffer_state framebuffer;
 193         struct pipe_poly_stipple stipple;
 194         struct pipe_viewport_state viewport;
 195         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 196         struct vc4_vertexbuf_stateobj vertexbuf;
 197         struct pipe_index_buffer indexbuf;
 198         /** @} */
 199 };
 200
 201 struct vc4_rasterizer_state {
 202         struct pipe_rasterizer_state base;
 203
 204         /* VC4_CONFIGURATION_BITS */
 205         uint8_t config_bits[3];
 206
 207         float point_size;
 208 };
 209
 210 struct vc4_depth_stencil_alpha_state {
 211         struct pipe_depth_stencil_alpha_state base;
 212
 213         /* VC4_CONFIGURATION_BITS */
 214         uint8_t config_bits[3];
 215
 216         /** Uniforms for stencil state.
 217          *
 218          * Index 0 is either the front config, or the front-and-back config.
 219          * Index 1 is the back config if doing separate back stencil.
 220          * Index 2 is the writemask config if it's not a common mask value.
 221          */
 222         uint32_t stencil_uniforms[3];
 223 };
 224
 225 static inline struct vc4_context *
 226 vc4_context(struct pipe_context *pcontext)
 227 {
 228         return (struct vc4_context *)pcontext;
 229 }
 230
 231 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 232                                         void *priv);
 233 void vc4_draw_init(struct pipe_context *pctx);
 234 void vc4_state_init(struct pipe_context *pctx);
 235 void vc4_program_init(struct pipe_context *pctx);
 236 void vc4_simulator_init(struct vc4_screen *screen);
 237 int vc4_simulator_flush(struct vc4_context *vc4,
 238                         struct drm_vc4_submit_cl *args);
 239
 240 void vc4_write_uniforms(struct vc4_context *vc4,
 241                         struct vc4_compiled_shader *shader,
 242                         struct vc4_constbuf_stateobj *cb,
 243                         struct vc4_texture_stateobj *texstate,
 244                         int shader_index);
 245
 246 void vc4_flush(struct pipe_context *pctx);
 247 void vc4_flush_for_bo(struct pipe_context *pctx, struct vc4_bo *bo);
 248 void vc4_emit_state(struct pipe_context *pctx);
 249 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 250 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 251 void vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 252
 253 bool vc4_rt_format_supported(enum pipe_format f);
 254 bool vc4_rt_format_is_565(enum pipe_format f);
 255 bool vc4_tex_format_supported(enum pipe_format f);
 256 uint8_t vc4_get_tex_format(enum pipe_format f);
 257 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 258
 259 #endif /* VC4_CONTEXT_H */