2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "pipe/p_context.h"
31 #include "pipe/p_state.h"
32 #include "util/u_slab.h"
36 #include "vc4_bufmgr.h"
37 #include "vc4_resource.h"
41 #ifdef USE_VC4_SIMULATOR
42 #define using_vc4_simulator true
44 #define using_vc4_simulator false
47 #define VC4_DIRTY_BLEND (1 << 0)
48 #define VC4_DIRTY_RASTERIZER (1 << 1)
49 #define VC4_DIRTY_ZSA (1 << 2)
50 #define VC4_DIRTY_FRAGTEX (1 << 3)
51 #define VC4_DIRTY_VERTTEX (1 << 4)
52 #define VC4_DIRTY_TEXSTATE (1 << 5)
54 #define VC4_DIRTY_BLEND_COLOR (1 << 7)
55 #define VC4_DIRTY_STENCIL_REF (1 << 8)
56 #define VC4_DIRTY_SAMPLE_MASK (1 << 9)
57 #define VC4_DIRTY_FRAMEBUFFER (1 << 10)
58 #define VC4_DIRTY_STIPPLE (1 << 11)
59 #define VC4_DIRTY_VIEWPORT (1 << 12)
60 #define VC4_DIRTY_CONSTBUF (1 << 13)
61 #define VC4_DIRTY_VTXSTATE (1 << 14)
62 #define VC4_DIRTY_VTXBUF (1 << 15)
63 #define VC4_DIRTY_INDEXBUF (1 << 16)
64 #define VC4_DIRTY_SCISSOR (1 << 17)
65 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
66 #define VC4_DIRTY_PRIM_MODE (1 << 19)
67 #define VC4_DIRTY_CLIP (1 << 20)
68 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
69 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
70 #define VC4_DIRTY_COMPILED_CS (1 << 23)
71 #define VC4_DIRTY_COMPILED_VS (1 << 24)
72 #define VC4_DIRTY_COMPILED_FS (1 << 25)
74 struct vc4_sampler_view
{
75 struct pipe_sampler_view base
;
80 struct vc4_sampler_state
{
81 struct pipe_sampler_state base
;
85 struct vc4_texture_stateobj
{
86 struct pipe_sampler_view
*textures
[PIPE_MAX_SAMPLERS
];
87 unsigned num_textures
;
88 struct pipe_sampler_state
*samplers
[PIPE_MAX_SAMPLERS
];
89 unsigned num_samplers
;
92 struct vc4_shader_uniform_info
{
93 enum quniform_contents
*contents
;
96 uint32_t num_texture_samples
;
99 struct vc4_uncompiled_shader
{
100 /** A name for this program, so you can track it in shader-db output. */
102 /** How many variants of this program were compiled, for shader-db. */
103 uint32_t compiled_variant_count
;
104 struct pipe_shader_state base
;
107 struct vc4_ubo_range
{
109 * offset in bytes from the start of the ubo where this range is
112 * Only set once used is set.
117 * offset in bytes from the start of the gallium uniforms where the
122 /** size in bytes of this ubo range */
126 struct vc4_compiled_shader
{
130 struct vc4_shader_uniform_info uniforms
;
132 struct vc4_ubo_range
*ubo_ranges
;
133 uint32_t num_ubo_ranges
;
136 * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
137 * uniforms have to be rewritten (and therefore the shader state
140 uint32_t uniform_dirty_bits
;
142 /** bitmask of which inputs are color inputs, for flat shade handling. */
143 uint32_t color_inputs
;
147 /* Byte offsets for the start of the vertex attributes 0-7, and the
148 * total size as "attribute" 8.
150 uint8_t vattr_offsets
[9];
154 * Array of the meanings of the VPM inputs this shader needs.
156 * It doesn't include those that aren't part of the VPM, like
157 * point/line coordinates.
159 struct vc4_varying_slot
*input_slots
;
162 struct vc4_program_stateobj
{
163 struct vc4_uncompiled_shader
*bind_vs
, *bind_fs
;
164 struct vc4_compiled_shader
*cs
, *vs
, *fs
;
167 struct vc4_constbuf_stateobj
{
168 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
169 uint32_t enabled_mask
;
173 struct vc4_vertexbuf_stateobj
{
174 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
176 uint32_t enabled_mask
;
180 struct vc4_vertex_stateobj
{
181 struct pipe_vertex_element pipe
[PIPE_MAX_ATTRIBS
];
182 unsigned num_elements
;
186 struct pipe_context base
;
189 struct vc4_screen
*screen
;
192 struct vc4_cl shader_rec
;
193 struct vc4_cl uniforms
;
194 struct vc4_cl bo_handles
;
195 struct vc4_cl bo_pointers
;
196 uint32_t shader_rec_count
;
198 /** @{ Surfaces to submit rendering for. */
199 struct pipe_surface
*color_read
;
200 struct pipe_surface
*color_write
;
201 struct pipe_surface
*zs_read
;
202 struct pipe_surface
*zs_write
;
203 struct pipe_surface
*msaa_color_write
;
204 struct pipe_surface
*msaa_zs_write
;
207 * Bounding box of the scissor across all queued drawing.
209 * Note that the max values are exclusive.
217 * Width/height of the color framebuffer being rendered to,
218 * for VC4_TILE_RENDERING_MODE_CONFIG.
221 uint32_t draw_height
;
223 /** @{ Tile information, depending on MSAA and float color buffer. */
224 uint32_t draw_tiles_x
; /** @< Number of tiles wide for framebuffer. */
225 uint32_t draw_tiles_y
; /** @< Number of tiles high for framebuffer. */
227 uint32_t tile_width
; /** @< Width of a tile. */
228 uint32_t tile_height
; /** @< Height of a tile. */
229 /** Whether the current rendering is in a 4X MSAA tile buffer. */
233 struct util_slab_mempool transfer_pool
;
234 struct blitter_context
*blitter
;
236 /** bitfield of VC4_DIRTY_* */
238 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
242 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
243 * (either clears or draws).
246 uint32_t clear_color
[2];
247 uint32_t clear_depth
; /**< 24-bit unorm depth */
248 uint8_t clear_stencil
;
251 * Set if some drawing (triangles, blits, or just a glClear()) has
252 * been done to the FBO, meaning that we need to
253 * DRM_IOCTL_VC4_SUBMIT_CL.
258 * Number of draw calls (not counting full buffer clears) queued in
261 uint32_t draw_calls_queued
;
263 /** Maximum index buffer valid for the current shader_rec. */
265 /** Last index bias baked into the current shader_rec. */
266 uint32_t last_index_bias
;
268 struct primconvert_context
*primconvert
;
270 struct hash_table
*fs_cache
, *vs_cache
;
271 uint32_t next_uncompiled_program_id
;
272 uint64_t next_compiled_program_id
;
274 struct ra_regs
*regs
;
275 unsigned int reg_class_any
;
276 unsigned int reg_class_a_or_b_or_acc
;
277 unsigned int reg_class_r4_or_a
;
278 unsigned int reg_class_a
;
282 /** Seqno of the last CL flush's job. */
283 uint64_t last_emit_seqno
;
285 struct u_upload_mgr
*uploader
;
287 /** @{ Current pipeline state objects */
288 struct pipe_scissor_state scissor
;
289 struct pipe_blend_state
*blend
;
290 struct vc4_rasterizer_state
*rasterizer
;
291 struct vc4_depth_stencil_alpha_state
*zsa
;
293 struct vc4_texture_stateobj verttex
, fragtex
;
295 struct vc4_program_stateobj prog
;
297 struct vc4_vertex_stateobj
*vtx
;
300 struct pipe_blend_color f
;
303 struct pipe_stencil_ref stencil_ref
;
304 unsigned sample_mask
;
305 struct pipe_framebuffer_state framebuffer
;
306 struct pipe_poly_stipple stipple
;
307 struct pipe_clip_state clip
;
308 struct pipe_viewport_state viewport
;
309 struct vc4_constbuf_stateobj constbuf
[PIPE_SHADER_TYPES
];
310 struct vc4_vertexbuf_stateobj vertexbuf
;
311 struct pipe_index_buffer indexbuf
;
315 struct vc4_rasterizer_state
{
316 struct pipe_rasterizer_state base
;
318 /* VC4_CONFIGURATION_BITS */
319 uint8_t config_bits
[3];
324 * Half-float (1/8/7 bits) value of polygon offset units for
325 * VC4_PACKET_DEPTH_OFFSET
327 uint16_t offset_units
;
329 * Half-float (1/8/7 bits) value of polygon offset scale for
330 * VC4_PACKET_DEPTH_OFFSET
332 uint16_t offset_factor
;
335 struct vc4_depth_stencil_alpha_state
{
336 struct pipe_depth_stencil_alpha_state base
;
338 /* VC4_CONFIGURATION_BITS */
339 uint8_t config_bits
[3];
341 /** Uniforms for stencil state.
343 * Index 0 is either the front config, or the front-and-back config.
344 * Index 1 is the back config if doing separate back stencil.
345 * Index 2 is the writemask config if it's not a common mask value.
347 uint32_t stencil_uniforms
[3];
350 #define perf_debug(...) do { \
351 if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \
352 fprintf(stderr, __VA_ARGS__); \
355 static inline struct vc4_context
*
356 vc4_context(struct pipe_context
*pcontext
)
358 return (struct vc4_context
*)pcontext
;
361 static inline struct vc4_sampler_view
*
362 vc4_sampler_view(struct pipe_sampler_view
*psview
)
364 return (struct vc4_sampler_view
*)psview
;
367 static inline struct vc4_sampler_state
*
368 vc4_sampler_state(struct pipe_sampler_state
*psampler
)
370 return (struct vc4_sampler_state
*)psampler
;
373 struct pipe_context
*vc4_context_create(struct pipe_screen
*pscreen
,
374 void *priv
, unsigned flags
);
375 void vc4_draw_init(struct pipe_context
*pctx
);
376 void vc4_state_init(struct pipe_context
*pctx
);
377 void vc4_program_init(struct pipe_context
*pctx
);
378 void vc4_program_fini(struct pipe_context
*pctx
);
379 void vc4_query_init(struct pipe_context
*pctx
);
380 void vc4_simulator_init(struct vc4_screen
*screen
);
381 int vc4_simulator_flush(struct vc4_context
*vc4
,
382 struct drm_vc4_submit_cl
*args
);
384 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader
*shader
);
385 void vc4_write_uniforms(struct vc4_context
*vc4
,
386 struct vc4_compiled_shader
*shader
,
387 struct vc4_constbuf_stateobj
*cb
,
388 struct vc4_texture_stateobj
*texstate
);
390 void vc4_flush(struct pipe_context
*pctx
);
391 void vc4_job_init(struct vc4_context
*vc4
);
392 void vc4_job_submit(struct vc4_context
*vc4
);
393 void vc4_job_reset(struct vc4_context
*vc4
);
394 bool vc4_cl_references_bo(struct pipe_context
*pctx
, struct vc4_bo
*bo
,
396 void vc4_emit_state(struct pipe_context
*pctx
);
397 void vc4_generate_code(struct vc4_context
*vc4
, struct vc4_compile
*c
);
398 struct qpu_reg
*vc4_register_allocate(struct vc4_context
*vc4
, struct vc4_compile
*c
);
399 void vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
);
401 bool vc4_rt_format_supported(enum pipe_format f
);
402 bool vc4_rt_format_is_565(enum pipe_format f
);
403 bool vc4_tex_format_supported(enum pipe_format f
);
404 uint8_t vc4_get_tex_format(enum pipe_format f
);
405 const uint8_t *vc4_get_format_swizzle(enum pipe_format f
);
406 void vc4_init_query_functions(struct vc4_context
*vc4
);
407 void vc4_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
);
408 #endif /* VC4_CONTEXT_H */