src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/slab.h"
  33 #include "xf86drm.h"
  34
  35 #define __user
  36 #include "vc4_drm.h"
  37 #include "vc4_bufmgr.h"
  38 #include "vc4_resource.h"
  39 #include "vc4_cl.h"
  40 #include "vc4_qir.h"
  41
  42 #ifdef USE_VC4_SIMULATOR
  43 #define using_vc4_simulator true
  44 #else
  45 #define using_vc4_simulator false
  46 #endif
  47
  48 #define VC4_DIRTY_BLEND         (1 <<  0)
  49 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  50 #define VC4_DIRTY_ZSA           (1 <<  2)
  51 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  52 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  53
  54 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  55 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  56 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  57 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  58 #define VC4_DIRTY_STIPPLE       (1 << 11)
  59 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  60 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  61 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  62 #define VC4_DIRTY_VTXBUF        (1 << 15)
  63 #define VC4_DIRTY_INDEXBUF      (1 << 16)
  64 #define VC4_DIRTY_SCISSOR       (1 << 17)
  65 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  66 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
  67 #define VC4_DIRTY_CLIP          (1 << 20)
  68 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
  69 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
  70 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
  71 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
  72 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
  73 #define VC4_DIRTY_FS_INPUTS     (1 << 26)
  74
  75 struct vc4_sampler_view {
  76         struct pipe_sampler_view base;
  77         uint32_t texture_p0;
  78         uint32_t texture_p1;
  79         bool force_first_level;
  80 };
  81
  82 struct vc4_sampler_state {
  83         struct pipe_sampler_state base;
  84         uint32_t texture_p1;
  85 };
  86
  87 struct vc4_texture_stateobj {
  88         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  89         unsigned num_textures;
  90         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  91         unsigned num_samplers;
  92 };
  93
  94 struct vc4_shader_uniform_info {
  95         enum quniform_contents *contents;
  96         uint32_t *data;
  97         uint32_t count;
  98         uint32_t num_texture_samples;
  99 };
 100
 101 struct vc4_uncompiled_shader {
 102         /** A name for this program, so you can track it in shader-db output. */
 103         uint32_t program_id;
 104         /** How many variants of this program were compiled, for shader-db. */
 105         uint32_t compiled_variant_count;
 106         struct pipe_shader_state base;
 107 };
 108
 109 struct vc4_ubo_range {
 110         /**
 111          * offset in bytes from the start of the ubo where this range is
 112          * uploaded.
 113          *
 114          * Only set once used is set.
 115          */
 116         uint32_t dst_offset;
 117
 118         /**
 119          * offset in bytes from the start of the gallium uniforms where the
 120          * data comes from.
 121          */
 122         uint32_t src_offset;
 123
 124         /** size in bytes of this ubo range */
 125         uint32_t size;
 126 };
 127
 128 struct vc4_fs_inputs {
 129         /**
 130          * Array of the meanings of the VPM inputs this shader needs.
 131          *
 132          * It doesn't include those that aren't part of the VPM, like
 133          * point/line coordinates.
 134          */
 135         struct vc4_varying_slot *input_slots;
 136         uint32_t num_inputs;
 137 };
 138
 139 struct vc4_compiled_shader {
 140         uint64_t program_id;
 141         struct vc4_bo *bo;
 142
 143         struct vc4_shader_uniform_info uniforms;
 144
 145         struct vc4_ubo_range *ubo_ranges;
 146         uint32_t num_ubo_ranges;
 147         uint32_t ubo_size;
 148         /**
 149          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
 150          * uniforms have to be rewritten (and therefore the shader state
 151          * reemitted).
 152          */
 153         uint32_t uniform_dirty_bits;
 154
 155         /** bitmask of which inputs are color inputs, for flat shade handling. */
 156         uint32_t color_inputs;
 157
 158         bool disable_early_z;
 159
 160         uint8_t num_inputs;
 161
 162         /* Byte offsets for the start of the vertex attributes 0-7, and the
 163          * total size as "attribute" 8.
 164          */
 165         uint8_t vattr_offsets[9];
 166         uint8_t vattrs_live;
 167
 168         const struct vc4_fs_inputs *fs_inputs;
 169 };
 170
 171 struct vc4_program_stateobj {
 172         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
 173         struct vc4_compiled_shader *cs, *vs, *fs;
 174 };
 175
 176 struct vc4_constbuf_stateobj {
 177         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 178         uint32_t enabled_mask;
 179         uint32_t dirty_mask;
 180 };
 181
 182 struct vc4_vertexbuf_stateobj {
 183         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 184         unsigned count;
 185         uint32_t enabled_mask;
 186         uint32_t dirty_mask;
 187 };
 188
 189 struct vc4_vertex_stateobj {
 190         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 191         unsigned num_elements;
 192 };
 193
 194 /* Hash table key for vc4->jobs */
 195 struct vc4_job_key {
 196         struct pipe_surface *cbuf;
 197         struct pipe_surface *zsbuf;
 198 };
 199
 200 /**
 201  * A complete bin/render job.
 202  *
 203  * This is all of the state necessary to submit a bin/render to the kernel.
 204  * We want to be able to have multiple in progress at a time, so that we don't
 205  * need to flush an existing CL just to switch to rendering to a new render
 206  * target (which would mean reading back from the old render target when
 207  * starting to render to it again).
 208  */
 209 struct vc4_job {
 210         struct vc4_cl bcl;
 211         struct vc4_cl shader_rec;
 212         struct vc4_cl uniforms;
 213         struct vc4_cl bo_handles;
 214         struct vc4_cl bo_pointers;
 215         uint32_t shader_rec_count;
 216
 217         /** @{ Surfaces to submit rendering for. */
 218         struct pipe_surface *color_read;
 219         struct pipe_surface *color_write;
 220         struct pipe_surface *zs_read;
 221         struct pipe_surface *zs_write;
 222         struct pipe_surface *msaa_color_write;
 223         struct pipe_surface *msaa_zs_write;
 224         /** @} */
 225         /** @{
 226          * Bounding box of the scissor across all queued drawing.
 227          *
 228          * Note that the max values are exclusive.
 229          */
 230         uint32_t draw_min_x;
 231         uint32_t draw_min_y;
 232         uint32_t draw_max_x;
 233         uint32_t draw_max_y;
 234         /** @} */
 235         /** @{
 236          * Width/height of the color framebuffer being rendered to,
 237          * for VC4_TILE_RENDERING_MODE_CONFIG.
 238         */
 239         uint32_t draw_width;
 240         uint32_t draw_height;
 241         /** @} */
 242         /** @{ Tile information, depending on MSAA and float color buffer. */
 243         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 244         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 245
 246         uint32_t tile_width; /** @< Width of a tile. */
 247         uint32_t tile_height; /** @< Height of a tile. */
 248         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 249         bool msaa;
 250         /** @} */
 251
 252         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 253          * first rendering.
 254          */
 255         uint32_t cleared;
 256         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 257          * (either clears or draws).
 258          */
 259         uint32_t resolve;
 260         uint32_t clear_color[2];
 261         uint32_t clear_depth; /**< 24-bit unorm depth */
 262         uint8_t clear_stencil;
 263
 264         /**
 265          * Set if some drawing (triangles, blits, or just a glClear()) has
 266          * been done to the FBO, meaning that we need to
 267          * DRM_IOCTL_VC4_SUBMIT_CL.
 268          */
 269         bool needs_flush;
 270
 271         /**
 272          * Number of draw calls (not counting full buffer clears) queued in
 273          * the current job.
 274          */
 275         uint32_t draw_calls_queued;
 276
 277         struct vc4_job_key key;
 278 };
 279
 280 struct vc4_context {
 281         struct pipe_context base;
 282
 283         int fd;
 284         struct vc4_screen *screen;
 285
 286         /** The 3D rendering job for the currently bound FBO. */
 287         struct vc4_job *job;
 288
 289         /* Map from struct vc4_job_key to the job for that FBO.
 290          */
 291         struct hash_table *jobs;
 292
 293         /**
 294          * Map from vc4_resource to a job writing to that resource.
 295          *
 296          * Primarily for flushing jobs rendering to textures that are now
 297          * being read from.
 298          */
 299         struct hash_table *write_jobs;
 300
 301         struct slab_child_pool transfer_pool;
 302         struct blitter_context *blitter;
 303
 304         /** bitfield of VC4_DIRTY_* */
 305         uint32_t dirty;
 306
 307         struct primconvert_context *primconvert;
 308
 309         struct hash_table *fs_cache, *vs_cache;
 310         struct set *fs_inputs_set;
 311         uint32_t next_uncompiled_program_id;
 312         uint64_t next_compiled_program_id;
 313
 314         struct ra_regs *regs;
 315         unsigned int reg_class_any;
 316         unsigned int reg_class_a_or_b_or_acc;
 317         unsigned int reg_class_r0_r3;
 318         unsigned int reg_class_r4_or_a;
 319         unsigned int reg_class_a;
 320
 321         uint8_t prim_mode;
 322
 323         /** Maximum index buffer valid for the current shader_rec. */
 324         uint32_t max_index;
 325         /** Last index bias baked into the current shader_rec. */
 326         uint32_t last_index_bias;
 327
 328         /** Seqno of the last CL flush's job. */
 329         uint64_t last_emit_seqno;
 330
 331         struct u_upload_mgr *uploader;
 332
 333         /** @{ Current pipeline state objects */
 334         struct pipe_scissor_state scissor;
 335         struct pipe_blend_state *blend;
 336         struct vc4_rasterizer_state *rasterizer;
 337         struct vc4_depth_stencil_alpha_state *zsa;
 338
 339         struct vc4_texture_stateobj verttex, fragtex;
 340
 341         struct vc4_program_stateobj prog;
 342
 343         struct vc4_vertex_stateobj *vtx;
 344
 345         struct {
 346                 struct pipe_blend_color f;
 347                 uint8_t ub[4];
 348         } blend_color;
 349         struct pipe_stencil_ref stencil_ref;
 350         unsigned sample_mask;
 351         struct pipe_framebuffer_state framebuffer;
 352         struct pipe_poly_stipple stipple;
 353         struct pipe_clip_state clip;
 354         struct pipe_viewport_state viewport;
 355         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 356         struct vc4_vertexbuf_stateobj vertexbuf;
 357         struct pipe_index_buffer indexbuf;
 358         /** @} */
 359 };
 360
 361 struct vc4_rasterizer_state {
 362         struct pipe_rasterizer_state base;
 363
 364         /* VC4_CONFIGURATION_BITS */
 365         uint8_t config_bits[3];
 366
 367         float point_size;
 368
 369         /**
 370          * Half-float (1/8/7 bits) value of polygon offset units for
 371          * VC4_PACKET_DEPTH_OFFSET
 372          */
 373         uint16_t offset_units;
 374         /**
 375          * Half-float (1/8/7 bits) value of polygon offset scale for
 376          * VC4_PACKET_DEPTH_OFFSET
 377          */
 378         uint16_t offset_factor;
 379 };
 380
 381 struct vc4_depth_stencil_alpha_state {
 382         struct pipe_depth_stencil_alpha_state base;
 383
 384         /* VC4_CONFIGURATION_BITS */
 385         uint8_t config_bits[3];
 386
 387         /** Uniforms for stencil state.
 388          *
 389          * Index 0 is either the front config, or the front-and-back config.
 390          * Index 1 is the back config if doing separate back stencil.
 391          * Index 2 is the writemask config if it's not a common mask value.
 392          */
 393         uint32_t stencil_uniforms[3];
 394 };
 395
 396 #define perf_debug(...) do {                            \
 397         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
 398                 fprintf(stderr, __VA_ARGS__);           \
 399 } while (0)
 400
 401 static inline struct vc4_context *
 402 vc4_context(struct pipe_context *pcontext)
 403 {
 404         return (struct vc4_context *)pcontext;
 405 }
 406
 407 static inline struct vc4_sampler_view *
 408 vc4_sampler_view(struct pipe_sampler_view *psview)
 409 {
 410         return (struct vc4_sampler_view *)psview;
 411 }
 412
 413 static inline struct vc4_sampler_state *
 414 vc4_sampler_state(struct pipe_sampler_state *psampler)
 415 {
 416         return (struct vc4_sampler_state *)psampler;
 417 }
 418
 419 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 420                                         void *priv, unsigned flags);
 421 void vc4_draw_init(struct pipe_context *pctx);
 422 void vc4_state_init(struct pipe_context *pctx);
 423 void vc4_program_init(struct pipe_context *pctx);
 424 void vc4_program_fini(struct pipe_context *pctx);
 425 void vc4_query_init(struct pipe_context *pctx);
 426 void vc4_simulator_init(struct vc4_screen *screen);
 427 void vc4_simulator_destroy(struct vc4_screen *screen);
 428 int vc4_simulator_flush(struct vc4_context *vc4,
 429                         struct drm_vc4_submit_cl *args,
 430                         struct vc4_job *job);
 431 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
 432
 433 static inline int
 434 vc4_ioctl(int fd, unsigned long request, void *arg)
 435 {
 436         if (using_vc4_simulator)
 437                 return vc4_simulator_ioctl(fd, request, arg);
 438         else
 439                 return drmIoctl(fd, request, arg);
 440 }
 441
 442 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
 443 void vc4_write_uniforms(struct vc4_context *vc4,
 444                         struct vc4_compiled_shader *shader,
 445                         struct vc4_constbuf_stateobj *cb,
 446                         struct vc4_texture_stateobj *texstate);
 447
 448 void vc4_flush(struct pipe_context *pctx);
 449 void vc4_job_init(struct vc4_context *vc4);
 450 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 451                             struct pipe_surface *cbuf,
 452                             struct pipe_surface *zsbuf);
 453 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
 454
 455 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
 456 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
 457                                      struct pipe_resource *prsc);
 458 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
 459                                      struct pipe_resource *prsc);
 460 void vc4_emit_state(struct pipe_context *pctx);
 461 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 462 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 463 void vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 464
 465 bool vc4_rt_format_supported(enum pipe_format f);
 466 bool vc4_rt_format_is_565(enum pipe_format f);
 467 bool vc4_tex_format_supported(enum pipe_format f);
 468 uint8_t vc4_get_tex_format(enum pipe_format f);
 469 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 470 void vc4_init_query_functions(struct vc4_context *vc4);
 471 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 472 void vc4_blitter_save(struct vc4_context *vc4);
 473 #endif /* VC4_CONTEXT_H */