src/gallium/drivers/vc4/vc4_context.h

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC4_CONTEXT_H
  26 #define VC4_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/slab.h"
  33 #include "xf86drm.h"
  34
  35 #define __user
  36 #include "vc4_drm.h"
  37 #include "vc4_bufmgr.h"
  38 #include "vc4_resource.h"
  39 #include "vc4_cl.h"
  40 #include "vc4_qir.h"
  41
  42 #ifdef USE_VC4_SIMULATOR
  43 #define using_vc4_simulator true
  44 #else
  45 #define using_vc4_simulator false
  46 #endif
  47
  48 #define VC4_DIRTY_BLEND         (1 <<  0)
  49 #define VC4_DIRTY_RASTERIZER    (1 <<  1)
  50 #define VC4_DIRTY_ZSA           (1 <<  2)
  51 #define VC4_DIRTY_FRAGTEX       (1 <<  3)
  52 #define VC4_DIRTY_VERTTEX       (1 <<  4)
  53
  54 #define VC4_DIRTY_BLEND_COLOR   (1 <<  7)
  55 #define VC4_DIRTY_STENCIL_REF   (1 <<  8)
  56 #define VC4_DIRTY_SAMPLE_MASK   (1 <<  9)
  57 #define VC4_DIRTY_FRAMEBUFFER   (1 << 10)
  58 #define VC4_DIRTY_STIPPLE       (1 << 11)
  59 #define VC4_DIRTY_VIEWPORT      (1 << 12)
  60 #define VC4_DIRTY_CONSTBUF      (1 << 13)
  61 #define VC4_DIRTY_VTXSTATE      (1 << 14)
  62 #define VC4_DIRTY_VTXBUF        (1 << 15)
  63 #define VC4_DIRTY_INDEXBUF      (1 << 16)
  64 #define VC4_DIRTY_SCISSOR       (1 << 17)
  65 #define VC4_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  66 #define VC4_DIRTY_PRIM_MODE     (1 << 19)
  67 #define VC4_DIRTY_CLIP          (1 << 20)
  68 #define VC4_DIRTY_UNCOMPILED_VS (1 << 21)
  69 #define VC4_DIRTY_UNCOMPILED_FS (1 << 22)
  70 #define VC4_DIRTY_COMPILED_CS   (1 << 23)
  71 #define VC4_DIRTY_COMPILED_VS   (1 << 24)
  72 #define VC4_DIRTY_COMPILED_FS   (1 << 25)
  73 #define VC4_DIRTY_FS_INPUTS     (1 << 26)
  74
  75 struct vc4_sampler_view {
  76         struct pipe_sampler_view base;
  77         uint32_t texture_p0;
  78         uint32_t texture_p1;
  79         bool force_first_level;
  80 };
  81
  82 struct vc4_sampler_state {
  83         struct pipe_sampler_state base;
  84         uint32_t texture_p1;
  85 };
  86
  87 struct vc4_texture_stateobj {
  88         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  89         unsigned num_textures;
  90         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  91         unsigned num_samplers;
  92 };
  93
  94 struct vc4_shader_uniform_info {
  95         enum quniform_contents *contents;
  96         uint32_t *data;
  97         uint32_t count;
  98         uint32_t num_texture_samples;
  99 };
 100
 101 struct vc4_uncompiled_shader {
 102         /** A name for this program, so you can track it in shader-db output. */
 103         uint32_t program_id;
 104         /** How many variants of this program were compiled, for shader-db. */
 105         uint32_t compiled_variant_count;
 106         struct pipe_shader_state base;
 107 };
 108
 109 struct vc4_ubo_range {
 110         /**
 111          * offset in bytes from the start of the ubo where this range is
 112          * uploaded.
 113          *
 114          * Only set once used is set.
 115          */
 116         uint32_t dst_offset;
 117
 118         /**
 119          * offset in bytes from the start of the gallium uniforms where the
 120          * data comes from.
 121          */
 122         uint32_t src_offset;
 123
 124         /** size in bytes of this ubo range */
 125         uint32_t size;
 126 };
 127
 128 struct vc4_fs_inputs {
 129         /**
 130          * Array of the meanings of the VPM inputs this shader needs.
 131          *
 132          * It doesn't include those that aren't part of the VPM, like
 133          * point/line coordinates.
 134          */
 135         struct vc4_varying_slot *input_slots;
 136         uint32_t num_inputs;
 137 };
 138
 139 struct vc4_compiled_shader {
 140         uint64_t program_id;
 141         struct vc4_bo *bo;
 142
 143         struct vc4_shader_uniform_info uniforms;
 144
 145         struct vc4_ubo_range *ubo_ranges;
 146         uint32_t num_ubo_ranges;
 147         uint32_t ubo_size;
 148         /**
 149          * VC4_DIRTY_* flags that, when set in vc4->dirty, mean that the
 150          * uniforms have to be rewritten (and therefore the shader state
 151          * reemitted).
 152          */
 153         uint32_t uniform_dirty_bits;
 154
 155         /** bitmask of which inputs are color inputs, for flat shade handling. */
 156         uint32_t color_inputs;
 157
 158         bool disable_early_z;
 159
 160         /* Set if the compile failed, likely due to register allocation
 161          * failure.  In this case, we have no shader to run and should not try
 162          * to do any draws.
 163          */
 164         bool failed;
 165
 166         bool fs_threaded;
 167
 168         uint8_t num_inputs;
 169
 170         /* Byte offsets for the start of the vertex attributes 0-7, and the
 171          * total size as "attribute" 8.
 172          */
 173         uint8_t vattr_offsets[9];
 174         uint8_t vattrs_live;
 175
 176         const struct vc4_fs_inputs *fs_inputs;
 177 };
 178
 179 struct vc4_program_stateobj {
 180         struct vc4_uncompiled_shader *bind_vs, *bind_fs;
 181         struct vc4_compiled_shader *cs, *vs, *fs;
 182 };
 183
 184 struct vc4_constbuf_stateobj {
 185         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 186         uint32_t enabled_mask;
 187         uint32_t dirty_mask;
 188 };
 189
 190 struct vc4_vertexbuf_stateobj {
 191         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 192         unsigned count;
 193         uint32_t enabled_mask;
 194         uint32_t dirty_mask;
 195 };
 196
 197 struct vc4_vertex_stateobj {
 198         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 199         unsigned num_elements;
 200 };
 201
 202 /* Hash table key for vc4->jobs */
 203 struct vc4_job_key {
 204         struct pipe_surface *cbuf;
 205         struct pipe_surface *zsbuf;
 206 };
 207
 208 /**
 209  * A complete bin/render job.
 210  *
 211  * This is all of the state necessary to submit a bin/render to the kernel.
 212  * We want to be able to have multiple in progress at a time, so that we don't
 213  * need to flush an existing CL just to switch to rendering to a new render
 214  * target (which would mean reading back from the old render target when
 215  * starting to render to it again).
 216  */
 217 struct vc4_job {
 218         struct vc4_cl bcl;
 219         struct vc4_cl shader_rec;
 220         struct vc4_cl uniforms;
 221         struct vc4_cl bo_handles;
 222         struct vc4_cl bo_pointers;
 223         uint32_t shader_rec_count;
 224
 225         /** @{ Surfaces to submit rendering for. */
 226         struct pipe_surface *color_read;
 227         struct pipe_surface *color_write;
 228         struct pipe_surface *zs_read;
 229         struct pipe_surface *zs_write;
 230         struct pipe_surface *msaa_color_write;
 231         struct pipe_surface *msaa_zs_write;
 232         /** @} */
 233         /** @{
 234          * Bounding box of the scissor across all queued drawing.
 235          *
 236          * Note that the max values are exclusive.
 237          */
 238         uint32_t draw_min_x;
 239         uint32_t draw_min_y;
 240         uint32_t draw_max_x;
 241         uint32_t draw_max_y;
 242         /** @} */
 243         /** @{
 244          * Width/height of the color framebuffer being rendered to,
 245          * for VC4_TILE_RENDERING_MODE_CONFIG.
 246         */
 247         uint32_t draw_width;
 248         uint32_t draw_height;
 249         /** @} */
 250         /** @{ Tile information, depending on MSAA and float color buffer. */
 251         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 252         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 253
 254         uint32_t tile_width; /** @< Width of a tile. */
 255         uint32_t tile_height; /** @< Height of a tile. */
 256         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 257         bool msaa;
 258         /** @} */
 259
 260         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 261          * first rendering.
 262          */
 263         uint32_t cleared;
 264         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 265          * (either clears or draws).
 266          */
 267         uint32_t resolve;
 268         uint32_t clear_color[2];
 269         uint32_t clear_depth; /**< 24-bit unorm depth */
 270         uint8_t clear_stencil;
 271
 272         /**
 273          * Set if some drawing (triangles, blits, or just a glClear()) has
 274          * been done to the FBO, meaning that we need to
 275          * DRM_IOCTL_VC4_SUBMIT_CL.
 276          */
 277         bool needs_flush;
 278
 279         /**
 280          * Number of draw calls (not counting full buffer clears) queued in
 281          * the current job.
 282          */
 283         uint32_t draw_calls_queued;
 284
 285         struct vc4_job_key key;
 286 };
 287
 288 struct vc4_context {
 289         struct pipe_context base;
 290
 291         int fd;
 292         struct vc4_screen *screen;
 293
 294         /** The 3D rendering job for the currently bound FBO. */
 295         struct vc4_job *job;
 296
 297         /* Map from struct vc4_job_key to the job for that FBO.
 298          */
 299         struct hash_table *jobs;
 300
 301         /**
 302          * Map from vc4_resource to a job writing to that resource.
 303          *
 304          * Primarily for flushing jobs rendering to textures that are now
 305          * being read from.
 306          */
 307         struct hash_table *write_jobs;
 308
 309         struct slab_child_pool transfer_pool;
 310         struct blitter_context *blitter;
 311
 312         /** bitfield of VC4_DIRTY_* */
 313         uint32_t dirty;
 314
 315         struct primconvert_context *primconvert;
 316
 317         struct hash_table *fs_cache, *vs_cache;
 318         struct set *fs_inputs_set;
 319         uint32_t next_uncompiled_program_id;
 320         uint64_t next_compiled_program_id;
 321
 322         struct ra_regs *regs;
 323         unsigned int reg_class_any[2];
 324         unsigned int reg_class_a_or_b[2];
 325         unsigned int reg_class_a_or_b_or_acc[2];
 326         unsigned int reg_class_r0_r3;
 327         unsigned int reg_class_r4_or_a[2];
 328         unsigned int reg_class_a[2];
 329
 330         uint8_t prim_mode;
 331
 332         /** Maximum index buffer valid for the current shader_rec. */
 333         uint32_t max_index;
 334         /** Last index bias baked into the current shader_rec. */
 335         uint32_t last_index_bias;
 336
 337         /** Seqno of the last CL flush's job. */
 338         uint64_t last_emit_seqno;
 339
 340         struct u_upload_mgr *uploader;
 341
 342         /** @{ Current pipeline state objects */
 343         struct pipe_scissor_state scissor;
 344         struct pipe_blend_state *blend;
 345         struct vc4_rasterizer_state *rasterizer;
 346         struct vc4_depth_stencil_alpha_state *zsa;
 347
 348         struct vc4_texture_stateobj verttex, fragtex;
 349
 350         struct vc4_program_stateobj prog;
 351
 352         struct vc4_vertex_stateobj *vtx;
 353
 354         struct {
 355                 struct pipe_blend_color f;
 356                 uint8_t ub[4];
 357         } blend_color;
 358         struct pipe_stencil_ref stencil_ref;
 359         unsigned sample_mask;
 360         struct pipe_framebuffer_state framebuffer;
 361         struct pipe_poly_stipple stipple;
 362         struct pipe_clip_state clip;
 363         struct pipe_viewport_state viewport;
 364         struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 365         struct vc4_vertexbuf_stateobj vertexbuf;
 366         struct pipe_index_buffer indexbuf;
 367         /** @} */
 368 };
 369
 370 struct vc4_rasterizer_state {
 371         struct pipe_rasterizer_state base;
 372
 373         /* VC4_CONFIGURATION_BITS */
 374         uint8_t config_bits[3];
 375
 376         float point_size;
 377
 378         /**
 379          * Half-float (1/8/7 bits) value of polygon offset units for
 380          * VC4_PACKET_DEPTH_OFFSET
 381          */
 382         uint16_t offset_units;
 383         /**
 384          * Half-float (1/8/7 bits) value of polygon offset scale for
 385          * VC4_PACKET_DEPTH_OFFSET
 386          */
 387         uint16_t offset_factor;
 388 };
 389
 390 struct vc4_depth_stencil_alpha_state {
 391         struct pipe_depth_stencil_alpha_state base;
 392
 393         /* VC4_CONFIGURATION_BITS */
 394         uint8_t config_bits[3];
 395
 396         /** Uniforms for stencil state.
 397          *
 398          * Index 0 is either the front config, or the front-and-back config.
 399          * Index 1 is the back config if doing separate back stencil.
 400          * Index 2 is the writemask config if it's not a common mask value.
 401          */
 402         uint32_t stencil_uniforms[3];
 403 };
 404
 405 #define perf_debug(...) do {                            \
 406         if (unlikely(vc4_debug & VC4_DEBUG_PERF))       \
 407                 fprintf(stderr, __VA_ARGS__);           \
 408 } while (0)
 409
 410 static inline struct vc4_context *
 411 vc4_context(struct pipe_context *pcontext)
 412 {
 413         return (struct vc4_context *)pcontext;
 414 }
 415
 416 static inline struct vc4_sampler_view *
 417 vc4_sampler_view(struct pipe_sampler_view *psview)
 418 {
 419         return (struct vc4_sampler_view *)psview;
 420 }
 421
 422 static inline struct vc4_sampler_state *
 423 vc4_sampler_state(struct pipe_sampler_state *psampler)
 424 {
 425         return (struct vc4_sampler_state *)psampler;
 426 }
 427
 428 struct pipe_context *vc4_context_create(struct pipe_screen *pscreen,
 429                                         void *priv, unsigned flags);
 430 void vc4_draw_init(struct pipe_context *pctx);
 431 void vc4_state_init(struct pipe_context *pctx);
 432 void vc4_program_init(struct pipe_context *pctx);
 433 void vc4_program_fini(struct pipe_context *pctx);
 434 void vc4_query_init(struct pipe_context *pctx);
 435 void vc4_simulator_init(struct vc4_screen *screen);
 436 void vc4_simulator_destroy(struct vc4_screen *screen);
 437 int vc4_simulator_flush(struct vc4_context *vc4,
 438                         struct drm_vc4_submit_cl *args,
 439                         struct vc4_job *job);
 440 int vc4_simulator_ioctl(int fd, unsigned long request, void *arg);
 441 void vc4_simulator_open_from_handle(int fd, uint32_t winsys_stride,
 442                                     int handle, uint32_t size);
 443
 444 static inline int
 445 vc4_ioctl(int fd, unsigned long request, void *arg)
 446 {
 447         if (using_vc4_simulator)
 448                 return vc4_simulator_ioctl(fd, request, arg);
 449         else
 450                 return drmIoctl(fd, request, arg);
 451 }
 452
 453 void vc4_set_shader_uniform_dirty_flags(struct vc4_compiled_shader *shader);
 454 void vc4_write_uniforms(struct vc4_context *vc4,
 455                         struct vc4_compiled_shader *shader,
 456                         struct vc4_constbuf_stateobj *cb,
 457                         struct vc4_texture_stateobj *texstate);
 458
 459 void vc4_flush(struct pipe_context *pctx);
 460 void vc4_job_init(struct vc4_context *vc4);
 461 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 462                             struct pipe_surface *cbuf,
 463                             struct pipe_surface *zsbuf);
 464 struct vc4_job *vc4_get_job_for_fbo(struct vc4_context *vc4);
 465
 466 void vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job);
 467 void vc4_flush_jobs_writing_resource(struct vc4_context *vc4,
 468                                      struct pipe_resource *prsc);
 469 void vc4_flush_jobs_reading_resource(struct vc4_context *vc4,
 470                                      struct pipe_resource *prsc);
 471 void vc4_emit_state(struct pipe_context *pctx);
 472 void vc4_generate_code(struct vc4_context *vc4, struct vc4_compile *c);
 473 struct qpu_reg *vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c);
 474 bool vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode);
 475
 476 bool vc4_rt_format_supported(enum pipe_format f);
 477 bool vc4_rt_format_is_565(enum pipe_format f);
 478 bool vc4_tex_format_supported(enum pipe_format f);
 479 uint8_t vc4_get_tex_format(enum pipe_format f);
 480 const uint8_t *vc4_get_format_swizzle(enum pipe_format f);
 481 void vc4_init_query_functions(struct vc4_context *vc4);
 482 void vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 483 void vc4_blitter_save(struct vc4_context *vc4);
 484 #endif /* VC4_CONTEXT_H */